Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance
common in today's circuits. Also, 0.01 uF caps are less expensive and take up less space (0805 vs. 1206). Huh? Why would you use a 1206 0.1uf for anything unless you needed 50WVDC or more rating? Everything I have read on bypassing for digital says to use 0603 or smaller parts since they have lower inductance, and at the moment 0603 is the most cost effective. On a current design I have 0603 0.1uf, 0.01uf and smaller, 0805 1uf and 1210 10uf ceramic caps, besides the larger tantalums. The operative phrase above is at the moment. Well, at the moment I did my cost/size comparison, 0.01 uF 0805 was cheaper than 0.1 uF 1206 and 0805. I suspect this is still the case, at least it was last time I bought a reel of caps. I don't use 0603 parts yet, due to lack of need for them. Maybe soon though. You are correct about smaller case size leading to lower inductance. I also try to minimize the number of distinct parts used in our products, to keep inventory manageable and get as much economy of scale across our product line as we can in a small operation. When I say small, I mean we don't produce a blue-purple-zillion units a year like the chip companies expect us all to do. Most of us are not in the cellphone and video game console business! Whatever happened to the effort to start a Protel User's website with downloadable footprints and such? I remember some enthusiatic discussion about this maybe a year or two ago, but nothing since. And whatever happened to Adbul (Abd ul-Rahman Lomax)? He seems to have dropped of this list. Or maybe he is a DXP user now? Forget Carmen Santiago, Where in the world is Abd ul-Rahman Lomax? Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, June 03, 2003 6:45 PM Subject: Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups
The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal Any comments? Also anyone else losing messages, or is it just my IT department and Lotus Notes? Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups
I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal But then you don't have as good decoupling between your pwr and gnd planes, since they are farther apart. My stackup (as mentioned in an earlier post, and repeated below) gives you copper balance, better decoupling, and your signals are still only 1 layer away from a pwr or gnd plane. And since the pwr and gnd planes are effectively the same thing to high frequencies, a signal being next to a pwr plane is the same as that signal being next to a gnd plane. sig gnd1 pwr1 sig sig gnd2 pwr2 sig While we are on this subject, I like to use 0.01 uF caps for decoupling, not the 0.1 uF caps you frequently see on digital circuits. The reason is that 0.01 uF caps have a higher self-resonance frequency than 0.1 uF caps, which makes them better able to decouple the high-speed transients that are so common in today's circuits. Also, 0.01 uF caps are less expensive and take up less space (0805 vs. 1206). One last comment: DO NOT put vias within your pads. Some folks advocate this in order to reduce the track inductance from the part pin to the via. The problem is that this causes hell for manufacturing. During the reflow process, solder flows down into the via barrel, away from the part pin/pad junction, resulting in insufficient solder at the junction. Sorry if the previous 2 paragraphs are obvious, but there might be some folks lurking on this list who are new to PCB design and need a rehash of da rules. Or should I say (e)da rules. Whaddaya know, I was on topic this time... Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, June 03, 2003 11:02 AM Subject: Re: [PEDA] six or eight-layer (or more?) stackups The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal Any comments? Also anyone else losing messages, or is it just my IT department and Lotus Notes? Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance
At 03:44 PM 6/3/2003 -0400, you wrote: I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal But then you don't have as good decoupling between your pwr and gnd planes, since they are farther apart. My stackup (as mentioned in an earlier post, and repeated below) gives you copper balance, better decoupling, and your signals are still only 1 layer away from a pwr or gnd plane. And since the pwr and gnd planes are effectively the same thing to high frequencies, a signal being next to a pwr plane is the same as that signal being next to a gnd plane. sig gnd1 pwr1 sig sig gnd2 pwr2 sig While we are on this subject, I like to use 0.01 uF caps for decoupling, not the 0.1 uF caps you frequently see on digital circuits. The reason is that 0.01 uF caps have a higher self-resonance frequency than 0.1 uF caps, which makes them better able to decouple the high-speed transients that are so common in today's circuits. Also, 0.01 uF caps are less expensive and take up less space (0805 vs. 1206). First, my experience regarding layout is minimal at best since I seem to exhaust all the wrong ways first. I once took a class in multilayer layout and was told that the capacitance between the power/ground planes themselves was sufficient for decoupling high frequencies and that adding capacitors could cause tuned circuits and troublesome resonances. I'm simply asking, any views on that theory? Ray * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance
First, my experience regarding layout is minimal at best since I seem to exhaust all the wrong ways first. I once took a class in multilayer layout and was told that the capacitance between the power/ground planes themselves was sufficient for decoupling high frequencies and that adding pacitors could cause tuned circuits and troublesome resonances. I'm simply asking, any views on that theory? That may be true at very low frequencies like 74LSxx parts, but as the edge rate goes up the capacitance needs to be closer to the pin. Most manufacturers today say to put decoupling capacitors as close to the power pins as possible and they try to make a power and ground such that the cap can be attached to both pins. common in today's circuits. Also, 0.01 uF caps are less expensive and take up less space (0805 vs. 1206). Huh? Why would you use a 1206 0.1uf for anything unless you needed 50WVDC or more rating? Everything I have read on bypassing for digital says to use 0603 or smaller parts since they have lower inductance, and at the moment 0603 is the most cost effective. On a current design I have 0603 0.1uf, 0.01uf and smaller, 0805 1uf and 1210 10uf ceramic caps, besides the larger tantalums. The previous designers, who no longer work for us, used 1210 0.1uf for all the bypassing and they put them on the other side of the board far away from the power pins with really small traces so they'd be comletely useless. It really makes life suck now that we need to get RFI compliance testing done, especially when they routed digital across ground plane cuts and routed ADC power on traces that snake all over the board, and...I'm going home for a beer. Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance
Ray, It is indeed possible to design a board where no external caps are required BUT there are major caveats! An interplane capacitor is indeed the best cap you'll ever get on a board however the total capacitance available is limited. This means that your design must be capable of working with this little capacitance. e.g. a chip drawing 30W at 3V rail (i.e. 10A average current), clocking at 1GHz will require 0.01uC of charge per clock cycle. If the maximum voltage ripple allowed is 10% then this chip requires a minimum of 33nF decoupling cap. Note that this minimum is what's needed for an AVERAGE current draw - most chips include state transitions where peak currents are much higher, so more capacitance is needed in order to support these peak transitions. So, provided that you can satisfy both the average and peak current requirements of your board with the available interplane cap, you don't really need any discretes. There aren't too many designs that I do where this is possible, though. I have seen it done quite successfully - one tantalum at the power connector was all there was. In most boards, there is a need for discrete caps to support lower frequency charge storage. Once these are on the board you WILL get resonances developing between the interplane cap and the bulk caps. The only ways to prevent these resonant nulls from getting in the way are: 1/ Find out where the nulls are and ensure that they aren't coincident with frequencies of interest (remembering to cater for all process and component tolerance spreads), or 2/ Use a spread of capacitor values so that you swap one or two deep resonant nulls for a swag of shallower ones spread across the spectrum. Most designers go for option 2 since time pressure seems to get in the way of designing and testing option 1 properly! Remember that, if you use only one cap value (like 0.01uF) for all your bypassing, you will get a very deep resonance null that may be where you don't want it. Cheers, John Haddy -Original Message- From: Ray Mitchell [mailto:[EMAIL PROTECTED] Sent: Wednesday, 4 June 2003 6:25 AM To: Protel EDA Forum Subject: Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance At 03:44 PM 6/3/2003 -0400, you wrote: I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal But then you don't have as good decoupling between your pwr and gnd planes, since they are farther apart. My stackup (as mentioned in an earlier post, and repeated below) gives you copper balance, better decoupling, and your signals are still only 1 layer away from a pwr or gnd plane. And since the pwr and gnd planes are effectively the same thing to high frequencies, a signal being next to a pwr plane is the same as that signal being next to a gnd plane. sig gnd1 pwr1 sig sig gnd2 pwr2 sig While we are on this subject, I like to use 0.01 uF caps for decoupling, not the 0.1 uF caps you frequently see on digital circuits. The reason is that 0.01 uF caps have a higher self-resonance frequency than 0.1 uF caps, which makes them better able to decouple the high-speed transients that are so common in today's circuits. Also, 0.01 uF caps are less expensive and take up less space (0805 vs. 1206). First, my experience regarding layout is minimal at best since I seem to exhaust all the wrong ways first. I once took a class in multilayer layout and was told that the capacitance between the power/ground planes themselves was sufficient for decoupling high frequencies and that adding capacitors could cause tuned circuits and troublesome resonances. I'm simply asking, any views on that theory? Ray * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups
Bagotronix Tech Support wrote: I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal But then you don't have as good decoupling between your pwr and gnd planes, since they are farther apart. My stackup (as mentioned in an earlier post, and repeated below) gives you copper balance, better decoupling, and your signals are still only 1 layer away from a pwr or gnd plane. And since the pwr and gnd planes are effectively the same thing to high frequencies, a signal being next to a pwr plane is the same as that signal being next to a gnd plane. sig gnd1 pwr1 sig sig gnd2 pwr2 sig While we are on this subject, I like to use 0.01 uF caps for decoupling, not the 0.1 uF caps you frequently see on digital circuits. The reason is that 0.01 uF caps have a higher self-resonance frequency than 0.1 uF caps, which makes them better able to decouple the high-speed transients that are so common in today's circuits. Also, 0.01 uF caps are less expensive and take up less space (0805 vs. 1206). One last comment: DO NOT put vias within your pads. Some folks advocate this in order to reduce the track inductance from the part pin to the via. The problem is that this causes hell for manufacturing. During the reflow process, solder flows down into the via barrel, away from the part pin/pad junction, resulting in insufficient solder at the junction. Have to agree with the above paragraph. We did our first bga board a few months ago and all the solder flowed through the vias creating a few no conductive connections even thou they appeared connected after x-raying. Lucky for us they were only prototypye boards. Sorry if the previous 2 paragraphs are obvious, but there might be some folks lurking on this list who are new to PCB design and need a rehash of da rules. Or should I say (e)da rules. I have to say I am a newbie to multi-layer boards and high speed / RF so even thou it may seem obvious to everyone else alot of this is all new to me and probale others out there as well. Whaddaya know, I was on topic this time... Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, June 03, 2003 11:02 AM Subject: Re: [PEDA] six or eight-layer (or more?) stackups The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal Any comments? Also anyone else losing messages, or is it just my IT department and Lotus Notes? Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- -- Nathan Horsfield Inspiration Technology P/L Ph: +61 8 8211 9668 Fax: +61 8 8211 9658 www.instech.com.au * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups
At 10:57 AM 6/3/2003 +0930, you wrote: Michael The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal thou never actually using 8 layers this is all i can give you. Hope it helps. Out of curiosity, what is the typical textbook stackup for a six-layer board? Do you typically have two signal, two power, two ground planes, or can you have, say, three signals layers and two power and one ground plane? i.e. 1. signal 2. gnd 3. pwr 4. signal 5. pwr 6. signal I would imagine this should be fine if there are no plane splits, save for possibly some on 3, since all signal layers would be directly adjacent to at least one unbroken plane... Or is my thinking flawed on this? Four layer is easy, and eight makes sense... But how do you typically work up the more oddball ones like six or ten or (shudder) even twenty two? I am looking at a design now that I think will probably require at least three signal layers to route, but I think an eight-layer board would be something of an overkill and would like to stick to six. How do folks typically deal with distributing power to parts that require separate core and I/O, maybe different cores for different parts on the board? For instance, multiple FPGAs that require a 2.5v core and 3.3v IO, and a DSP which requires a 1.8v core and 3.3v IO? Obviously 3.3v should probably have it's own power plane across the board, but can you take an inner power layer (like #3 in the above example) and split it between 1.8v and 2.5v as needed to source the core voltages as and where needed? I've done four layer boards fine this far; my approach (under QFP FPGAs that required 2.5v core and 3.3v IO) was to pour a polygon-plane on the top signal layer under the chip, and to connect this to all of the necessary pins, decouple the living daylights out of it, and then run a very fat trace on the back of the board over to the 2.5v regulator. It seems to have worked just fine on the latest run of boards - very clean power being supplied to all of the core pins - but I'm always interested in other's approaches that may be better suited to these kinds of situations. Someone really needs to write a modern 'style guide' to multilayer PCB layout, y'know? Not just the math and theory covered in several of the better books out there, but one also covering component layout techniques, approaches to signal and bus routing, shapes and patterns of via layout for moving busses from one layer to the other nicely, how to route *special* signals (differential, controlled impedance, matched length, etc), how to efficiently break out BGAs, and so forth. Certainly would make life a little easier for us newbies! :D Regards, -- Matt * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups
If you used the construction you suggest you'd encounter a problem with copper balance. It would appear either during board manufacture or reflow, or both. The mass of copper on 2/3 is different to 4/5 so the board will be badly bent or twisted. (The coefficient of expansion of copper is different to prepreg and FR4). The forces generated on a layer during heating depend on the density of copper in any given area. If you want a guide to PCB lay-up, I suggest you talk to your board house. Ours publishes a really useful guide, see www.graphic.plc.uk Each houses capabilities differ depending on their techniques and equipment, though there are general industry and practical rules too. Jason. -Original Message- From: Matt Polak [mailto:[EMAIL PROTECTED] Sent: 03 June 2003 10:12 To: Protel EDA Forum Subject: Re: [PEDA] six or eight-layer (or more?) stackups At 10:57 AM 6/3/2003 +0930, you wrote: Michael The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal thou never actually using 8 layers this is all i can give you. Hope it helps. Out of curiosity, what is the typical textbook stackup for a six-layer board? Do you typically have two signal, two power, two ground planes, or can you have, say, three signals layers and two power and one ground plane? i.e. 1. signal 2. gnd 3. pwr 4. signal 5. pwr 6. signal I would imagine this should be fine if there are no plane splits, save for possibly some on 3, since all signal layers would be directly adjacent to at least one unbroken plane... Or is my thinking flawed on this? Four layer is easy, and eight makes sense... But how do you typically work up the more oddball ones like six or ten or (shudder) even twenty two? I am looking at a design now that I think will probably require at least three signal layers to route, but I think an eight-layer board would be something of an overkill and would like to stick to six. How do folks typically deal with distributing power to parts that require separate core and I/O, maybe different cores for different parts on the board? For instance, multiple FPGAs that require a 2.5v core and 3.3v IO, and a DSP which requires a 1.8v core and 3.3v IO? Obviously 3.3v should probably have it's own power plane across the board, but can you take an inner power layer (like #3 in the above example) and split it between 1.8v and 2.5v as needed to source the core voltages as and where needed? I've done four layer boards fine this far; my approach (under QFP FPGAs that required 2.5v core and 3.3v IO) was to pour a polygon-plane on the top signal layer under the chip, and to connect this to all of the necessary pins, decouple the living daylights out of it, and then run a very fat trace on the back of the board over to the 2.5v regulator. It seems to have worked just fine on the latest run of boards - very clean power being supplied to all of the core pins - but I'm always interested in other's approaches that may be better suited to these kinds of situations. Someone really needs to write a modern 'style guide' to multilayer PCB layout, y'know? Not just the math and theory covered in several of the better books out there, but one also covering component layout techniques, approaches to signal and bus routing, shapes and patterns of via layout for moving busses from one layer to the other nicely, how to route *special* signals (differential, controlled impedance, matched length, etc), how to efficiently break out BGAs, and so forth. Certainly would make life a little easier for us newbies! :D Regards, -- Matt * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups
Matt Polak wrote: At 10:57 AM 6/3/2003 +0930, you wrote: Michael The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal thou never actually using 8 layers this is all i can give you. Hope it helps. Out of curiosity, what is the typical textbook stackup for a six-layer board? Do you typically have two signal, two power, two ground planes, or can you have, say, three signals layers and two power and one ground plane? i.e. 1. signal 2. gnd 3. pwr 4. signal 5. pwr 6. signal I would imagine this should be fine if there are no plane splits, save for possibly some on 3, since all signal layers would be directly adjacent to at least one unbroken plane... Or is my thinking flawed on this? Four layer is easy, and eight makes sense... But how do you typically work up the more oddball ones like six or ten or (shudder) even twenty two? I am looking at a design now that I think will probably require at least three signal layers to route, but I think an eight-layer board would be something of an overkill and would like to stick to six. How do folks typically deal with distributing power to parts that require separate core and I/O, maybe different cores for different parts on the board? For instance, multiple FPGAs that require a 2.5v core and 3.3v IO, and a DSP which requires a 1.8v core and 3.3v IO? Obviously 3.3v should probably have it's own power plane across the board, but can you take an inner power layer (like #3 in the above example) and split it between 1.8v and 2.5v as needed to source the core voltages as and where needed? I've done four layer boards fine this far; my approach (under QFP FPGAs that required 2.5v core and 3.3v IO) was to pour a polygon-plane on the top signal layer under the chip, and to connect this to all of the necessary pins, decouple the living daylights out of it, and then run a very fat trace on the back of the board over to the 2.5v regulator. It seems to have worked just fine on the latest run of boards - very clean power being supplied to all of the core pins - but I'm always interested in other's approaches that may be better suited to these kinds of situations. Someone really needs to write a modern 'style guide' to multilayer PCB layout, y'know? Not just the math and theory covered in several of the better books out there, but one also covering component layout techniques, approaches to signal and bus routing, shapes and patterns of via layout for moving busses from one layer to the other nicely, how to route *special* signals (differential, controlled impedance, matched length, etc), how to efficiently break out BGAs, and so forth. Certainly would make life a little easier for us newbies! :D Regards, -- Matt the main issue with an odd number of plane is the PCB becomes unbalenced and so is more likely to warp. with the 6 layer setup suggested this should not be to bad but could cause issues, particularly if the middle sugnal layer is lightly used. If you are using a layup where you have an od number of planes then it can often be worth adding some ground flods to the appropriate signal layer to help with the copper balence * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
