Author: David Schneider <david.schnei...@picle.org> Branch: Changeset: r64863:d417faaac238 Date: 2013-06-12 05:46 -0500 http://bitbucket.org/pypy/pypy/changeset/d417faaac238/
Log: rename is_reg method to is_core_reg on location objects diff --git a/rpython/jit/backend/arm/assembler.py b/rpython/jit/backend/arm/assembler.py --- a/rpython/jit/backend/arm/assembler.py +++ b/rpython/jit/backend/arm/assembler.py @@ -113,7 +113,7 @@ tmpreg = r.lr mc.gen_load_int(r.ip.value, self.cpu.pos_exc_value()) if excvalloc is not None: # store - assert excvalloc.is_reg() + assert excvalloc.is_core_reg() self.load_reg(mc, excvalloc, r.ip) if on_frame: # store exc_value in JITFRAME @@ -125,7 +125,7 @@ self.store_reg(mc, r.ip, r.fp, ofs, helper=tmpreg) if exctploc is not None: # store pos_exception in exctploc - assert exctploc.is_reg() + assert exctploc.is_core_reg() mc.gen_load_int(r.ip.value, self.cpu.pos_exception()) self.load_reg(mc, exctploc, r.ip, helper=tmpreg) @@ -146,7 +146,7 @@ tmpreg = r.lr # use lr as a second temporary reg mc.gen_load_int(r.ip.value, self.cpu.pos_exc_value()) if excvalloc is not None: - assert excvalloc.is_reg() + assert excvalloc.is_core_reg() self.store_reg(mc, excvalloc, r.ip) else: assert exctploc is not r.fp @@ -947,7 +947,7 @@ # regalloc support def load(self, loc, value): """load an immediate value into a register""" - assert (loc.is_reg() and value.is_imm() + assert (loc.is_core_reg() and value.is_imm() or loc.is_vfp_reg() and value.is_imm_float()) if value.is_imm(): self.mc.gen_load_int(loc.value, value.getint()) @@ -958,7 +958,7 @@ def load_reg(self, mc, target, base, ofs=0, cond=c.AL, helper=r.ip): if target.is_vfp_reg(): return self._load_vfp_reg(mc, target, base, ofs, cond, helper) - elif target.is_reg(): + elif target.is_core_reg(): return self._load_core_reg(mc, target, base, ofs, cond, helper) def _load_vfp_reg(self, mc, target, base, ofs, cond=c.AL, helper=r.ip): @@ -1012,7 +1012,7 @@ def _mov_imm_to_loc(self, prev_loc, loc, cond=c.AL): if loc.type == FLOAT: raise AssertionError("invalid target for move from imm value") - if loc.is_reg(): + if loc.is_core_reg(): new_loc = loc elif loc.is_stack() or loc.is_raw_sp(): new_loc = r.lr @@ -1027,7 +1027,7 @@ def _mov_reg_to_loc(self, prev_loc, loc, cond=c.AL): if loc.is_imm(): raise AssertionError("mov reg to imm doesn't make sense") - if loc.is_reg(): + if loc.is_core_reg(): self.mc.MOV_rr(loc.value, prev_loc.value, cond=cond) elif loc.is_stack() and loc.type != FLOAT: # spill a core register @@ -1050,7 +1050,7 @@ helper = None offset = prev_loc.value tmp = None - if loc.is_reg(): + if loc.is_core_reg(): assert prev_loc.type != FLOAT, 'trying to load from an \ incompatible location into a core register' # unspill a core register @@ -1126,7 +1126,7 @@ """Moves a value from a previous location to some other location""" if prev_loc.is_imm(): return self._mov_imm_to_loc(prev_loc, loc, cond) - elif prev_loc.is_reg(): + elif prev_loc.is_core_reg(): self._mov_reg_to_loc(prev_loc, loc, cond) elif prev_loc.is_stack(): self._mov_stack_to_loc(prev_loc, loc, cond) @@ -1215,7 +1215,7 @@ scratch_reg = r.vfp_ip self.regalloc_mov(loc, scratch_reg, cond) self.regalloc_push(scratch_reg, cond) - elif loc.is_reg(): + elif loc.is_core_reg(): self.mc.PUSH([loc.value], cond=cond) elif loc.is_vfp_reg(): self.mc.VPUSH([loc.value], cond=cond) @@ -1238,7 +1238,7 @@ scratch_reg = r.vfp_ip self.regalloc_pop(scratch_reg) self.regalloc_mov(scratch_reg, loc) - elif loc.is_reg(): + elif loc.is_core_reg(): self.mc.POP([loc.value], cond=cond) elif loc.is_vfp_reg(): self.mc.VPOP([loc.value], cond=cond) @@ -1306,7 +1306,7 @@ # lengthloc is the length of the array, which we must not modify! assert lengthloc is not r.r0 and lengthloc is not r.r1 - if lengthloc.is_reg(): + if lengthloc.is_core_reg(): varsizeloc = lengthloc else: assert lengthloc.is_stack() diff --git a/rpython/jit/backend/arm/callbuilder.py b/rpython/jit/backend/arm/callbuilder.py --- a/rpython/jit/backend/arm/callbuilder.py +++ b/rpython/jit/backend/arm/callbuilder.py @@ -40,7 +40,7 @@ if self.fnloc.is_stack(): self.asm.mov_loc_loc(self.fnloc, r.ip) self.fnloc = r.ip - assert self.fnloc.is_reg() + assert self.fnloc.is_core_reg() self.mc.BLX(self.fnloc.value) def restore_stack_pointer(self): @@ -135,7 +135,7 @@ return [], [] if self.resloc.is_vfp_reg(): return [r.r0, r.r1], [] - assert self.resloc.is_reg() + assert self.resloc.is_core_reg() return [r.r0], [] def load_result(self): @@ -146,7 +146,7 @@ if resloc.is_vfp_reg(): # move result to the allocated register self.asm.mov_to_vfp_loc(r.r0, r.r1, resloc) - elif resloc.is_reg(): + elif resloc.is_core_reg(): # move result to the allocated register if resloc is not r.r0: self.asm.mov_loc_loc(r.r0, resloc) @@ -283,7 +283,7 @@ def load_result(self): resloc = self.resloc # ensure the result is wellformed and stored in the correct location - if resloc is not None and resloc.is_reg(): + if resloc is not None and resloc.is_core_reg(): self._ensure_result_bit_extension(resloc, self.ressize, self.ressign) @@ -292,7 +292,7 @@ return [], [] if self.resloc.is_vfp_reg(): return [], [r.d0] - assert self.resloc.is_reg() + assert self.resloc.is_core_reg() return [r.r0], [] diff --git a/rpython/jit/backend/arm/helper/assembler.py b/rpython/jit/backend/arm/helper/assembler.py --- a/rpython/jit/backend/arm/helper/assembler.py +++ b/rpython/jit/backend/arm/helper/assembler.py @@ -82,7 +82,7 @@ assert guard is not None l0 = arglocs[0] l1 = arglocs[1] - assert l0.is_reg() + assert l0.is_core_reg() if l1.is_imm(): self.mc.CMP_ri(l0.value, imm=l1.getint(), cond=fcond) diff --git a/rpython/jit/backend/arm/locations.py b/rpython/jit/backend/arm/locations.py --- a/rpython/jit/backend/arm/locations.py +++ b/rpython/jit/backend/arm/locations.py @@ -15,7 +15,7 @@ def is_raw_sp(self): return False - def is_reg(self): + def is_core_reg(self): return False def is_vfp_reg(self): @@ -43,7 +43,7 @@ def __repr__(self): return 'r%d' % self.value - def is_reg(self): + def is_core_reg(self): return True def as_key(self): @@ -62,7 +62,7 @@ def __repr__(self): return 'vfp%d' % self.value - def is_reg(self): + def is_core_reg(self): return False def is_vfp_reg(self): diff --git a/rpython/jit/backend/arm/opassembler.py b/rpython/jit/backend/arm/opassembler.py --- a/rpython/jit/backend/arm/opassembler.py +++ b/rpython/jit/backend/arm/opassembler.py @@ -248,7 +248,7 @@ l1 = arglocs[1] failargs = arglocs[2:] - if l0.is_reg(): + if l0.is_core_reg(): if l1.is_imm(): self.mc.CMP_ri(l0.value, l1.getint()) else: @@ -488,7 +488,7 @@ # case GCFLAG_CARDS_SET: emit a few instructions to do # directly the card flag setting loc_index = arglocs[1] - assert loc_index.is_reg() + assert loc_index.is_core_reg() # must save the register loc_index before it is mutated mc.PUSH([loc_index.value]) tmp1 = loc_index @@ -588,7 +588,7 @@ def emit_op_setarrayitem_gc(self, op, arglocs, regalloc, fcond): value_loc, base_loc, ofs_loc, scale, ofs = arglocs - assert ofs_loc.is_reg() + assert ofs_loc.is_core_reg() if scale.value > 0: self.mc.LSL_ri(r.ip.value, ofs_loc.value, scale.value) ofs_loc = r.ip @@ -606,7 +606,7 @@ # vstr only supports imm offsets # so if the ofset is too large we add it to the base and use an # offset of 0 - if ofs_loc.is_reg(): + if ofs_loc.is_core_reg(): tmploc, save = self.get_tmp_reg([value_loc, base_loc, ofs_loc]) assert not save self.mc.ADD_rr(tmploc.value, base_loc.value, ofs_loc.value) @@ -644,13 +644,13 @@ def emit_op_raw_store(self, op, arglocs, regalloc, fcond): value_loc, base_loc, ofs_loc, scale, ofs = arglocs - assert ofs_loc.is_reg() + assert ofs_loc.is_core_reg() self._write_to_mem(value_loc, base_loc, ofs_loc, scale, fcond) return fcond def emit_op_getarrayitem_gc(self, op, arglocs, regalloc, fcond): res_loc, base_loc, ofs_loc, scale, ofs = arglocs - assert ofs_loc.is_reg() + assert ofs_loc.is_core_reg() signed = op.getdescr().is_item_signed() # scale the offset as required @@ -672,7 +672,7 @@ # vldr only supports imm offsets # if the offset is in a register we add it to the base and use a # tmp reg - if ofs_loc.is_reg(): + if ofs_loc.is_core_reg(): tmploc, save = self.get_tmp_reg([base_loc, ofs_loc]) assert not save self.mc.ADD_rr(tmploc.value, base_loc.value, ofs_loc.value) @@ -727,7 +727,7 @@ def emit_op_raw_load(self, op, arglocs, regalloc, fcond): res_loc, base_loc, ofs_loc, scale, ofs = arglocs - assert ofs_loc.is_reg() + assert ofs_loc.is_core_reg() # no base offset assert ofs.value == 0 signed = op.getdescr().is_item_signed() @@ -805,10 +805,10 @@ bytes_box = TempBox() bytes_loc = regalloc.rm.force_allocate_reg(bytes_box, forbidden_vars) scale = self._get_unicode_item_scale() - if not length_loc.is_reg(): + if not length_loc.is_core_reg(): self.regalloc_mov(length_loc, bytes_loc) length_loc = bytes_loc - assert length_loc.is_reg() + assert length_loc.is_core_reg() self.mc.MOV_ri(r.ip.value, 1 << scale) self.mc.MUL(bytes_loc.value, r.ip.value, length_loc.value) length_box = bytes_box @@ -835,8 +835,8 @@ # result = base_loc + (scaled_loc << scale) + static_offset def _gen_address(self, result, base_loc, scaled_loc, scale=0, static_offset=0): - assert scaled_loc.is_reg() - assert base_loc.is_reg() + assert scaled_loc.is_core_reg() + assert base_loc.is_core_reg() assert check_imm_arg(scale) assert check_imm_arg(static_offset) if scale > 0: @@ -1063,7 +1063,7 @@ def emit_op_cast_float_to_int(self, op, arglocs, regalloc, fcond): arg, res = arglocs assert arg.is_vfp_reg() - assert res.is_reg() + assert res.is_core_reg() self.mc.VCVT_float_to_int(r.vfp_ip.value, arg.value) self.mc.VMOV_rc(res.value, r.ip.value, r.vfp_ip.value) return fcond @@ -1071,7 +1071,7 @@ def emit_op_cast_int_to_float(self, op, arglocs, regalloc, fcond): arg, res = arglocs assert res.is_vfp_reg() - assert arg.is_reg() + assert arg.is_core_reg() self.mc.MOV_ri(r.ip.value, 0) self.mc.VMOV_cr(res.value, arg.value, r.ip.value) self.mc.VCVT_int_to_float(res.value, res.value) @@ -1087,7 +1087,7 @@ loc = arglocs[0] res = arglocs[1] assert loc.is_vfp_reg() - assert res.is_reg() + assert res.is_core_reg() self.mc.VMOV_rc(res.value, r.ip.value, loc.value) return fcond @@ -1108,7 +1108,7 @@ def emit_op_cast_float_to_singlefloat(self, op, arglocs, regalloc, fcond): arg, res = arglocs assert arg.is_vfp_reg() - assert res.is_reg() + assert res.is_core_reg() self.mc.VCVT_f64_f32(r.vfp_ip.value, arg.value) self.mc.VMOV_rc(res.value, r.ip.value, r.vfp_ip.value) return fcond @@ -1116,7 +1116,7 @@ def emit_op_cast_singlefloat_to_float(self, op, arglocs, regalloc, fcond): arg, res = arglocs assert res.is_vfp_reg() - assert arg.is_reg() + assert arg.is_core_reg() self.mc.MOV_ri(r.ip.value, 0) self.mc.VMOV_cr(res.value, arg.value, r.ip.value) self.mc.VCVT_f32_f64(res.value, res.value) diff --git a/rpython/jit/backend/arm/regalloc.py b/rpython/jit/backend/arm/regalloc.py --- a/rpython/jit/backend/arm/regalloc.py +++ b/rpython/jit/backend/arm/regalloc.py @@ -324,7 +324,7 @@ loc = r.fp arg = inputargs[i] i += 1 - if loc.is_reg(): + if loc.is_core_reg(): self.rm.reg_bindings[arg] = loc used[loc] = None elif loc.is_vfp_reg(): @@ -358,7 +358,7 @@ continue if box.type == REF and self.rm.is_still_alive(box): assert not noregs - assert loc.is_reg() + assert loc.is_core_reg() val = loc.value gcmap[val // WORD // 8] |= r_uint(1) << (val % (WORD * 8)) for box, loc in self.fm.bindings.iteritems(): @@ -1154,7 +1154,7 @@ assert isinstance(arg, Box) loc = self.loc(arg) arglocs[i] = loc - if loc.is_reg(): + if loc.is_core_reg(): self.frame_manager.mark_as_free(arg) # descr._arm_arglocs = arglocs diff --git a/rpython/jit/backend/arm/test/test_jump.py b/rpython/jit/backend/arm/test/test_jump.py --- a/rpython/jit/backend/arm/test/test_jump.py +++ b/rpython/jit/backend/arm/test/test_jump.py @@ -255,7 +255,7 @@ else: newvalue = 'value-vfp-%d' % i regs2[loc.value] = newvalue - elif loc.is_reg(): + elif loc.is_core_reg(): regs1[loc.value] = 'value-int-%d' % i elif loc.is_stack(): stack[loc.position] = 'value-width%d-%d' % (loc.width, i) @@ -284,7 +284,7 @@ assert loc.width == expected_width*WORD if loc.is_vfp_reg(): return regs2[loc.value] - elif loc.is_reg(): + elif loc.is_core_reg(): return regs1[loc.value] elif loc.is_stack(): got = stack[loc.position] @@ -298,7 +298,7 @@ def write(loc, newvalue): if loc.is_vfp_reg(): regs2[loc.value] = newvalue - elif loc.is_reg(): + elif loc.is_core_reg(): regs1[loc.value] = newvalue elif loc.is_stack(): if loc.width > WORD: @@ -317,17 +317,17 @@ for op in assembler.ops: if op[0] == 'mov': src, dst = op[1:] - assert src.is_reg() or src.is_vfp_reg() or src.is_stack() or src.is_imm_float() or src.is_imm() - assert dst.is_reg() or dst.is_vfp_reg() or dst.is_stack() + assert src.is_core_reg() or src.is_vfp_reg() or src.is_stack() or src.is_imm_float() or src.is_imm() + assert dst.is_core_reg() or dst.is_vfp_reg() or dst.is_stack() assert not (src.is_stack() and dst.is_stack()) write(dst, read(src)) elif op[0] == 'push': src, = op[1:] - assert src.is_reg() or src.is_vfp_reg() or src.is_stack() + assert src.is_core_reg() or src.is_vfp_reg() or src.is_stack() extrapushes.append(read(src)) elif op[0] == 'pop': dst, = op[1:] - assert dst.is_reg() or dst.is_vfp_reg() or dst.is_stack() + assert dst.is_core_reg() or dst.is_vfp_reg() or dst.is_stack() write(dst, extrapushes.pop()) else: assert 0, "unknown op: %r" % (op,) diff --git a/rpython/jit/backend/llsupport/assembler.py b/rpython/jit/backend/llsupport/assembler.py --- a/rpython/jit/backend/llsupport/assembler.py +++ b/rpython/jit/backend/llsupport/assembler.py @@ -47,7 +47,7 @@ input_i += 1 if arg.type == REF: loc = fail_locs[i] - if loc.is_reg(): + if loc.is_core_reg(): val = self.cpu.all_reg_indexes[loc.value] else: val = loc.get_position() + self.cpu.JITFRAME_FIXED_SIZE diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py --- a/rpython/jit/backend/x86/assembler.py +++ b/rpython/jit/backend/x86/assembler.py @@ -1551,14 +1551,14 @@ frame in jf_guard_exc """ if excvalloc is not None: - assert excvalloc.is_reg() + assert excvalloc.is_core_reg() mc.MOV(excvalloc, heap(self.cpu.pos_exc_value())) elif tmploc is not None: # if both are None, just ignore ofs = self.cpu.get_ofs_of_frame_field('jf_guard_exc') mc.MOV(tmploc, heap(self.cpu.pos_exc_value())) mc.MOV(RawEbpLoc(ofs), tmploc) if exctploc is not None: - assert exctploc.is_reg() + assert exctploc.is_core_reg() mc.MOV(exctploc, heap(self.cpu.pos_exception())) mc.MOV(heap(self.cpu.pos_exception()), imm0) diff --git a/rpython/jit/backend/x86/regloc.py b/rpython/jit/backend/x86/regloc.py --- a/rpython/jit/backend/x86/regloc.py +++ b/rpython/jit/backend/x86/regloc.py @@ -45,7 +45,7 @@ def is_stack(self): return False - def is_reg(self): + def is_core_reg(self): return False def get_position(self): @@ -169,7 +169,7 @@ def is_float(self): return self.is_xmm - def is_reg(self): + def is_core_reg(self): return True class ImmediateAssemblerLocation(AssemblerLocation): _______________________________________________ pypy-commit mailing list pypy-commit@python.org http://mail.python.org/mailman/listinfo/pypy-commit