Author: Armin Rigo <ar...@tunes.org>
Branch:
Changeset: r21:0ffe3584a6d9
Date: 2013-05-26 18:31 +0200
http://bitbucket.org/pypy/stmgc/changeset/0ffe3584a6d9/
Log: Kill CFENCE.
diff --git a/c3/atomic_ops.h b/c3/atomic_ops.h
--- a/c3/atomic_ops.h
+++ b/c3/atomic_ops.h
@@ -13,16 +13,12 @@
#define UNLIKELY(test) __builtin_expect(test, 0)
-/* "compiler fence" for preventing reordering of loads/stores to
- non-volatiles. Should not be used any more. */
-#define CFENCE asm volatile ("":::"memory")
-
#if defined(__amd64__) || defined(__i386__)
-# define smp_wmb() CFENCE
-# define smp_spinloop() asm volatile ("pause")
+# define smp_wmb() asm volatile ("":::"memory")
+# define smp_spinloop() asm volatile ("pause":::"memory")
#elif defined(__powerpc__)
# define smp_wmb() asm volatile ("lwsync":::"memory")
-# define smp_spinloop() /* fill me? */
+# define smp_spinloop() asm volatile ("":::"memory") /* fill me? */
#else
# error "Define smp_wmb() for your architecture"
#endif
@@ -100,18 +96,9 @@
#endif
-static inline void spinloop(void)
-{
- smp_spinloop();
- /* use "memory" here to make sure that gcc will reload the
- relevant data from memory after the spinloop */
- CFENCE;
-}
-
-
#define spinlock_acquire(lock, targetvalue) \
do { if (bool_cas(&(lock), 0, (targetvalue))) break; \
- do { spinloop(); } while (ACCESS_ONCE(lock)); \
+ do { smp_spinloop(); } while (ACCESS_ONCE(lock)); \
} while (1)
#define spinlock_release(lock) \
diff --git a/c3/et.c b/c3/et.c
--- a/c3/et.c
+++ b/c3/et.c
@@ -404,7 +404,7 @@
assert(d->active >= 1);
assert(num < SPINLOOP_REASONS);
d->num_spinloops[num]++;
- spinloop();
+ smp_spinloop();
}
#if 0
diff --git a/c3/nursery.c b/c3/nursery.c
--- a/c3/nursery.c
+++ b/c3/nursery.c
@@ -815,7 +815,7 @@
while (1) {
count = ACCESS_ONCE(d->debug_nursery_access);
if (count == (revision_t)-1) {
- spinloop();
+ smp_spinloop();
continue;
}
if (bool_cas(&d->debug_nursery_access, count, (revision_t)-1))
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