Author: Richard Plangger <planri...@gmail.com>
Branch: ppc-vsx-support
Changeset: r85424:c3391ca232ac
Date: 2016-06-27 16:07 +0200
http://bitbucket.org/pypy/pypy/changeset/c3391ca232ac/
Log: removed & renamed load/store combinations that are rewritten to
vec_load/vec_store
diff --git a/rpython/jit/backend/llsupport/rewrite.py
b/rpython/jit/backend/llsupport/rewrite.py
--- a/rpython/jit/backend/llsupport/rewrite.py
+++ b/rpython/jit/backend/llsupport/rewrite.py
@@ -158,10 +158,10 @@
def _emit_mul_if_factor_offset_not_supported(self, index_box,
factor, offset):
- factor, offset, index_box = cpu_simplify_scale(self.cpu, indexbox,
factor, offset)
- if index_box:
+ factor, offset, new_index_box = cpu_simplify_scale(self.cpu,
index_box, factor, offset)
+ if index_box is not new_index_box:
self.emit_op(index_box)
- return factor, offset, index_box
+ return factor, offset, new_index_box
def emit_gc_load_or_indexed(self, op, ptr_box, index_box, itemsize,
factor, offset, sign, type='i'):
diff --git a/rpython/jit/backend/llsupport/vector_ext.py
b/rpython/jit/backend/llsupport/vector_ext.py
--- a/rpython/jit/backend/llsupport/vector_ext.py
+++ b/rpython/jit/backend/llsupport/vector_ext.py
@@ -3,6 +3,7 @@
from rpython.rlib.objectmodel import specialize, always_inline
from rpython.jit.metainterp.history import (VECTOR, FLOAT, INT)
from rpython.jit.metainterp.resoperation import rop
+from rpython.jit.metainterp.optimizeopt.schedule import forwarded_vecinfo
class TypeRestrict(object):
ANY_TYPE = '\x00'
diff --git a/rpython/jit/backend/ppc/vector_ext.py
b/rpython/jit/backend/ppc/vector_ext.py
--- a/rpython/jit/backend/ppc/vector_ext.py
+++ b/rpython/jit/backend/ppc/vector_ext.py
@@ -26,22 +26,7 @@
class VectorAssembler(object):
_mixin_ = True
- def _emit_getitem(self, op, arglocs, regalloc):
- # prepares item scale (raw_load does not)
- resloc, base_loc, ofs_loc, size_loc, ofs, integer_loc, aligned_loc =
arglocs
- scale = get_scale(size_loc.value)
- xxx
- src_addr = addr_add(base_loc, ofs_loc, ofs.value, scale)
- self._vec_load(resloc, src_addr, integer_loc.value,
- size_loc.value, aligned_loc.value)
-
- emit_vec_getarrayitem_raw_i = _emit_getitem
- emit_vec_getarrayitem_raw_f = _emit_getitem
-
- emit_vec_getarrayitem_gc_i = _emit_getitem
- emit_vec_getarrayitem_gc_f = _emit_getitem
-
- def emit_vec_raw_load_f(self, op, arglocs, regalloc):
+ def emit_vec_load_f(self, op, arglocs, regalloc):
resloc, baseloc, indexloc, size_loc, ofs, integer_loc, aligned_loc =
arglocs
#src_addr = addr_add(baseloc, ofs_loc, ofs.value, 0)
assert ofs.value == 0
@@ -51,7 +36,7 @@
elif itemsize == 8:
self.mc.lxvd2x(resloc.value, indexloc.value, baseloc.value)
- def emit_vec_raw_load_i(self, op, arglocs, regalloc):
+ def emit_vec_load_i(self, op, arglocs, regalloc):
resloc, baseloc, indexloc, size_loc, ofs, \
Vhiloc, Vloloc, Vploc, tloc = arglocs
#src_addr = addr_add(base_loc, ofs_loc, ofs.value, 0)
@@ -84,15 +69,15 @@
genop_discard_vec_setarrayitem_raw = _emit_vec_setitem
genop_discard_vec_setarrayitem_gc = _emit_vec_setitem
- def emit_vec_raw_store(self, op, arglocs, regalloc):
+ def emit_vec_store(self, op, arglocs, regalloc):
baseloc, ofsloc, valueloc, size_loc, baseofs, \
integer_loc, aligned_loc = arglocs
#dest_loc = addr_add(base_loc, ofs_loc, baseofs.value, 0)
assert baseofs.value == 0
- self._vec_store(baseloc, ofsloc, valueloc, integer_loc.value,
- size_loc.value, regalloc)
+ # self._vec_store(baseloc, ofsloc, valueloc, integer_loc.value,
+ # size_loc.value, regalloc)
- def _vec_store(self, baseloc, indexloc, valueloc, integer, itemsize,
regalloc):
+ #def _vec_store(self, baseloc, indexloc, valueloc, integer, itemsize,
regalloc):
if integer:
Vloloc = regalloc.ivrm.get_scratch_reg()
Vhiloc = regalloc.ivrm.get_scratch_reg()
@@ -137,7 +122,6 @@
elif itemsize == 8:
self.mc.stxvd2x(valueloc.value, indexloc.value, baseloc.value)
-
def emit_vec_int_add(self, op, arglocs, regalloc):
resloc, loc0, loc1, size_loc = arglocs
size = size_loc.value
@@ -601,12 +585,8 @@
return [result_loc, base_loc, ofs_loc, imm(itemsize), imm(ofs),
Vhiloc, Vloloc, Vploc, tloc]
- prepare_vec_getarrayitem_raw_i = _prepare_load_i
- prepare_vec_getarrayitem_raw_f = _prepare_load
- prepare_vec_getarrayitem_gc_i = _prepare_load_i
- prepare_vec_getarrayitem_gc_f = _prepare_load
- prepare_vec_raw_load_i = _prepare_load_i
- prepare_vec_raw_load_f = _prepare_load
+ prepare_vec_load_i = _prepare_load_i
+ prepare_vec_load_f = _prepare_load
def prepare_vec_arith(self, op):
a0 = op.getarg(0)
@@ -639,7 +619,7 @@
del prepare_vec_arith
- def _prepare_vec_store(self, op):
+ def prepare_vec_store(self, op):
descr = op.getdescr()
assert isinstance(descr, ArrayDescr)
assert not descr.is_array_of_pointers() and \
@@ -657,11 +637,6 @@
return [baseloc, ofsloc, valueloc,
imm(itemsize), imm(ofs), imm(integer), imm(aligned)]
- prepare_vec_setarrayitem_raw = _prepare_vec_store
- prepare_vec_setarrayitem_gc = _prepare_vec_store
- prepare_vec_raw_store = _prepare_vec_store
- del _prepare_vec_store
-
def prepare_vec_int_signext(self, op):
assert isinstance(op, VectorOp)
a0 = op.getarg(0)
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