Author: Richard Plangger <planri...@gmail.com>
Branch: ppc-vsx-support
Changeset: r87220:a7ce3d0c0585
Date: 2016-09-19 09:42 +0200
http://bitbucket.org/pypy/pypy/changeset/a7ce3d0c0585/
Log: expand gpr/fpr to a vector reg
diff --git a/rpython/jit/backend/zarch/instruction_builder.py
b/rpython/jit/backend/zarch/instruction_builder.py
--- a/rpython/jit/backend/zarch/instruction_builder.py
+++ b/rpython/jit/backend/zarch/instruction_builder.py
@@ -546,6 +546,19 @@
self.writechar(opcode2)
return encode_vri_a
+def build_vri_c(mnemonic, (opcode1,opcode2), argtypes='v,v,i16,m'):
+ @builder.arguments(argtypes)
+ def encode_vri_c(self, v1, v3, i2, mask4):
+ self.writechar(opcode1)
+ rbx = (v1 >= 16) << 3
+ rbx |= (v3 >= 16) << 2
+ byte = (v1 & BIT_MASK_4) << 4 | (v3 & BIT_MASK_4)
+ self.writechar(chr(byte))
+ self.write_i16(i2 & BIT_MASK_16)
+ self.writechar(chr((mask4 & BIT_MASK_4) << 4 | (rbx & BIT_MASK_4)))
+ self.writechar(opcode2)
+ return encode_vri_c
+
def build_vrs_b(mnemonic, (opcode1,opcode2), argtypes='v,r,db,m'):
@builder.arguments(argtypes)
def encode_vrs_b(self, v1, r2, db3, m4):
diff --git a/rpython/jit/backend/zarch/instructions.py
b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -300,6 +300,8 @@
'VST': ('vrx', ['\xE7','\x0E'], 'v,bid'),
+ 'VREP': ('vri_c', ['\xE7','\x4D']),
+
# integral
# -> arith
'VA': ('vrr_c', ['\xE7','\xF3'], 'v,v,v,m'),
diff --git a/rpython/jit/backend/zarch/vector_ext.py
b/rpython/jit/backend/zarch/vector_ext.py
--- a/rpython/jit/backend/zarch/vector_ext.py
+++ b/rpython/jit/backend/zarch/vector_ext.py
@@ -244,9 +244,20 @@
assert isinstance(op, VectorOp)
resloc, loc0 = arglocs
size = op.bytesize
- self.mc.VLREP(resloc, loc0, l.itemsize_to_mask(size))
+ if loc0.is_core_reg():
+ self.mc.VLVG(resloc, loc0, l.addr(0), l.itemsize_to_mask(size))
+ self.mc.VREP(resloc, loc0, l.imm0, l.itemsize_to_mask(size))
+ else:
+ self.mc.VLREP(resloc, loc0, l.itemsize_to_mask(size))
- emit_vec_expand_f = emit_vec_expand_i
+ def emit_vec_expand_f(self, op, arglocs, regalloc):
+ assert isinstance(op, VectorOp)
+ resloc, loc0 = arglocs
+ size = op.bytesize
+ if loc0.is_fp_reg():
+ self.mc.VREP(resloc, loc0, l.imm0, l.itemsize_to_mask(size))
+ else:
+ self.mc.VLREP(resloc, loc0, l.itemsize_to_mask(size))
def _accum_reduce(self, op, arg, accumloc, targetloc):
# Currently the accumulator can ONLY be 64 bit float/int
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