Hi Peter,
This series has been reviewed, but it looks like it slipped through the cracks.
Is it possible it could be merged through your tree, assuming it looks good?
Thanks!
Joe
-Original Message-
From: Qemu-devel On Behalf
Of Joe Komlodi
Sent: Monday, November 16, 2020 3:11 PM
commands. [1]
[1]
https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf?rev=9b167fbf2b3645efba6385949a72e453
Signed-off-by: Joe Komlodi
Reviewed-by: Francisco Iglesias
---
hw/block/m25p80.c | 30
The previous naming of the configuration registers made it sound like that if
the bits were set the settings would be enabled, while the opposite is true.
Signed-off-by: Joe Komlodi
Reviewed-by: Francisco Iglesias
---
hw/block/m25p80.c | 12 ++--
1 file changed, 6 insertions(+), 6
VCFG XIP is set (disabled) when the NVCFG XIP bits are all set (disabled).
Signed-off-by: Joe Komlodi
Reviewed-by: Francisco Iglesias
---
hw/block/m25p80.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 452d252..eb6539f 100644
ue isn't all 0s or 1s, then the flash expects the amount of
cycles sent to be equal to the count in the register.
Thanks!
Joe
Joe Komlodi (4):
hw/block/m25p80: Make Numonyx config field names more accurate
hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx
hw/block/m25p80: Check SPI mode
Some Numonyx flash commands cannot be executed in DIO and QIO mode, such as
trying to do DPP or DOR when in QIO mode.
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 114 +-
1 file changed, 95 insertions(+), 19 deletions(-)
diff --git a/hw
Hi Francisco,
-Original Message-
From: Francisco Iglesias
Sent: Monday, November 16, 2020 7:59 AM
To: Joe Komlodi
Cc: qemu-de...@nongnu.org; philippe.mathieu.da...@gmail.com; Francisco Eduardo
Iglesias ; alist...@alistair23.me; qemu-block@nongnu.org;
mre...@redhat.com
Subject: Re
://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf?rev=9b167fbf2b3645efba6385949a72e453
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 30 +++---
1 file changed, 27 insertions(+), 3 deletions
Some Numonyx flash commands cannot be executed in DIO and QIO mode, such as
trying to do DPP or DOR when in QIO mode.
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 134 +-
1 file changed, 112 insertions(+), 22 deletions(-)
diff --git
The previous naming of the configuration registers made it sound like that if
the bits were set the settings would be enabled, while the opposite is true.
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/block
the dummy cycles for fast read commands are set to a specific value
(8 or 10) if the register is all 0s or 1s.
If the register value isn't all 0s or 1s, then the flash expects the amount of
cycles sent to be equal to the count in the register.
Thanks!
Joe
Joe Komlodi (4):
hw/block/m25p80: Make Numon
VCFG XIP is set (disabled) when the NVCFG XIP bits are all set (disabled).
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 452d252..eb6539f 100644
--- a/hw/block/m25p80.c
+++ b/hw
Hi Francisco,
-Original Message-
From: Francisco Iglesias
Sent: Wednesday, November 11, 2020 6:33 AM
To: Joe Komlodi
Cc: qemu-de...@nongnu.org; philippe.mathieu.da...@gmail.com; Francisco Eduardo
Iglesias ; alist...@alistair23.me; qemu-block@nongnu.org;
mre...@redhat.com
Subject: Re
Hi Philippe,
-Original Message-
From: Philippe Mathieu-Daudé
Sent: Monday, November 9, 2020 6:21 AM
To: Joe Komlodi ; qemu-de...@nongnu.org; Cédric Le Goater
; Edgar Iglesias
Cc: Francisco Eduardo Iglesias ; alist...@alistair23.me;
philippe.mathieu.da...@gmail.com; qemu-block
://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf?rev=9b167fbf2b3645efba6385949a72e453
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 43 ---
1 file changed, 40 insertions
Some Numonyx flash commands cannot be executed in DIO and QIO mode, such as
trying to do DPP or DOR when in QIO mode.
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 132 --
1 file changed, 119 insertions(+), 13 deletions(-)
diff --git
QIO and DIO modes should be enabled when the bits in NVCFG are set to 0.
This matches the behavior of the other bits in the NVCFG register.
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block/m25p80.c b/hw/block
r fast read commands are set to a specific value
(8 or 10) if the register is all 0s or 1s.
If the register value isn't all 0s or 1s, then the flash expects the amount of
cycles sent to be equal to the count in the register.
Thanks!
Joe
Joe Komlodi (3):
hw/block/m25p80: Fix Numonyx NVCFG DIO a
Hi Philippe,
Comments marked inline with [Joe]
-Original Message-
From: Philippe Mathieu-Daudé On Behalf Of
Philippe Mathieu-Daudé
Sent: Wednesday, October 28, 2020 2:27 AM
To: Joe Komlodi ; qemu-de...@nongnu.org
Cc: Francisco Eduardo Iglesias ; kw...@redhat.com;
alist...@alistair23
Hi Francisco,
Comments marked with [Joe]
-Original Message-
From: Francisco Iglesias
Sent: Tuesday, October 20, 2020 6:50 AM
To: Joe Komlodi
Cc: qemu-de...@nongnu.org; alist...@alistair23.me; kw...@redhat.com;
mre...@redhat.com; qemu-block@nongnu.org
Subject: Re: [PATCH 1/2] hw/block
://www.micron.com/-/media/client/global/documents/products/data-sheet/
nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf
?rev=9b167fbf2b3645efba6385949a72e453
Page 34, page 39 note 5
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 26 +++---
1 file changed, 23
(8 or 10) if the register is all 0s or 1s.
If the register value isn't all 0s or 1s, then the flash expects the amount of
cycles sent to be equal to the count in the register.
Thanks!
Joe
Joe Komlodi (1):
hw/block/m25p80: Fix Numonyx fast read dummy cycle count
hw/block/m25p80.c |
The nvcfg registers are all 1s, unless previously modified.
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 43830c9..69c88d4 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
.
The second patch changes the default value of the nvcfg register so it
matches what would be in hardware from the factory.
Thanks!
Joe
Joe Komlodi (2):
hw/block/m25p80: Fix Numonyx dummy cycle register behavior
hw/block/m25p80: Fix nonvolatile-cfg property default value
hw/block/m25p80.c
://www.micron.com/-/media/client/global/documents/products/
data-sheet/nor-flash/serial-nor/n25q/n25q_512mb_1_8v_65nm.pdf
Page 22 note 2, and page 30 notes 5 and 10.
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff
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