On 2/5/21 5:57 PM, Peter Maydell wrote:
> On Fri, 5 Feb 2021 at 14:43, Philippe Mathieu-Daudé wrote:
>>
>> The Xilinx CAN controller test is uses the ZCU102 board which is
>> based on a ZynqMP SoC. In the default configuration - used by this
>> test - this SoC creates 2 Cortex R5F cores. Such
On Fri, 5 Feb 2021 at 14:43, Philippe Mathieu-Daudé wrote:
>
> The Xilinx CAN controller test is uses the ZCU102 board which is
> based on a ZynqMP SoC. In the default configuration - used by this
> test - this SoC creates 2 Cortex R5F cores. Such cores are not
> v8A archicture, thus can not be
On Fri, Feb 5, 2021 at 6:45 AM Philippe Mathieu-Daudé wrote:
>
> The Xilinx CAN controller test is uses the ZCU102 board which is
> based on a ZynqMP SoC. In the default configuration - used by this
> test - this SoC creates 2 Cortex R5F cores. Such cores are not
> v8A archicture, thus can not be
