On Wed, Jun 08, 2022 at 10:28:55AM +0200, Klaus Jensen wrote:
> On May 9 16:16, Lukasz Maniak wrote:
> > Changes since v7:
> > - Fixed description of hw/acpi: Make the PCI hot-plug aware of SR-IOV
> > - Added description to docs: Add documentation for SR-IOV and
> >
)) {
> -trace_pci_nvme_mmio_shutdown_set();
> -nvme_ctrl_shutdown(n);
> -cc = data;
> -csts |= NVME_CSTS_SHST_COMPLETE;
> -} else if (!NVME_CC_SHN(data) && NVME_CC_SHN(cc)) {
> -trace_pci_nvme_mmio_shutdown_cleared();
> -csts &= ~NVME_CSTS_SHST_COMPLETE;
> -cc = data;
> +break;
> }
>
> -stl_le_p(>bar.cc, cc);
> stl_le_p(>bar.csts, csts);
>
> break;
> --
> 2.36.1
>
Reviewed-by: Lukasz Maniak
On Wed, May 25, 2022 at 09:35:24AM +0200, Klaus Jensen wrote:
>
> +stl_le_p(>bar.intms, 0);
> +stl_le_p(>bar.intmc, 0);
> +stl_le_p(>bar.cc, 0);
Looks fine, though it seems the NVMe spec says the above registers
should be cleared during each reset for VF as well.
> --
>
On Tue, May 17, 2022 at 01:04:56PM +0200, Klaus Jensen wrote:
> On May 16 17:25, Lukasz Maniak wrote:
> > On Mon, May 09, 2022 at 04:16:08PM +0200, Lukasz Maniak wrote:
> > > Changes since v7:
> > > - Fixed description of hw/acpi: Make the PCI hot-plug aware of SR-IO
On Tue, May 17, 2022 at 01:16:05PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> The SRIOV series exposed an issued with how CC register writes are
> handled and how CSTS is set in response to that. Specifically, after
> applying the SRIOV series, the controller could end up in a state
On Mon, May 09, 2022 at 04:16:08PM +0200, Lukasz Maniak wrote:
> Changes since v7:
> - Fixed description of hw/acpi: Make the PCI hot-plug aware of SR-IOV
> - Added description to docs: Add documentation for SR-IOV and
> Virtualization Enhancements
> - Added Reviewed-by an
From: Łukasz Gieryk
This patch updates the initialization place for the AER queue, so it’s
initialized once, at controller initialization, and not every time
controller is enabled.
While the original version works for a non-SR-IOV device, as it’s hard
to interact with the controller if it’s not
.
Signed-off-by: Lukasz Maniak
Acked-by: Michael S. Tsirkin
Reviewed-by: Klaus Jensen
---
docs/system/devices/nvme.rst | 82
1 file changed, 82 insertions(+)
diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst
index b5acb2a9c19
From: Łukasz Gieryk
An NVMe device with SR-IOV capability calculates the BAR size
differently for PF and VF, so it makes sense to extract the common code
to a separate function.
Signed-off-by: Łukasz Gieryk
Reviewed-by: Klaus Jensen
Acked-by: Michael S. Tsirkin
---
hw/nvme/ctrl.c | 45
the capabilities of
the VF.
NVMe subsystem is required for the use of SR-IOV.
Signed-off-by: Lukasz Maniak
Reviewed-by: Klaus Jensen
Acked-by: Michael S. Tsirkin
---
hw/nvme/ctrl.c | 85 ++--
hw/nvme/nvme.h | 3 +-
include/hw/pci/pci_ids.h | 1
From: Łukasz Gieryk
The n->reg_size parameter unnecessarily splits the BAR0 size calculation
in two phases; removed to simplify the code.
With all the calculations done in one place, it seems the pow2ceil,
applied originally to reg_size, is unnecessary. The rounding should
happen as the last
From: Łukasz Gieryk
The NVMe device defines two properties: max_ioqpairs, msix_qsize. Having
them as constants is problematic for SR-IOV support.
SR-IOV introduces virtual resources (queues, interrupts) that can be
assigned to PF and its dependent VFs. Each device, following a reset,
should
Changes since v7:
- Fixed description of hw/acpi: Make the PCI hot-plug aware of SR-IOV
- Added description to docs: Add documentation for SR-IOV and
Virtualization Enhancements
- Added Reviewed-by and Acked-by tags
- Rebased on master
Lukasz Maniak (4):
hw/nvme: Add support for SR-IOV
hw
From: Łukasz Gieryk
PCI device capable of SR-IOV support is a new, still-experimental
feature with only a single working example of the Nvme device.
This patch in an attempt to fix a double-free problem when a
SR-IOV-capable Nvme device is hot-unplugged in the following scenario:
Qemu CLI:
From: Łukasz Gieryk
With the new command one can:
- assign flexible resources (queues, interrupts) to primary and
secondary controllers,
- toggle the online/offline state of given controller.
Signed-off-by: Łukasz Gieryk
Acked-by: Michael S. Tsirkin
Reviewed-by: Klaus Jensen
---
From: Łukasz Gieryk
This patch implements the Function Level Reset, a feature currently not
implemented for the Nvme device, while listed as a mandatory ("shall")
in the 1.4 spec.
The implementation reuses FLR-related building blocks defined for the
pci-bridge module, and follows the same
Implementation of Primary Controller Capabilities data
structure (Identify command with CNS value of 14h).
Currently, the command returns only ID of a primary controller.
Handling of remaining fields are added in subsequent patches
implementing virtualization enhancements.
Signed-off-by: Lukasz
From: Łukasz Gieryk
With four new properties:
- sriov_v{i,q}_flexible,
- sriov_max_v{i,q}_per_vf,
one can configure the number of available flexible resources, as well as
the limits. The primary and secondary controller capability structures
are initialized accordingly.
Since the number of
is unregistered.
Signed-off-by: Lukasz Maniak
Acked-by: Michael S. Tsirkin
Reviewed-by: Klaus Jensen
---
hw/nvme/ctrl.c | 35 +
hw/nvme/ns.c | 2 +-
hw/nvme/nvme.h | 18 +++
hw/nvme/subsys.c | 75
On Wed, Apr 20, 2022 at 02:12:58PM +0200, Klaus Jensen wrote:
> On Apr 20 08:02, Michael S. Tsirkin wrote:
> > On Fri, Mar 18, 2022 at 08:18:07PM +0100, Lukasz Maniak wrote:
> > > Resubmitting v6 as v7 since Patchew got lost with my sophisticated CC of
> > > all mai
On Mon, Apr 04, 2022 at 11:41:46AM +0200, Łukasz Gieryk wrote:
> On Thu, Mar 31, 2022 at 02:38:41PM +0200, Igor Mammedov wrote:
> > it's unclear what's bing hotpluged and unplugged, it would be better if
> > you included QEMU CLI and relevan qmp/monito commands to reproduce it.
>
> Qemu CLI:
>
On Tue, Mar 01, 2022 at 01:23:18PM +0100, Klaus Jensen wrote:
> On Feb 17 18:45, Lukasz Maniak wrote:
> > Signed-off-by: Lukasz Maniak
>
> Please add a short commit description as well. Otherwise,
Klaus,
Sorry I forgot to add the description in v6 aka v7, been really busy
recen
From: Łukasz Gieryk
PCI device capable of SR-IOV support is a new, still-experimental
feature with only a single working example of the Nvme device.
This patch in an attempt to fix a double-free problem when a
SR-IOV-capable Nvme device is hot-unplugged. The problem and the
reproduction steps
From: Łukasz Gieryk
This patch updates the initialization place for the AER queue, so it’s
initialized once, at controller initialization, and not every time
controller is enabled.
While the original version works for a non-SR-IOV device, as it’s hard
to interact with the controller if it’s not
Signed-off-by: Lukasz Maniak
---
docs/system/devices/nvme.rst | 82
1 file changed, 82 insertions(+)
diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst
index b5acb2a9c19..aba253304e4 100644
--- a/docs/system/devices/nvme.rst
+++ b/docs
From: Łukasz Gieryk
The NVMe device defines two properties: max_ioqpairs, msix_qsize. Having
them as constants is problematic for SR-IOV support.
SR-IOV introduces virtual resources (queues, interrupts) that can be
assigned to PF and its dependent VFs. Each device, following a reset,
should
From: Łukasz Gieryk
This patch implements the Function Level Reset, a feature currently not
implemented for the Nvme device, while listed as a mandatory ("shall")
in the 1.4 spec.
The implementation reuses FLR-related building blocks defined for the
pci-bridge module, and follows the same
the capabilities of
the VF.
NVMe subsystem is required for the use of SR-IOV.
Signed-off-by: Lukasz Maniak
Reviewed-by: Klaus Jensen
---
hw/nvme/ctrl.c | 85 ++--
hw/nvme/nvme.h | 3 +-
include/hw/pci/pci_ids.h | 1 +
3 files changed, 85
From: Łukasz Gieryk
With the new command one can:
- assign flexible resources (queues, interrupts) to primary and
secondary controllers,
- toggle the online/offline state of given controller.
Signed-off-by: Łukasz Gieryk
---
hw/nvme/ctrl.c | 257
From: Łukasz Gieryk
With four new properties:
- sriov_v{i,q}_flexible,
- sriov_max_v{i,q}_per_vf,
one can configure the number of available flexible resources, as well as
the limits. The primary and secondary controller capability structures
are initialized accordingly.
Since the number of
From: Łukasz Gieryk
The n->reg_size parameter unnecessarily splits the BAR0 size calculation
in two phases; removed to simplify the code.
With all the calculations done in one place, it seems the pow2ceil,
applied originally to reg_size, is unnecessary. The rounding should
happen as the last
is unregistered.
Signed-off-by: Lukasz Maniak
---
hw/nvme/ctrl.c | 35 +
hw/nvme/ns.c | 2 +-
hw/nvme/nvme.h | 18 +++
hw/nvme/subsys.c | 75 ++--
hw/nvme/trace-events | 1 +
include/block/nvme.h | 20
into the tree
- Added Reviewed-by labels
Lukasz Maniak (4):
hw/nvme: Add support for SR-IOV
hw/nvme: Add support for Primary Controller Capabilities
hw/nvme: Add support for Secondary Controller List
docs: Add documentation for SR-IOV and Virtualization Enhancements
Łukasz Gieryk (8):
hw/nvme
From: Łukasz Gieryk
An NVMe device with SR-IOV capability calculates the BAR size
differently for PF and VF, so it makes sense to extract the common code
to a separate function.
Signed-off-by: Łukasz Gieryk
Reviewed-by: Klaus Jensen
---
hw/nvme/ctrl.c | 45
Implementation of Primary Controller Capabilities data
structure (Identify command with CNS value of 14h).
Currently, the command returns only ID of a primary controller.
Handling of remaining fields are added in subsequent patches
implementing virtualization enhancements.
Signed-off-by: Lukasz
From: Łukasz Gieryk
With four new properties:
- sriov_v{i,q}_flexible,
- sriov_max_v{i,q}_per_vf,
one can configure the number of available flexible resources, as well as
the limits. The primary and secondary controller capability structures
are initialized accordingly.
Since the number of
From: Łukasz Gieryk
PCI device capable of SR-IOV support is a new, still-experimental
feature with only a single working example of the Nvme device.
This patch in an attempt to fix a double-free problem when a
SR-IOV-capable Nvme device is hot-unplugged. The problem and the
reproduction steps
Signed-off-by: Lukasz Maniak
---
docs/system/devices/nvme.rst | 82
1 file changed, 82 insertions(+)
diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst
index b5acb2a9c19..aba253304e4 100644
--- a/docs/system/devices/nvme.rst
+++ b/docs
From: Łukasz Gieryk
With the new command one can:
- assign flexible resources (queues, interrupts) to primary and
secondary controllers,
- toggle the online/offline state of given controller.
Signed-off-by: Łukasz Gieryk
---
hw/nvme/ctrl.c | 257
From: Łukasz Gieryk
This patch updates the initialization place for the AER queue, so it’s
initialized once, at controller initialization, and not every time
controller is enabled.
While the original version works for a non-SR-IOV device, as it’s hard
to interact with the controller if it’s not
From: Łukasz Gieryk
An NVMe device with SR-IOV capability calculates the BAR size
differently for PF and VF, so it makes sense to extract the common code
to a separate function.
Signed-off-by: Łukasz Gieryk
Reviewed-by: Klaus Jensen
---
hw/nvme/ctrl.c | 45
From: Łukasz Gieryk
The n->reg_size parameter unnecessarily splits the BAR0 size calculation
in two phases; removed to simplify the code.
With all the calculations done in one place, it seems the pow2ceil,
applied originally to reg_size, is unnecessary. The rounding should
happen as the last
From: Łukasz Gieryk
The NVMe device defines two properties: max_ioqpairs, msix_qsize. Having
them as constants is problematic for SR-IOV support.
SR-IOV introduces virtual resources (queues, interrupts) that can be
assigned to PF and its dependent VFs. Each device, following a reset,
should
is unregistered.
Signed-off-by: Lukasz Maniak
---
hw/nvme/ctrl.c | 35 +
hw/nvme/ns.c | 2 +-
hw/nvme/nvme.h | 18 +++
hw/nvme/subsys.c | 75 ++--
hw/nvme/trace-events | 1 +
include/block/nvme.h | 20
Implementation of Primary Controller Capabilities data
structure (Identify command with CNS value of 14h).
Currently, the command returns only ID of a primary controller.
Handling of remaining fields are added in subsequent patches
implementing virtualization enhancements.
Signed-off-by: Lukasz
the capabilities of
the VF.
NVMe subsystem is required for the use of SR-IOV.
Signed-off-by: Lukasz Maniak
Reviewed-by: Klaus Jensen
---
hw/nvme/ctrl.c | 85 ++--
hw/nvme/nvme.h | 3 +-
include/hw/pci/pci_ids.h | 1 +
3 files changed, 85
From: Łukasz Gieryk
This patch implements the Function Level Reset, a feature currently not
implemented for the Nvme device, while listed as a mandatory ("shall")
in the 1.4 spec.
The implementation reuses FLR-related building blocks defined for the
pci-bridge module, and follows the same
Changes since v5:
- Fixed PCI hotplug issue related to deleting VF twice
- Corrected error messages for SR-IOV parameters
- Rebased on master, patches for PCI got pulled into the tree
- Added Reviewed-by labels
Lukasz Maniak (4):
hw/nvme: Add support for SR-IOV
hw/nvme: Add support
On Wed, Mar 09, 2022 at 01:41:27PM +0100, Łukasz Gieryk wrote:
> On Tue, Mar 01, 2022 at 02:07:08PM +0100, Klaus Jensen wrote:
> > On Feb 17 18:45, Lukasz Maniak wrote:
> > > From: Łukasz Gieryk
> > >
> > > With the new command one can:
> > > -
On Thu, Feb 17, 2022 at 06:45:01PM +0100, Lukasz Maniak wrote:
> From: Łukasz Gieryk
>
> With four new properties:
> - sriov_v{i,q}_flexible,
> - sriov_max_v{i,q}_per_vf,
> one can configure the number of available flexible resources, as well as
> the limits. The
On Fri, Feb 18, 2022 at 03:23:15AM -0500, Michael S. Tsirkin wrote:
> On Thu, Feb 17, 2022 at 06:44:49PM +0100, Lukasz Maniak wrote:
> > Changes since v4:
> > - Added hello world example for SR-IOV to the docs
> > - Moved AER initialization from nvme_init_ctrl to nvme_i
Signed-off-by: Lukasz Maniak
---
docs/system/devices/nvme.rst | 82
1 file changed, 82 insertions(+)
diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst
index b5acb2a9c19..aba253304e4 100644
--- a/docs/system/devices/nvme.rst
+++ b/docs
From: Łukasz Gieryk
With four new properties:
- sriov_v{i,q}_flexible,
- sriov_max_v{i,q}_per_vf,
one can configure the number of available flexible resources, as well as
the limits. The primary and secondary controller capability structures
are initialized accordingly.
Since the number of
From: Łukasz Gieryk
An NVMe device with SR-IOV capability calculates the BAR size
differently for PF and VF, so it makes sense to extract the common code
to a separate function.
Signed-off-by: Łukasz Gieryk
Reviewed-by: Klaus Jensen
---
hw/nvme/ctrl.c | 45
From: Łukasz Gieryk
The NVMe device defines two properties: max_ioqpairs, msix_qsize. Having
them as constants is problematic for SR-IOV support.
SR-IOV introduces virtual resources (queues, interrupts) that can be
assigned to PF and its dependent VFs. Each device, following a reset,
should
From: Łukasz Gieryk
With the new command one can:
- assign flexible resources (queues, interrupts) to primary and
secondary controllers,
- toggle the online/offline state of given controller.
Signed-off-by: Łukasz Gieryk
---
hw/nvme/ctrl.c | 257
is unregistered.
Signed-off-by: Lukasz Maniak
---
hw/nvme/ctrl.c | 35 +
hw/nvme/ns.c | 2 +-
hw/nvme/nvme.h | 18 +++
hw/nvme/subsys.c | 75 ++--
hw/nvme/trace-events | 1 +
include/block/nvme.h | 20
the capabilities of
the VF.
NVMe subsystem is required for the use of SR-IOV.
Signed-off-by: Lukasz Maniak
---
hw/nvme/ctrl.c | 85 ++--
hw/nvme/nvme.h | 3 +-
include/hw/pci/pci_ids.h | 1 +
3 files changed, 85 insertions(+), 4 deletions
From: Łukasz Gieryk
The n->reg_size parameter unnecessarily splits the BAR0 size calculation
in two phases; removed to simplify the code.
With all the calculations done in one place, it seems the pow2ceil,
applied originally to reg_size, is unnecessary. The rounding should
happen as the last
From: Łukasz Gieryk
This patch implements the Function Level Reset, a feature currently not
implemented for the Nvme device, while listed as a mandatory ("shall")
in the 1.4 spec.
The implementation reuses FLR-related building blocks defined for the
pci-bridge module, and follows the same
From: Łukasz Gieryk
This patch updates the initialization place for the AER queue, so it’s
initialized once, at controller initialization, and not every time
controller is enabled.
While the original version works for a non-SR-IOV device, as it’s hard
to interact with the controller if it’s not
Implementation of Primary Controller Capabilities data
structure (Identify command with CNS value of 14h).
Currently, the command returns only ID of a primary controller.
Handling of remaining fields are added in subsequent patches
implementing virtualization enhancements.
Signed-off-by: Lukasz
From: Knut Omang
This patch provides the building blocks for creating an SR/IOV
PCIe Extended Capability header and register/unregister
SR/IOV Virtual Functions.
Signed-off-by: Knut Omang
---
hw/pci/meson.build | 1 +
hw/pci/pci.c| 100 +---
hw/pci/pcie.c
From: Łukasz Gieryk
Convenience function for retrieving the PCIDevice object of the N-th VF.
Signed-off-by: Łukasz Gieryk
Reviewed-by: Knut Omang
---
hw/pci/pcie_sriov.c | 10 +-
include/hw/pci/pcie_sriov.h | 6 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff
From: Łukasz Gieryk
Signed-off-by: Łukasz Gieryk
---
include/hw/pci/pci_regs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/pci/pci_regs.h b/include/hw/pci/pci_regs.h
index 77ba64b9314..a5901409622 100644
--- a/include/hw/pci/pci_regs.h
+++ b/include/hw/pci/pci_regs.h
@@ -4,5
From: Knut Omang
Add a small intro + minimal documentation for how to
implement SR/IOV support for an emulated device.
Signed-off-by: Knut Omang
---
docs/pcie_sriov.txt | 115
1 file changed, 115 insertions(+)
create mode 100644
)
pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt
Lukasz Maniak (4):
hw/nvme: Add support for SR-IOV
hw/nvme: Add support for Primary Controller Capabilities
hw/nvme: Add support for Secondary Controller List
docs: Add documentation for SR-IOV and Virtualization Enhancements
On Fri, Feb 11, 2022 at 08:26:10AM +0100, Klaus Jensen wrote:
> On Jan 26 18:11, Lukasz Maniak wrote:
> > Changes since v3:
> > - Addressed comments to review on pcie: Add support for Single Root I/O
> > Virtualization (SR/IOV)
> > - Fixed issues reported by checkpatc
On Wed, Jan 26, 2022 at 06:11:06PM +0100, Lukasz Maniak wrote:
> From: Knut Omang
>
> This patch provides the building blocks for creating an SR/IOV
> PCIe Extended Capability header and register/unregister
> SR/IOV Virtual Functions.
>
> Signed-off-by: Knut Omang
Hi
From: Łukasz Gieryk
With four new properties:
- sriov_v{i,q}_flexible,
- sriov_max_v{i,q}_per_vf,
one can configure the number of available flexible resources, as well as
the limits. The primary and secondary controller capability structures
are initialized accordingly.
Since the number of
From: Łukasz Gieryk
This patch updates the initialization place for the AER queue, so it’s
initialized once, at controller initialization, and not every time
controller is enabled.
While the original version works for a non-SR-IOV device, as it’s hard
to interact with the controller if it’s not
From: Łukasz Gieryk
An NVMe device with SR-IOV capability calculates the BAR size
differently for PF and VF, so it makes sense to extract the common code
to a separate function.
Signed-off-by: Łukasz Gieryk
---
hw/nvme/ctrl.c | 45 +++--
1 file changed,
From: Łukasz Gieryk
With the new command one can:
- assign flexible resources (queues, interrupts) to primary and
secondary controllers,
- toggle the online/offline state of given controller.
Signed-off-by: Łukasz Gieryk
---
hw/nvme/ctrl.c | 257
Signed-off-by: Lukasz Maniak
---
docs/system/devices/nvme.rst | 36
1 file changed, 36 insertions(+)
diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst
index b5acb2a9c1..166a11abc6 100644
--- a/docs/system/devices/nvme.rst
+++ b/docs
From: Łukasz Gieryk
The NVMe device defines two properties: max_ioqpairs, msix_qsize. Having
them as constants is problematic for SR-IOV support.
SR-IOV introduces virtual resources (queues, interrupts) that can be
assigned to PF and its dependent VFs. Each device, following a reset,
should
is unregistered.
Signed-off-by: Lukasz Maniak
---
hw/nvme/ctrl.c | 35 +
hw/nvme/ns.c | 2 +-
hw/nvme/nvme.h | 18 +++
hw/nvme/subsys.c | 75 ++--
hw/nvme/trace-events | 1 +
include/block/nvme.h | 20
From: Łukasz Gieryk
This patch implements the Function Level Reset, a feature currently not
implemented for the Nvme device, while listed as a mandatory ("shall")
in the 1.4 spec.
The implementation reuses FLR-related building blocks defined for the
pci-bridge module, and follows the same
the capabilities of
the VF.
NVMe subsystem is required for the use of SR-IOV.
Signed-off-by: Lukasz Maniak
---
hw/nvme/ctrl.c | 85 ++--
hw/nvme/nvme.h | 3 +-
include/hw/pci/pci_ids.h | 1 +
3 files changed, 85 insertions(+), 4 deletions
From: Łukasz Gieryk
The n->reg_size parameter unnecessarily splits the BAR0 size calculation
in two phases; removed to simplify the code.
With all the calculations done in one place, it seems the pow2ceil,
applied originally to reg_size, is unnecessary. The rounding should
happen as the last
Implementation of Primary Controller Capabilities data
structure (Identify command with CNS value of 14h).
Currently, the command returns only ID of a primary controller.
Handling of remaining fields are added in subsequent patches
implementing virtualization enhancements.
Signed-off-by: Lukasz
From: Łukasz Gieryk
Signed-off-by: Łukasz Gieryk
---
include/hw/pci/pci_regs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/pci/pci_regs.h b/include/hw/pci/pci_regs.h
index 77ba64b931..a590140962 100644
--- a/include/hw/pci/pci_regs.h
+++ b/include/hw/pci/pci_regs.h
@@ -4,5
/pcie_sriov.txt
Lukasz Maniak (4):
hw/nvme: Add support for SR-IOV
hw/nvme: Add support for Primary Controller Capabilities
hw/nvme: Add support for Secondary Controller List
docs: Add documentation for SR-IOV and Virtualization Enhancements
Łukasz Gieryk (9):
pcie: Add a helper to the SR/IOV API
From: Łukasz Gieryk
Convenience function for retrieving the PCIDevice object of the N-th VF.
Signed-off-by: Łukasz Gieryk
Reviewed-by: Knut Omang
---
hw/pci/pcie_sriov.c | 10 +-
include/hw/pci/pcie_sriov.h | 6 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff
From: Knut Omang
Add a small intro + minimal documentation for how to
implement SR/IOV support for an emulated device.
Signed-off-by: Knut Omang
---
docs/pcie_sriov.txt | 115
1 file changed, 115 insertions(+)
create mode 100644
From: Knut Omang
This patch provides the building blocks for creating an SR/IOV
PCIe Extended Capability header and register/unregister
SR/IOV Virtual Functions.
Signed-off-by: Knut Omang
---
hw/pci/meson.build | 1 +
hw/pci/pci.c| 100 +---
hw/pci/pcie.c
From: Łukasz Gieryk
With the new command one can:
- assign flexible resources (queues, interrupts) to primary and
secondary controllers,
- toggle the online/offline state of given controller.
Signed-off-by: Łukasz Gieryk
---
hw/nvme/ctrl.c | 253
From: Łukasz Gieryk
The n->reg_size parameter unnecessarily splits the BAR0 size calculation
in two phases; removed to simplify the code.
With all the calculations done in one place, it seems the pow2ceil,
applied originally to reg_size, is unnecessary. The rounding should
happen as the last
From: Łukasz Gieryk
With four new properties:
- sriov_v{i,q}_flexible,
- sriov_max_v{i,q}_per_vf,
one can configure the number of available flexible resources, as well as
the limits. The primary and secondary controller capability structures
are initialized accordingly.
Since the number of
Signed-off-by: Lukasz Maniak
---
docs/system/devices/nvme.rst | 36
1 file changed, 36 insertions(+)
diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst
index b5acb2a9c1..166a11abc6 100644
--- a/docs/system/devices/nvme.rst
+++ b/docs
From: Łukasz Gieryk
An NVMe device with SR-IOV capability calculates the BAR size
differently for PF and VF, so it makes sense to extract the common code
to a separate function.
Signed-off-by: Łukasz Gieryk
---
hw/nvme/ctrl.c | 45 +++--
1 file changed,
From: Łukasz Gieryk
This patch updates the initialization place for the AER queue, so it’s
initialized once, at controller initialization, and not every time
controller is enabled.
While the original version works for a non-SR-IOV device, as it’s hard
to interact with the controller if it’s not
From: Łukasz Gieryk
The NVMe device defines two properties: max_ioqpairs, msix_qsize. Having
them as constants is problematic for SR-IOV support.
SR-IOV introduces virtual resources (queues, interrupts) that can be
assigned to PF and its dependent VFs. Each device, following a reset,
should
is unregistered.
Signed-off-by: Lukasz Maniak
---
hw/nvme/ctrl.c | 35 +
hw/nvme/ns.c | 2 +-
hw/nvme/nvme.h | 18 +++
hw/nvme/subsys.c | 75 ++--
hw/nvme/trace-events | 1 +
include/block/nvme.h | 20
From: Łukasz Gieryk
Signed-off-by: Łukasz Gieryk
---
include/hw/pci/pci_regs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/pci/pci_regs.h b/include/hw/pci/pci_regs.h
index 77ba64b931..a590140962 100644
--- a/include/hw/pci/pci_regs.h
+++ b/include/hw/pci/pci_regs.h
@@ -4,5
From: Łukasz Gieryk
This patch implements the Function Level Reset, a feature currently not
implemented for the Nvme device, while listed as a mandatory ("shall")
in the 1.4 spec.
The implementation reuses FLR-related building blocks defined for the
pci-bridge module, and follows the same
Implementation of Primary Controller Capabilities data
structure (Identify command with CNS value of 14h).
Currently, the command returns only ID of a primary controller.
Handling of remaining fields are added in subsequent patches
implementing virtualization enhancements.
Signed-off-by: Lukasz
the capabilities of
the VF.
NVMe subsystem is required for the use of SR-IOV.
Signed-off-by: Lukasz Maniak
---
hw/nvme/ctrl.c | 84 ++--
hw/nvme/nvme.h | 3 +-
include/hw/pci/pci_ids.h | 1 +
3 files changed, 84 insertions(+), 4 deletions
From: Knut Omang
Add a small intro + minimal documentation for how to
implement SR/IOV support for an emulated device.
Signed-off-by: Knut Omang
---
docs/pcie_sriov.txt | 115
1 file changed, 115 insertions(+)
create mode 100644
From: Knut Omang
This patch provides the building blocks for creating an SR/IOV
PCIe Extended Capability header and register/unregister
SR/IOV Virtual Functions.
Signed-off-by: Knut Omang
---
hw/pci/meson.build | 1 +
hw/pci/pci.c| 97 +---
hw/pci/pcie.c
pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt
Lukasz Maniak (4):
hw/nvme: Add support for SR-IOV
hw/nvme: Add support for Primary Controller Capabilities
hw/nvme: Add support for Secondary Controller List
docs: Add documentation for SR-IOV and Virtualization Enhancemen
1 - 100 of 129 matches
Mail list logo
