Re: [PATCH 3/9] hw/ide/ahci: write D2H FIS on when processing NCQ command

2023-05-17 Thread John Snow
On Fri, Apr 28, 2023 at 9:22 AM Niklas Cassel wrote: > > From: Niklas Cassel > > The way that BUSY + PxCI is cleared for NCQ (FPDMA QUEUED) commands is > described in SATA 3.5a Gold: > > 11.15 FPDMA QUEUED command protocol > DFPDMAQ2: ClearInterfaceBsy > "Transmit Register Device to Host FIS

[PATCH 3/9] hw/ide/ahci: write D2H FIS on when processing NCQ command

2023-04-28 Thread Niklas Cassel
From: Niklas Cassel The way that BUSY + PxCI is cleared for NCQ (FPDMA QUEUED) commands is described in SATA 3.5a Gold: 11.15 FPDMA QUEUED command protocol DFPDMAQ2: ClearInterfaceBsy "Transmit Register Device to Host FIS with the BSY bit cleared to zero and the DRQ bit cleared to zero and