> +s->sfpd_area[0x13] = 0x04; /* Parameter Table Length (DWORD) */
> +s->sfpd_area[0x14] = 0x60; /* Parameter Table Pointer */
> + s->sfpd_area[0x15] = 0x00; /* Parameter Table Pointer */
> +s->sfpd_area[0x16] = 0x00; /* Parameter Table Pointer */
> +s->
lar fix is needed in the xilinx_spips aswell, I just
provided a patch. Thank you for the notification!
Best regards,
Francisco Iglesias
>
> Thanks,
>
> C.
>
>
> > Signed-off-by: Guenter Roeck
> > ---
> > hw/ssi/aspeed_smc.c | 2 +-
> > 1 file changed, 1 insertion
gt;cmd_in_progress){
case QOR:
case QOR4
case QIOR:
case QIOR4:
n_dummies = 10;
break;
default:
n_dummies = 8;
break;
}
}
return n_dummies;
Best regards,
Francisco Iglesias
> +num_dummies = 10;
> +} else {
&g
also:
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %s"
(get_man(s) == MAN_SST) ? "AAI_WP with write protect" :
"Unknown CMD: 0xAD\n");
Lastly, [1] also says that the address shouldn't wrapp around when in AAI mode,
so we need a check before doing that also I think.
Best regards,
Francisco Iglesias
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
> +}
> +break;
> default:
> s->pos = 0;
> s->len = 1;
> --
> 2.25.1
>
>
Hello Bin,
On [2020 Dec 04] Fri 15:52:12, Bin Meng wrote:
> Hi Francisco,
>
> On Thu, Dec 3, 2020 at 4:38 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin and Alistair,
> >
> > On [2020 Dec 02] Wed 11:40:11, Alistair Francis wrote:
> > > On
Hello Bin,
On [2020 Dec 04] Fri 18:52:50, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Dec 4, 2020 at 6:46 PM Francisco Iglesias
> wrote:
> >
> > Hello Bin,
> >
> > On [2020 Dec 04] Fri 15:52:12, Bin Meng wrote:
> > > Hi Francisco,
> > >
&
man(s)) {
> > /* Dummy cycles - modeled with bytes writes instead of bits */
> > +case MAN_SST:
> > +s->needed_bytes += 1;
1 dummy clk cycle is modelled as 1 byte write (see the comment above), so 1
dummy byte (8 dummy clk cycles) will need +8 above. An o
Hi bin,
On [2020 Dec 12] Sat 16:16:59, Bin Meng wrote:
> Hi Francisco,
>
> On Sat, Dec 12, 2020 at 12:11 AM Francisco Iglesias
> wrote:
> >
> > Hello Bin,
> >
> > On [2020 Dec 11] Fri 23:29:16, Bin Meng wrote:
> > > Hi Francisco,
> > >
>
Hello Bin,
On [2020 Dec 11] Fri 23:29:16, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Dec 11, 2020 at 11:16 PM Francisco Iglesias
> wrote:
> >
> > Hello Bin,
> >
> > On [2020 Dec 11] Fri 14:07:21, Bin Meng wrote:
> > > Hi Francisco,
> > >
&
Signed-off-by: Xuzhou Cheng
> Signed-off-by: Bin Meng
Reviewed-by: Francisco Iglesias
>
> ---
>
> Changes in v5:
> - remove the guest error logging when address wrap is detected in AAI
> - change to return s->aai_enable in m25p80_aai_enable_needed()
>
> Cha
Hello Bin,
On [2020 Dec 12] Sat 17:44:27, Bin Meng wrote:
> Hi Francisco,
>
> On Sat, Dec 12, 2020 at 5:24 PM Francisco Iglesias
> wrote:
> >
> > Hi bin,
> >
> > On [2020 Dec 12] Sat 16:16:59, Bin Meng wrote:
> > > Hi Francisco,
> > >
>
aborts.
> + */
> +qemu_log_mask(LOG_GUEST_ERROR,
> + "M25P80: AAI highest memory address reached");
Above message will be printed after writing the highest addressed byte but
before trying to write a byte after wrapping. Since it wouldn't be
On [2020 Dec 22] Tue 14:45:19, Bin Meng wrote:
> From: Bin Meng
>
> When write is disabled, the write to flash should be avoided
> in flash_write8().
>
> Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
> Signed-off-by: Bin Meng
qemu_log_mask(LOG_GUEST_ERROR,
> + "M25P80: AAI highest memory address reached");
> + s->write_enable = false;
> +s->aai_enable = false;
> +}
> +
> break;
>
> case ST
Hello Bin,
On [2020 Dec 11] Fri 14:07:21, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Dec 4, 2020 at 7:28 PM Francisco Iglesias
> wrote:
> >
> > Hello Bin,
> >
> > On [2020 Dec 04] Fri 18:52:50, Bin Meng wrote:
> > > Hi Francisco,
> > >
&
md_in_progress) {
case QIOR:
case QIOR4:
num_dummies = 10;
break;
default:
num_dummies = (mode == MODE_QIO) = 10 : 8;
break;
};
Best regards,
Francisco Iglesias
> +} else {
> +num_dummies = cycle_count;
> +}
> +
> +/*
> + * Validation
k(LOG_GUEST_ERROR, "M25P80: Attempting Quad PP while in DIO
mode!\n");
}
break;
> - s->needed_bytes = get_addr_length(s);
> -s->pos = 0;
> -s->len = 0;
> -s->state = STATE_COLLECTING_DATA;
> +if
value should be propagated as it was before (0 - enabled and 1 - disabled). I
do see though that the define naming is not perfect and can make you believe
otherwise.
Best regards,
Francisco Iglesias
>
> Signed-off-by: Joe Komlodi
> ---
> hw/block/m25p80.c | 4 ++--
> 1 file
On Thu, Nov 12, 2020 at 07:10:52PM -0800, Joe Komlodi wrote:
> The previous naming of the configuration registers made it sound like that if
> the bits were set the settings would be enabled, while the opposite is true.
>
> Signed-off-by: Joe Komlodi
Reviewed-by: Franci
On Thu, Nov 12, 2020 at 07:10:53PM -0800, Joe Komlodi wrote:
> VCFG XIP is set (disabled) when the NVCFG XIP bits are all set (disabled).
>
> Signed-off-by: Joe Komlodi
Reviewed-by: Francisco Iglesias
> ---
> hw/block/m25p80.c | 2 +-
> 1 file changed, 1 insertion(+), 1 del
GUEST_ERROR, "M25P80: Cannot execute cmd %x in
> "
> + "QIO mode\n", s->cmd_in_progress);
> +}
> break;
>
> case QIOR:
> case QIOR4:
> -decode_qio_read_cmd(s);
> +
commands. [1]
"
Reviewed-by: Francisco Iglesias
Best regards,
Francisco Iglesias
>
> [1]
> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf?rev=9b167fbf2b3645efba6385949a72e453
>
> Signed
On Mon, Nov 16, 2020 at 03:11:03PM -0800, Joe Komlodi wrote:
> Some Numonyx flash commands cannot be executed in DIO and QIO mode, such as
> trying to do DPP or DOR when in QIO mode.
>
> Signed-off-by: Joe Komlodi
Reviewed-by: Francisco Iglesias
> ---
> hw/bl
Hi Bin,
On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote:
> Hi Francisco,
>
> On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
Dear Bin,
On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote:
> Hi Francisco,
>
> On Tue, Jan 19, 2021 at 9:01 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
Dear Bin,
On [2021 Jan 21] Thu 16:59:51, Bin Meng wrote:
> Hi Francisco,
>
> On Thu, Jan 21, 2021 at 4:50 PM Francisco Iglesias
> wrote:
> >
> > Dear Bin,
> >
> > On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
Hi Bin,
On [2021 Jan 21] Thu 16:59:51, Bin Meng wrote:
> Hi Francisco,
>
> On Thu, Jan 21, 2021 at 4:50 PM Francisco Iglesias
> wrote:
> >
> > Dear Bin,
> >
> > On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
on four lines (Quad command) it generates 2 dummy clock
cycles since it takes two cycles to transfer 8 bits).
Best regards,
Francisco Iglesias
> followed by fixes to 3 known SPI controller models that fall into
> the 2nd case above.
>
> Please note, I have no way to verify patch
Hi Bin,
On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
Hi Bin,
On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote:
> > > From: Bin Meng
> > >
>
s for examples. This might also mean that the
controller will need a change and do the opposite what above calculation
does, and convert the dummy bytes into dummy clock cycles (when
transmitting on 1 line it generates 8 dummy clock cycles for each dummy
byte, when it uses 2 lines it genera
On [2021 Apr 27] Tue 15:56:10, Alistair Francis wrote:
> On Fri, Apr 23, 2021 at 4:46 PM Bin Meng wrote:
> >
> > On Mon, Feb 8, 2021 at 10:41 PM Bin Meng wrote:
> > >
> > > On Thu, Jan 21, 2021 at 10:18 PM Francisco Iglesias
> > > wrote:
> > >
Hello Edgar,
On [2021 Feb 08] Mon 16:30:00, Edgar E. Iglesias wrote:
>On Mon, Feb 8, 2021 at 3:42 PM Bin Meng wrote:
>
> On Thu, Jan 21, 2021 at 10:18 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021
; 10, 1024, ER_4K) },
> +{ INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K) },
Reviewed-by: Francisco Iglesias
> };
>
> typedef enum {
> --
> 2.34.1
>
>
e.g. CVE-2021-3527).
>
> Signed-off-by: Philippe Mathieu-Daudé
> [PMM: expanded commit message]
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> block/vpc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/block
; +++ b/hw/block/m25p80.c
> @@ -1558,6 +1558,7 @@ static int m25p80_pre_save(void *opaque)
>
> static Property m25p80_properties[] = {
> /* This is default value for Micron flash */
> +DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false),
On [2022 Jun 21] Tue 13:24:27, Iris Chen wrote:
> From: Iris Chen
>
> Signed-off-by: Iris Chen
Reviewed-by: Francisco Iglesias
> ---
> Fixed .needed for subsection and suggestions from Francisco
>
> hw/block/m25p80.c | 82 ++--
Hi Iris
On [2022 Jul 06] Wed 19:16:26, Iris Chen wrote:
> Signed-off-by: Iris Chen
A couple of suggestions below if you would like to go for a v3 but otherwise:
Reviewed-by: Francisco Iglesias
Thanks,
Best regards,
Francisco Iglesias
> ---
> Addressing all comments.
>
On [2022 Jul 01] Fri 14:23:17, Cédric Le Goater wrote:
> On 7/1/22 13:40, Francisco Iglesias wrote:
> > Hi Iris,
> >
> > Looks good, a couple of minor comments below!
> >
> > On [2022 Jun 27] Mon 11:52:33, Iris Chen wrote:
> > > Signed-off-by: Iris Chen
s->data[0] |= (!!s->top_bottom_bit) << 5;
> +}
> +if (s->pi->flags & SNOR_F_HAS_SR_BP3_BIT6) {
> +s->data[0] |= (!!s->block_protect3) << 6;
> +}
>
> if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
> s->data[0] |= (!!s->quad_enable) << 6;
> @@ -1553,6 +1598,11 @@ static void m25p80_reset(DeviceState *d)
>
> s->wp_level = true;
> s->status_register_write_disabled = false;
> +s->block_protect0 = false;
> +s->block_protect1 = false;
> +s->block_protect2 = false;
> +s->block_protect3 = false;
> +s->top_bottom_bit = false;
We need to place above ones in a subsection in the vmstate (similar to the your
previous patch).
Looks good to me otherwise!
Thanks!
Best regards,
Francisco Iglesias
>
> reset_memory(s);
> }
> --
> 2.30.2
>
>
On [2022 Jul 08] Fri 09:45:52, Iris Chen wrote:
> Signed-off-by: Iris Chen
Reviewed-by: Francisco Iglesias
> ---
> Cosmetic suggestions addressed.
>
> hw/block/m25p80.c | 102 --
> 1 file changed, 90 insertions(+), 12 deletions(
On [2022 Jun 28] Tue 17:52:50, Cédric Le Goater wrote:
> Alistair, Francisco,
>
> On 6/22/22 11:45, Francisco Iglesias wrote:
> > On [2022 Jun 21] Tue 13:24:27, Iris Chen wrote:
> > > From: Iris Chen
> > >
> > > Signed-off-by: Iris Chen
> >
*s = M25P80(d);
>
> +s->wp_level = true;
> + s->status_register_write_disabled = false;
> +
> reset_memory(s);
> }
>
> @@ -1601,6 +1636,8 @@ static const VMStateDescription vmstate_m25p80 = {
> VMSTATE_UINT8(needed_bytes, Flash),
>
Hi Iris,
On [2022 Jun 17] Fri 15:02:45, Iris Chen wrote:
> Signed-off-by: Iris Chen
> ---
> Thanks everyone for your comments. This is a v3 patch that addresses all
> suggestions (moving write_enable to decode_new_cmd).
> I am waiting on some feedback from Dan's (dz4l...@gmail.com) patch
>
/* StandBy state SO shall be HiZ */
0xFF should be enough here (since we are dealing with 8 bits, e.g.
m25p80_transfer8). More safe is probably to return 0 though and see this as if
a pulldown was connected to the line instead (this because r has been default
to 0 and was the most likely return
RDSFDP command giving access to
> a private SFDP area under the flash. This area now needs to be
> populated with the flash device characteristics, using a new
> 'sfdp_read' handler under FlashPartInfo.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> -
On [2022 Jul 22] Fri 08:36:02, Cédric Le Goater wrote:
> A mx25l25635f chip model is generally found on these machines. It's
> newer and uses 4B opcodes which is better to exercise the support in
> the Linux kernel.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Fra
d so
might be that you can switch to just INFO and _ext_id 0 above (might be the
same in the previous patch with the similar flash). Otherwise looks good to
me:
Reviewed-by: Francisco Iglesias
> + .sfdp_read = m25p80_sfdp_mx25l25635f },
> { INFO("mx25l25655e", 0xc22619,
tern' in above hdr if we like (also the other patches),
either way:
Reviewed-by: Francisco Iglesias
> +
> +
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 13e7b28fd2b0..028b026d8ba2 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@
cd3f8a 100644
> --- a/hw/block/m25p80_sfdp.h
> +++ b/hw/block/m25p80_sfdp.h
> @@ -24,4 +24,6 @@ extern uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
> extern uint8_t m25p80_sfdp_w25q256(uint32_t addr);
> extern uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
>
> +extern uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
(optional -extern)
Reviewed-by: Francisco Iglesias
> +
> #endif
> --
> 2.35.1
>
tern uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
(optional -extern)
Reviewed-by: Francisco Iglesias
>
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 220dbc8fb327..8ba9d732a323 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -347,7
"qemu/osdep.h"
> +#include "qemu/host-utils.h"
> +#include "m25p80_sfdp.h"
> +
> +#define define_sfdp_read(model) \
> +uint8_t m25p80_sfdp_##model(uint32_t addr)\
> +{
nt8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
(optional -extern)
Reviewed-by: Francisco Iglesias
>
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 6b120ce65212..52df24d24751 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -240,7 +240,8 @@
b/hw/block/m25p80_sfdp.h
> @@ -21,4 +21,6 @@ extern uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
> extern uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
> extern uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
>
> +extern uint8_t m25p80_sfdp_w25q256(uint32_t addr);
(optional
Hi Cedric,
On [2022 Oct 10] Mon 11:58:40, Michael Walle wrote:
> Am 2022-10-10 08:23, schrieb Cédric Le Goater:
> > On 10/7/22 16:44, Francisco Iglesias wrote:
>
> > > > --- a/hw/block/m25p80.c
> > > > +++ b/hw/block/m25p80.c
> > > > @@ -234,6 +2
On [2022 Oct 13] Thu 18:12:34, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> hw/block/m25p80.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
&g
s->needed_bytes = 2;
> +if (s->write_enable) {
> +if (get_man(s) == MAN_NUMONYX) {
> +s->needed_bytes = 2;
> + } else if (get_man(s) == MAN_MICRON) {
> +s->needed_bytes += get_addr_length(s);
> +
> This is confusing for the user.
>
> Use blk_check_size_and_read_all() instead of blk_pread() to improve
> the reported error.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> hw/block/m25p80.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletio
On [2023 Dec 05] Tue 15:22:25, Sai Pavan Boddu wrote:
> Add Micro 2Gb OSPI flash part with sfdp data.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> ---
> hw/block/m25p80_sfdp.h | 1 +
> hw/block/m25p80.c | 3 +++
> hw/blo
On [2023 Dec 05] Tue 15:22:26, Sai Pavan Boddu wrote:
> This property allows users to change flash model on command line as
> below.
>
>ex: "-M xlnx-versal-virt,ospi-flash=mt35xu02gbba"
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> -
> the memory region.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
Tested-by: Francisco Iglesias
> ---
> hw/ssi/xlnx-versal-ospi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c
>
On 2024-02-16 12:03, Philippe Mathieu-Daudé wrote:
When the QOM parent is available, prefer object_initialize_child()
over object_initialize(), since it create the parent relationship.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
---
hw/net/can/xlnx-versal
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