Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 14c126baf1c38607c5bd988878de85a06cefd8cf
      
https://github.com/qemu/qemu/commit/14c126baf1c38607c5bd988878de85a06cefd8cf
  Author: Brendan Fennell <bfenn...@skynet.ie>
  Date:   2012-09-26 (Wed, 26 Sep 2012)

  Changed paths:
    M hw/pl190.c

  Log Message:
  -----------
  pl190: fix read of VECTADDR

Reading VECTADDR was causing us to set the current priority to
the wrong value, the most obvious effect of which was that we
would return the vector for the wrong interrupt as the result
of the read.

Signed-off-by: Brendan Fennell <bfenn...@skynet.ie>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 9892cae39562d2e6c00ccc5966302c00f23be6d4
      
https://github.com/qemu/qemu/commit/9892cae39562d2e6c00ccc5966302c00f23be6d4
  Author: Meador Inge <mead...@codesourcery.com>
  Date:   2012-09-26 (Wed, 26 Sep 2012)

  Changed paths:
    M hw/armv7m_nvic.c

  Log Message:
  -----------
  hw/armv7m_nvic: Correctly register GIC region when setting up NVIC

When setting up the NVIC memory regions the memory range
0x100..0xcff is aliased to an IO memory region that belongs
to the ARM GIC.  This aliased region should be added to the
NVIC memory container, but the actual GIC IO memory region
was being added instead.  This mixup was causing the wrong
IO memory access functions to be called when accessing parts
of the NVIC memory.

Signed-off-by: Meador Inge <mead...@codesourcery.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 661bafb3e14bfffcb0a7c7910534c7944608ca45
      
https://github.com/qemu/qemu/commit/661bafb3e14bfffcb0a7c7910534c7944608ca45
  Author: Francesco Lavra <francescolavra...@gmail.com>
  Date:   2012-09-26 (Wed, 26 Sep 2012)

  Changed paths:
    M hw/vexpress.c

  Log Message:
  -----------
  Versatile Express: Fix NOR flash 0 address and remove flash alias

In the A series memory map (implemented in the Cortex A15 CoreTile), the
first NOR flash bank (flash 0) is mapped to address 0x08000000, while
address 0x00000000 can be configured as alias to either the first or the
second flash bank. This patch fixes the definition of flash 0 address,
and for simplicity removes the alias definition.

Signed-off-by: Francesco Lavra <francescolavra...@gmail.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 3dc3e7dd936f2e7f3e6dd4056f81c8961dc8201b
      
https://github.com/qemu/qemu/commit/3dc3e7dd936f2e7f3e6dd4056f81c8961dc8201b
  Author: Francesco Lavra <francescolavra...@gmail.com>
  Date:   2012-09-26 (Wed, 26 Sep 2012)

  Changed paths:
    M hw/vexpress.c

  Log Message:
  -----------
  Versatile Express: Add modelling of NOR flash

This patch adds modelling of the two NOR flash banks found on the
Versatile Express motherboard. Tested with U-Boot running on an emulated
Versatile Express, with either A9 or A15 CoreTile.

Signed-off-by: Francesco Lavra <francescolavra...@gmail.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: fdefe51c288866b98e62663fa18c8af1d66bf5f6
      
https://github.com/qemu/qemu/commit/fdefe51c288866b98e62663fa18c8af1d66bf5f6
  Author: Richard Henderson <r...@twiddle.net>
  Date:   2012-09-27 (Thu, 27 Sep 2012)

  Changed paths:
    M target-alpha/translate.c
    M target-arm/translate.c
    M target-cris/translate.c
    M target-i386/translate.c
    M target-lm32/translate.c
    M target-microblaze/translate.c
    M target-mips/translate.c
    M target-openrisc/translate.c
    M target-ppc/translate.c
    M target-sh4/translate.c
    M target-sparc/translate.c
    M target-xtensa/translate.c

  Log Message:
  -----------
  Emit debug_insn for CPU_LOG_TB_OP_OPT as well.

For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.

This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.

Signed-off-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>


  Commit: fa547e617c2f499903dccb8f1b9031bfe724e11e
      
https://github.com/qemu/qemu/commit/fa547e617c2f499903dccb8f1b9031bfe724e11e
  Author: Richard Henderson <r...@twiddle.net>
  Date:   2012-09-27 (Thu, 27 Sep 2012)

  Changed paths:
    M target-m68k/translate.c

  Log Message:
  -----------
  target-m68k: Call tcg_gen_debug_insn_start

Cc: Paul Brook <p...@codesourcery.com>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>


  Commit: 7193b5f6f52d633531406771b9370d7b591cef88
      
https://github.com/qemu/qemu/commit/7193b5f6f52d633531406771b9370d7b591cef88
  Author: Richard Henderson <r...@twiddle.net>
  Date:   2012-09-27 (Thu, 27 Sep 2012)

  Changed paths:
    M target-s390x/translate.c

  Log Message:
  -----------
  target-s390x: Call tcg_gen_debug_insn_start

Cc: Alexander Graf <ag...@suse.de>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>


  Commit: daa47c34a893917d712923b107d33f7b89a3a53b
      
https://github.com/qemu/qemu/commit/daa47c34a893917d712923b107d33f7b89a3a53b
  Author: Richard Henderson <r...@twiddle.net>
  Date:   2012-09-27 (Thu, 27 Sep 2012)

  Changed paths:
    M target-unicore32/translate.c

  Log Message:
  -----------
  target-unicore32: Call tcg_gen_debug_insn_start

Acked-by: Guan Xuetao <g...@mprc.pku.edu.cn>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>


  Commit: 0d404541b24b332f6a822139c6bd889b7e319762
      
https://github.com/qemu/qemu/commit/0d404541b24b332f6a822139c6bd889b7e319762
  Author: Richard Henderson <r...@twiddle.net>
  Date:   2012-09-27 (Thu, 27 Sep 2012)

  Changed paths:
    M target-s390x/helper.c
    M target-s390x/misc_helper.c

  Log Message:
  -----------
  target-s390x: Use CPU_LOG_INT

Three places in the interrupt code did we not honor the mask.

Reviewed-by: Alexander Graf <ag...@suse.de>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>


  Commit: 87a5395bdd75c22e8c9b92c5655810762a7fd5bf
      
https://github.com/qemu/qemu/commit/87a5395bdd75c22e8c9b92c5655810762a7fd5bf
  Author: Richard Henderson <r...@twiddle.net>
  Date:   2012-09-27 (Thu, 27 Sep 2012)

  Changed paths:
    M target-s390x/translate.c

  Log Message:
  -----------
  target-s390x: Avoid double CPU_LOG_TB_CPU

This is already handled generically in cpu_exec.

Reviewed-by: Alexander Graf <ag...@suse.de>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>


  Commit: d885bdd481fc1c11d3158cc1c4c68bffdb2c26fe
      
https://github.com/qemu/qemu/commit/d885bdd481fc1c11d3158cc1c4c68bffdb2c26fe
  Author: Richard Henderson <r...@twiddle.net>
  Date:   2012-09-27 (Thu, 27 Sep 2012)

  Changed paths:
    M target-s390x/translate.c

  Log Message:
  -----------
  target-s390x: Tidy cpu_dump_state

The blank lines inside the single dump make it difficult for the
eye to pick out the block.  Worse, with interior newlines, but
no blank line following, the PSW line appears to belong to the
next dump block.

Reviewed-by: Alexander Graf <ag...@suse.de>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>


  Commit: 6f8fd2530e9a530f237240daf1c981fa5df7f978
      
https://github.com/qemu/qemu/commit/6f8fd2530e9a530f237240daf1c981fa5df7f978
  Author: Aurelien Jarno <aurel...@aurel32.net>
  Date:   2012-09-27 (Thu, 27 Sep 2012)

  Changed paths:
    M hw/armv7m_nvic.c
    M hw/pl190.c
    M hw/vexpress.c

  Log Message:
  -----------
  Merge branch 'arm-devs.for-upstream' of 
git://git.linaro.org/people/pmaydell/qemu-arm

* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm:
  Versatile Express: Add modelling of NOR flash
  Versatile Express: Fix NOR flash 0 address and remove flash alias
  hw/armv7m_nvic: Correctly register GIC region when setting up NVIC
  pl190: fix read of VECTADDR


Compare: https://github.com/qemu/qemu/compare/6673f47da217...6f8fd2530e9a

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