Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 62724cc5ebd7fb9113f156cbc0d2bb5e3cb0a9ae
https://github.com/qemu/qemu/commit/62724cc5ebd7fb9113f156cbc0d2bb5e3cb0a9ae
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M linux-user/qemu.h
Log Message:
-----------
linux-user: Use memcpy in get_user/put_user.
When host and target have differing alignment rules, using a cast
and direct memory operation can result in SIGBUS. Use memcpy instead,
which the compiler will happily optimize when alignment is satisfied.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 3ee60ad44a3a8673ad38e3da5af05455fed377b8
https://github.com/qemu/qemu/commit/3ee60ad44a3a8673ad38e3da5af05455fed377b8
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Hack in qemu_ld/st64 for 32-bit.
Not actually implemented, but at least we avoid the tcg assert at startup.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: a221ae3fcc55fcc3911587bc572af88eed3342dd
https://github.com/qemu/qemu/commit/a221ae3fcc55fcc3911587bc572af88eed3342dd
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Fix ADDX opcode.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: d5dd696fe3049657c08eb14f40cb74b6e94e79cc
https://github.com/qemu/qemu/commit/d5dd696fe3049657c08eb14f40cb74b6e94e79cc
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M exec.c
Log Message:
-----------
tcg-sparc: Don't MAP_FIXED on top of the program
The address we pick in sparc64.ld is also 0x60000000, so doing a fixed map
on top of that is guaranteed to blow up. Choosing 0x40000000 is exactly
right for the max of code_gen_buffer_size set below.
No need to ever use MAP_FIXED. While getting our desired address helps
optimize the generated code, we won't fail if we don't get it.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: 9b9c37c36439ee0452632253dac7a31897f27f70
https://github.com/qemu/qemu/commit/9b9c37c36439ee0452632253dac7a31897f27f70
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M configure
M disas.c
M exec.c
M qemu-timer.h
M tcg/sparc/tcg-target.c
M tcg/sparc/tcg-target.h
M tcg/tcg.c
Log Message:
-----------
tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
Current code doesn't actually work in 32-bit mode at all. Since
no one really noticed, drop the complication of v7 and v8 cpus.
Eliminate the --sparc_cpu configure option and standardize macro
testing on TCG_TARGET_REG_BITS / HOST_LONG_BITS
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: a0ce341aac61ca3d56bcb56dcfb6ac11272fd567
https://github.com/qemu/qemu/commit/a0ce341aac61ca3d56bcb56dcfb6ac11272fd567
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Fix qemu_ld/st to handle 32-bit host.
At the same time, split out the tlb load logic to a new function.
Fixes the cases of two data registers and two address registers.
Fixes the signature of, and adds missing, qemu_ld/st opcodes.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: c6f7e4fb9a0f82bb826f4bd7dff6f2c90d6a83be
https://github.com/qemu/qemu/commit/c6f7e4fb9a0f82bb826f4bd7dff6f2c90d6a83be
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M configure
M tcg/sparc/tcg-target.c
M tcg/sparc/tcg-target.h
Log Message:
-----------
tcg-sparc: Support GUEST_BASE.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: 0c554161b6fadf75e42d4228e952ff100176ff8a
https://github.com/qemu/qemu/commit/0c554161b6fadf75e42d4228e952ff100176ff8a
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M tcg/sparc/tcg-target.c
M tcg/sparc/tcg-target.h
Log Message:
-----------
tcg-sparc: Change AREG0 in generated code to %i0.
We can now move the TCG variable from %g[56] to a call-preserved
windowed register.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: 4c3204cb12a966d0d1255eeeaabf30ee4bd34629
https://github.com/qemu/qemu/commit/4c3204cb12a966d0d1255eeeaabf30ee4bd34629
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M configure
M tcg/sparc/tcg-target.c
M tcg/sparc/tcg-target.h
Log Message:
-----------
tcg-sparc: Clean up cruft stemming from attempts to use global registers.
Don't use -ffixed-gN. Don't link statically. Don't save/restore
AREG0 around calls. Don't allocate space on the stack for AREG0 save.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: 1fd959466574c3d46f4898f2e27cd3b1060338e4
https://github.com/qemu/qemu/commit/1fd959466574c3d46f4898f2e27cd3b1060338e4
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Mask shift immediates to avoid illegal insns.
The xtensa-test image generates a sra_i32 with count 0x40.
Whether this is accident of tcg constant propagation or
originating directly from the instruction stream is immaterial.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: 375816f84b820e087fab8ff584bd5b8f27811cdb
https://github.com/qemu/qemu/commit/375816f84b820e087fab8ff584bd5b8f27811cdb
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Use defines for temporaries.
And change from %i4/%i5 to %g1/%o7 to remove a v8plus fixme.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: 26adfb759c4c6ad42958c365812945316f3468ae
https://github.com/qemu/qemu/commit/26adfb759c4c6ad42958c365812945316f3468ae
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Add %g/%o registers to alloc_order
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: 5bbd2cae8e087b4329e17c3f44439096e4c3ec6a
https://github.com/qemu/qemu/commit/5bbd2cae8e087b4329e17c3f44439096e4c3ec6a
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M exec-all.h
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Fix and enable direct TB chaining.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: f4bf0b912e780978a37979f7a9fad40f99aa2241
https://github.com/qemu/qemu/commit/f4bf0b912e780978a37979f7a9fad40f99aa2241
Author: Richard Henderson <r...@twiddle.net>
Date: 2012-09-21 (Fri, 21 Sep 2012)
Changed paths:
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Preserve branch destinations during retranslation
Signed-off-by: Richard Henderson <r...@twiddle.net>
Commit: 66176802960ad1f7c3d061d17b784088c2e28d59
https://github.com/qemu/qemu/commit/66176802960ad1f7c3d061d17b784088c2e28d59
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M fpu/softfloat.h
Log Message:
-----------
softfloat: make float_muladd_negate_* flags independent
Flags passed into float{32,64}_muladd are treated as bits; assign
independent bits to float_muladd_negate_* to allow precise control over
what gets negated in float{32,64}_muladd.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: 213ff4e6df0f74e93995a5d3d7429acb4ad3ee86
https://github.com/qemu/qemu/commit/213ff4e6df0f74e93995a5d3d7429acb4ad3ee86
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M fpu/softfloat-specialize.h
M fpu/softfloat.h
Log Message:
-----------
softfloat: add NO_SIGNALING_NANS
Architectures that don't have signaling NaNs can define
NO_SIGNALING_NANS, it will make float*_is_quiet_nan return 1 for any NaN
and float*_is_signaling_nan always return 0.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: 10f6ca034089e201aaff1da5ed99b127811081d5
https://github.com/qemu/qemu/commit/10f6ca034089e201aaff1da5ed99b127811081d5
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M target-xtensa/overlay_tool.h
Log Message:
-----------
target-xtensa: handle boolean option in overlays
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: b81fe822dad134871cd336e26ed55d165e597f4e
https://github.com/qemu/qemu/commit/b81fe822dad134871cd336e26ed55d165e597f4e
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M fpu/softfloat-specialize.h
Log Message:
-----------
target-xtensa: specialize softfloat NaN rules
NaN propagation rule: leftmost NaN in the expression gets propagated to
the result.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: dd519cbec63434f2b883f0b4a20f827bbd59793e
https://github.com/qemu/qemu/commit/dd519cbec63434f2b883f0b4a20f827bbd59793e
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M gdbstub.c
M target-xtensa/cpu.h
M target-xtensa/helper.h
M target-xtensa/op_helper.c
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: add FP registers
There are 16 32-bit FP registers (f0 - f15), control and status user
registers (fcr, fsr).
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: 9ed7ae12afacdd234a749aa5af27dd93ea1594ec
https://github.com/qemu/qemu/commit/9ed7ae12afacdd234a749aa5af27dd93ea1594ec
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: implement LSCX and LSCI groups
These are load/store instructions for FP registers with immediate or
register index and optional base post-update.
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: 0b6df8385d24a4eed0ff546493c59e047b16537b
https://github.com/qemu/qemu/commit/0b6df8385d24a4eed0ff546493c59e047b16537b
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M target-xtensa/helper.h
M target-xtensa/op_helper.c
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: implement FP0 arithmetic
These are FP arithmetic opcodes.
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: b7ee8c6a32987e5039f0a2c2976fad556965727d
https://github.com/qemu/qemu/commit/b7ee8c6a32987e5039f0a2c2976fad556965727d
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M target-xtensa/helper.h
M target-xtensa/op_helper.c
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: implement FP0 conversions
These are FP to integer and integer to FP conversion opcodes.
See ISA, 4.3.10 for more details.
Note that ISA description for utrunc.s is currently incorrect and will
be fixed in future revisions.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: 4e273869671d78660cd709183d3c5dec3a17de79
https://github.com/qemu/qemu/commit/4e273869671d78660cd709183d3c5dec3a17de79
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M target-xtensa/helper.h
M target-xtensa/op_helper.c
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: implement FP1 group
These are comparison and conditional move opcodes.
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: ef04a8467eae31bc93b9458ad3d30a6ad1303327
https://github.com/qemu/qemu/commit/ef04a8467eae31bc93b9458ad3d30a6ad1303327
Author: Max Filippov <jcmvb...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M target-xtensa/cpu.h
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: implement coprocessor context option
In case Coprocessor Context option is enabled CPENABLE SR bits control
whether access to coprocessors is allowed or would rise one of
CoprocessorXDisabled exceptions.
See ISA, 4.4.5 for more details.
FP is coprocessor 0.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
Commit: 04cbbdeefdda2615b11f7890f1e61b750e83129f
https://github.com/qemu/qemu/commit/04cbbdeefdda2615b11f7890f1e61b750e83129f
Author: Blue Swirl <blauwir...@gmail.com>
Date: 2012-09-22 (Sat, 22 Sep 2012)
Changed paths:
M configure
M disas.c
M exec-all.h
M exec.c
M linux-user/qemu.h
M qemu-timer.h
M tcg/sparc/tcg-target.c
M tcg/sparc/tcg-target.h
M tcg/tcg.c
Log Message:
-----------
Merge branch 'tcg-sparc' of git://repo.or.cz/qemu/rth
* 'tcg-sparc' of git://repo.or.cz/qemu/rth:
tcg-sparc: Preserve branch destinations during retranslation
tcg-sparc: Fix and enable direct TB chaining.
tcg-sparc: Add %g/%o registers to alloc_order
tcg-sparc: Use defines for temporaries.
tcg-sparc: Mask shift immediates to avoid illegal insns.
tcg-sparc: Clean up cruft stemming from attempts to use global registers.
tcg-sparc: Change AREG0 in generated code to %i0.
tcg-sparc: Support GUEST_BASE.
tcg-sparc: Fix qemu_ld/st to handle 32-bit host.
tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
tcg-sparc: Don't MAP_FIXED on top of the program
tcg-sparc: Fix ADDX opcode.
tcg-sparc: Hack in qemu_ld/st64 for 32-bit.
linux-user: Use memcpy in get_user/put_user.
Compare: https://github.com/qemu/qemu/compare/e809c0dc7052...04cbbdeefdda
