Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 07664ca68b6fd1be1b5574e6a5e360057fd54322
https://github.com/qemu/qemu/commit/07664ca68b6fd1be1b5574e6a5e360057fd54322
Author: Alistair Francis <alistair.fran...@xilinx.com>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/timer/Makefile.objs
A hw/timer/xlnx-zynqmp-rtc.c
A include/hw/timer/xlnx-zynqmp-rtc.h
Log Message:
-----------
xlnx-zynqmp-rtc: Initial commit
Initial commit of the ZynqMP RTC device.
Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 246003ce6799e1de6a2216953917fc4484d24079
https://github.com/qemu/qemu/commit/246003ce6799e1de6a2216953917fc4484d24079
Author: Alistair Francis <alistair.fran...@xilinx.com>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/timer/trace-events
M hw/timer/xlnx-zynqmp-rtc.c
M include/hw/timer/xlnx-zynqmp-rtc.h
Log Message:
-----------
xlnx-zynqmp-rtc: Add basic time support
Allow the guest to determine the time set from the QEMU command line.
This includes adding a trace event to debug the new time.
Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 08b2f15e67d9d9b3bda09e5bd3d89979bfc4f6b8
https://github.com/qemu/qemu/commit/08b2f15e67d9d9b3bda09e5bd3d89979bfc4f6b8
Author: Alistair Francis <alistair.fran...@xilinx.com>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/arm/xlnx-zynqmp.c
M include/hw/arm/xlnx-zynqmp.h
Log Message:
-----------
xlnx-zynqmp: Connect the RTC device
Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 768055980b5f4a65d1bc2b6a7c1ece98adf7e262
https://github.com/qemu/qemu/commit/768055980b5f4a65d1bc2b6a7c1ece98adf7e262
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M scripts/decodetree.py
Log Message:
-----------
decodetree: Propagate return value from translate subroutines
Allow the translate subroutines to return false for invalid insns.
At present we can of course invoke an invalid insn exception from within
the translate subroutine, but in the short term this consolidates code.
In the long term it would allow the decodetree language to support
overlapping patterns for ISA extensions.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180227232618.2908-1-richard.hender...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 97df5feee3fe8b0e4e1a2cd3105ec476eb84cf42
https://github.com/qemu/qemu/commit/97df5feee3fe8b0e4e1a2cd3105ec476eb84cf42
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/core/loader.c
M include/hw/loader.h
Log Message:
-----------
loader: Add new load_ramdisk_as()
Add a function load_ramdisk_as() which behaves like the existing
load_ramdisk() but allows the caller to specify the AddressSpace
to use. This matches the pattern we have already for various
other loader functions.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-2-peter.mayd...@linaro.org
Commit: 9f43d4c34017df6bb5b6a13d43f941e90ec2d233
https://github.com/qemu/qemu/commit/9f43d4c34017df6bb5b6a13d43f941e90ec2d233
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Honour CPU's address space for image loads
Instead of loading kernels, device trees, and the like to
the system address space, use the CPU's address space. This
is important if we're trying to load the file to memory or
via an alias memory region that is provided by an SoC
object and thus not mapped into the system address space.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-3-peter.mayd...@linaro.org
Commit: 891f3bc37fb9dd81a27d19edc091be2603c9c176
https://github.com/qemu/qemu/commit/891f3bc37fb9dd81a27d19edc091be2603c9c176
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/arm/armv7m.c
Log Message:
-----------
hw/arm/armv7m: Honour CPU's address space for image loads
Instead of loading guest images to the system address space, use the
CPU's address space. This is important if we're trying to load the
file to memory or via an alias memory region that is provided by an
SoC object and thus not mapped into the system address space.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-4-peter.mayd...@linaro.org
Commit: 181962fd69938bffa1682bfa0ec43f02d829929d
https://github.com/qemu/qemu/commit/181962fd69938bffa1682bfa0ec43f02d829929d
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
A target/arm/idau.h
Log Message:
-----------
target/arm: Define an IDAU interface
In v8M, the Implementation Defined Attribution Unit (IDAU) is
a small piece of hardware typically implemented in the SoC
which provides board or SoC specific security attribution
information for each address that the CPU performs MPU/SAU
checks on. For QEMU, we model this with a QOM interface which
is implemented by the board or SoC object and connected to
the CPU using a link property.
This commit defines the new interface class, adds the link
property to the CPU object, and makes the SAU checking
code call the IDAU interface if one is present.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-5-peter.mayd...@linaro.org
Commit: c60c1b0d5af1a3568922611afc8a9d9bce31c200
https://github.com/qemu/qemu/commit/c60c1b0d5af1a3568922611afc8a9d9bce31c200
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/arm/armv7m.c
M include/hw/arm/armv7m.h
Log Message:
-----------
armv7m: Forward idau property to CPU object
Create an "idau" property on the armv7m container object which
we can forward to the CPU object. Annoyingly, we can't use
object_property_add_alias() because the CPU object we want to
forward to doesn't exist until the armv7m container is realized.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-6-peter.mayd...@linaro.org
Commit: 38e2a77c9d6876e58f45cabb1dd9a6a60c22b39e
https://github.com/qemu/qemu/commit/38e2a77c9d6876e58f45cabb1dd9a6a60c22b39e
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
Log Message:
-----------
target/arm: Define init-svtor property for the reset secure VTOR value
The Cortex-M33 allows the system to specify the reset value of the
secure Vector Table Offset Register (VTOR) by asserting config
signals. In particular, guest images for the MPS2 AN505 board rely
on the MPS2's initial VTOR being correct for that board.
Implement a QEMU property so board and SoC code can set the reset
value to the correct value.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-7-peter.mayd...@linaro.org
Commit: 60d75d81b59aa073e8f3ab4c81e73e534d5e7a98
https://github.com/qemu/qemu/commit/60d75d81b59aa073e8f3ab4c81e73e534d5e7a98
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/arm/armv7m.c
M include/hw/arm/armv7m.h
Log Message:
-----------
armv7m: Forward init-svtor property to CPU object
Create an "init-svtor" property on the armv7m container
object which we can forward to the CPU object.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-8-peter.mayd...@linaro.org
Commit: c7b26382fee8b745c6e903c85281babf30c2cb7c
https://github.com/qemu/qemu/commit/c7b26382fee8b745c6e903c85281babf30c2cb7c
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Add Cortex-M33
Add a Cortex-M33 definition. The M33 is an M profile CPU
which implements the ARM v8M architecture, including the
M profile Security Extension.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-9-peter.mayd...@linaro.org
Commit: a7bc4ee528c66486e43e815429b4aaf8cf2049d5
https://github.com/qemu/qemu/commit/a7bc4ee528c66486e43e815429b4aaf8cf2049d5
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/misc/unimp.c
M include/hw/misc/unimp.h
Log Message:
-----------
hw/misc/unimp: Move struct to header file
Move the definition of the struct for the unimplemented-device
from unimp.c to unimp.h, so that users can embed the struct
in their own device structs if they prefer.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-10-peter.mayd...@linaro.org
Commit: 439f122f760c0327f60228047652638d769a836c
https://github.com/qemu/qemu/commit/439f122f760c0327f60228047652638d769a836c
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M include/hw/or-irq.h
Log Message:
-----------
include/hw/or-irq.h: Add missing include guard
The or-irq.h header file is missing the customary guard against
multiple inclusion, which means compilation fails if it gets
included twice. Fix the omission.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-11-peter.mayd...@linaro.org
Commit: 4a151677a8ea80e65f519fed1df92c0db6350a02
https://github.com/qemu/qemu/commit/4a151677a8ea80e65f519fed1df92c0db6350a02
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/core/qdev.c
M include/hw/qdev-core.h
Log Message:
-----------
qdev: Add new qdev_init_gpio_in_named_with_opaque()
The function qdev_init_gpio_in_named() passes the DeviceState pointer
as the opaque data pointor for the irq handler function. Usually
this is what you want, but in some cases it would be helpful to use
some other data pointer.
Add a new function qdev_init_gpio_in_named_with_opaque() which allows
the caller to specify the data pointer they want.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-12-peter.mayd...@linaro.org
Commit: 5edb1b3fa93217cf7adc50725a69ab0cefcea973
https://github.com/qemu/qemu/commit/5edb1b3fa93217cf7adc50725a69ab0cefcea973
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/core/Makefile.objs
A hw/core/split-irq.c
A include/hw/core/split-irq.h
M include/hw/irq.h
Log Message:
-----------
hw/core/split-irq: Device that splits IRQ lines
In some board or SoC models it is necessary to split a qemu_irq line
so that one input can feed multiple outputs. We currently have
qemu_irq_split() for this, but that has several deficiencies:
* it can only handle splitting a line into two
* it unavoidably leaks memory, so it can't be used
in a device that can be deleted
Implement a qdev device that encapsulates splitting of IRQs, with a
configurable number of outputs. (This is in some ways the inverse of
the TYPE_OR_IRQ device.)
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-13-peter.mayd...@linaro.org
Commit: 9a52d9992f179416f02cef457c947a28999d879d
https://github.com/qemu/qemu/commit/9a52d9992f179416f02cef457c947a28999d879d
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/misc/Makefile.objs
A hw/misc/mps2-fpgaio.c
M hw/misc/trace-events
A include/hw/misc/mps2-fpgaio.h
Log Message:
-----------
hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505
The MPS2 AN505 FPGA image includes a "FPGA control block"
which is a small set of registers handling LEDs, buttons
and some counters.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-14-peter.mayd...@linaro.org
Commit: 9eb8040c2d2b38e1a40bb6129b1b668fa178fcab
https://github.com/qemu/qemu/commit/9eb8040c2d2b38e1a40bb6129b1b668fa178fcab
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/misc/Makefile.objs
M hw/misc/trace-events
A hw/misc/tz-ppc.c
A include/hw/misc/tz-ppc.h
Log Message:
-----------
hw/misc/tz-ppc: Model TrustZone peripheral protection controller
Add a model of the TrustZone peripheral protection controller (PPC),
which is used to gate transactions to non-TZ-aware peripherals so
that secure software can configure them to not be accessible to
non-secure software.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-15-peter.mayd...@linaro.org
Commit: de343bb632a123d7c2286e62267d6866a6b9e5f3
https://github.com/qemu/qemu/commit/de343bb632a123d7c2286e62267d6866a6b9e5f3
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/misc/Makefile.objs
A hw/misc/iotkit-secctl.c
M hw/misc/trace-events
A include/hw/misc/iotkit-secctl.h
Log Message:
-----------
hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton
The Arm IoT Kit includes a "security controller" which is largely a
collection of registers for controlling the PPCs and other bits of
glue in the system. This commit provides the initial skeleton of the
device, implementing just the ID registers, and a couple of read-only
read-as-zero registers.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-16-peter.mayd...@linaro.org
Commit: b3717c23e1c02b4f03cc4998cf41885a9db2eb03
https://github.com/qemu/qemu/commit/b3717c23e1c02b4f03cc4998cf41885a9db2eb03
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/misc/iotkit-secctl.c
M include/hw/misc/iotkit-secctl.h
Log Message:
-----------
hw/misc/iotkit-secctl: Add handling for PPCs
The IoTKit Security Controller includes various registers
that expose to software the controls for the Peripheral
Protection Controllers in the system. Implement these.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-17-peter.mayd...@linaro.org
Commit: b1ce38e12baf64c9cbe6e71c5b165a87248451b2
https://github.com/qemu/qemu/commit/b1ce38e12baf64c9cbe6e71c5b165a87248451b2
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/misc/iotkit-secctl.c
M include/hw/misc/iotkit-secctl.h
Log Message:
-----------
hw/misc/iotkit-secctl: Add remaining simple registers
Add remaining easy registers to iotkit-secctl:
* NSCCFG just routes its two bits out to external GPIO lines
* BRGINSTAT/BRGINTCLR/BRGINTEN can be dummies, because QEMU's
bus fabric can never report errors
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180220180325.29818-18-peter.mayd...@linaro.org
Commit: 9e5e54d1af26c4b0a4a32259a465b77db21900a0
https://github.com/qemu/qemu/commit/9e5e54d1af26c4b0a4a32259a465b77db21900a0
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/arm/Makefile.objs
A hw/arm/iotkit.c
A include/hw/arm/iotkit.h
Log Message:
-----------
hw/arm/iotkit: Model Arm IOT Kit
Model the Arm IoT Kit documented in
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
The Arm IoT Kit is a subsystem which includes a CPU and some devices,
and is intended be extended by adding extra devices to form a
complete system. It is used in the MPS2 board's AN505 image for the
Cortex-M33.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-19-peter.mayd...@linaro.org
Commit: 5aff1c0744a19ceec81787f8371302d2e1fc0be1
https://github.com/qemu/qemu/commit/5aff1c0744a19ceec81787f8371302d2e1fc0be1
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M hw/arm/Makefile.objs
A hw/arm/mps2-tz.c
Log Message:
-----------
mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image
Define a new board model for the MPS2 with an AN505 FPGA image
containing a Cortex-M33. Since the FPGA images for TrustZone
cores (AN505, and the similar AN519 for Cortex-M23) have a
significantly different layout of devices to the non-TrustZone
images, we use a new source file rather than shoehorning them
into the existing mps2.c.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180220180325.29818-20-peter.mayd...@linaro.org
Commit: 1dc81c15418d9b174f59a1c6262eb3487f352c56
https://github.com/qemu/qemu/commit/1dc81c15418d9b174f59a1c6262eb3487f352c56
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M linux-user/elfload.c
M target/arm/cpu.h
Log Message:
-----------
target/arm: Add ARM_FEATURE_V8_RDM
Not enabled anywhere yet.
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 5f81b1de43259ed0969e62a7419ab9dd9da2c5c0
https://github.com/qemu/qemu/commit/5f81b1de43259ed0969e62a7419ab9dd9da2c5c0
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Refactor disas_simd_indexed decode
Include the U bit in the switches rather than testing separately.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180228193125.20577-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 449f264b1749ac0e59c58bbc2eacdb3dc302c2bf
https://github.com/qemu/qemu/commit/449f264b1749ac0e59c58bbc2eacdb3dc302c2bf
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Refactor disas_simd_indexed size checks
The integer size check was already outside of the opcode switch;
move the floating-point size check outside as well. Unify the
size vs index adjustment between fp and integer paths.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180228193125.20577-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d9061ec3d27eb940402a7eafee3fb77ce1146ad4
https://github.com/qemu/qemu/commit/d9061ec3d27eb940402a7eafee3fb77ce1146ad4
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/Makefile.objs
M target/arm/helper.h
M target/arm/translate-a64.c
A target/arm/vec_helper.c
Log Message:
-----------
target/arm: Decode aa64 armv8.1 scalar three same extra
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: e7186d822955c351e4aac504380f82217c670321
https://github.com/qemu/qemu/commit/e7186d822955c351e4aac504380f82217c670321
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/helper.h
M target/arm/translate-a64.c
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Decode aa64 armv8.1 three same extra
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d345df7a3f1336ceb0537c1fa0a7261030426768
https://github.com/qemu/qemu/commit/d345df7a3f1336ceb0537c1fa0a7261030426768
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Decode aa64 armv8.1 scalar/vector x indexed element
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 36a719348a9744d17c6ef6bac01bcb5fcd279753
https://github.com/qemu/qemu/commit/36a719348a9744d17c6ef6bac01bcb5fcd279753
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Decode aa32 armv8.1 three same
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 61adacc8f589539ac6b25cfcbd6e099357188974
https://github.com/qemu/qemu/commit/61adacc8f589539ac6b25cfcbd6e099357188974
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Decode aa32 armv8.1 two reg and a scalar
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: f5dfc2ecdd48b71900bc50298ad2768d60356e44
https://github.com/qemu/qemu/commit/f5dfc2ecdd48b71900bc50298ad2768d60356e44
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable ARM_FEATURE_V8_RDM
Enable it for the "any" CPU used by *-linux-user.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180228193125.20577-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 0438f0372a7031debe796f4e3d30875d4d1e7899
https://github.com/qemu/qemu/commit/0438f0372a7031debe796f4e3d30875d4d1e7899
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M linux-user/elfload.c
M target/arm/cpu.h
Log Message:
-----------
target/arm: Add ARM_FEATURE_V8_FCMA
Not enabled anywhere yet.
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 1695cd61b08d4376c11e0658836c4f08b4fc3aa1
https://github.com/qemu/qemu/commit/1695cd61b08d4376c11e0658836c4f08b4fc3aa1
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/helper.h
M target/arm/translate-a64.c
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Decode aa64 armv8.3 fcadd
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d17b7cdcf4ea3e858ceee8b86fc8544bb71561e6
https://github.com/qemu/qemu/commit/d17b7cdcf4ea3e858ceee8b86fc8544bb71561e6
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/helper.h
M target/arm/translate-a64.c
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Decode aa64 armv8.3 fcmla
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
[PMM: renamed e1/e2/e3/e4 to use the same naming as the version
of the pseudocode in the Arm ARM]
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 8b7209fae730813d722b17a8a13b6a16c84616c8
https://github.com/qemu/qemu/commit/8b7209fae730813d722b17a8a13b6a16c84616c8
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Decode aa32 armv8.3 3-same
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180228193125.20577-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 638808ff8a0c0d62333822d3756e5d98f9f369c3
https://github.com/qemu/qemu/commit/638808ff8a0c0d62333822d3756e5d98f9f369c3
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Decode aa32 armv8.3 2-reg-index
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-15-richard.hender...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 0052087efb8a5c0e29ddc2f59f8476fcdc6495b2
https://github.com/qemu/qemu/commit/0052087efb8a5c0e29ddc2f59f8476fcdc6495b2
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Decode t32 simd 3reg and 2reg_scalar extension
Happily, the bits are in the same places compared to a32.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180228193125.20577-16-richard.hender...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078
https://github.com/qemu/qemu/commit/e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable ARM_FEATURE_V8_FCMA
Enable it for the "any" CPU used by *-linux-user.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180228193125.20577-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 86f4c7e05b1c44dbe1b329a51f311f10aef6ff34
https://github.com/qemu/qemu/commit/86f4c7e05b1c44dbe1b329a51f311f10aef6ff34
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-02 (Fri, 02 Mar 2018)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/arm/Makefile.objs
M hw/arm/armv7m.c
M hw/arm/boot.c
A hw/arm/iotkit.c
A hw/arm/mps2-tz.c
M hw/arm/xlnx-zynqmp.c
M hw/core/Makefile.objs
M hw/core/loader.c
M hw/core/qdev.c
A hw/core/split-irq.c
M hw/misc/Makefile.objs
A hw/misc/iotkit-secctl.c
A hw/misc/mps2-fpgaio.c
M hw/misc/trace-events
A hw/misc/tz-ppc.c
M hw/misc/unimp.c
M hw/timer/Makefile.objs
M hw/timer/trace-events
A hw/timer/xlnx-zynqmp-rtc.c
M include/hw/arm/armv7m.h
A include/hw/arm/iotkit.h
M include/hw/arm/xlnx-zynqmp.h
A include/hw/core/split-irq.h
M include/hw/irq.h
M include/hw/loader.h
A include/hw/misc/iotkit-secctl.h
A include/hw/misc/mps2-fpgaio.h
A include/hw/misc/tz-ppc.h
M include/hw/misc/unimp.h
M include/hw/or-irq.h
M include/hw/qdev-core.h
A include/hw/timer/xlnx-zynqmp-rtc.h
M linux-user/elfload.c
M scripts/decodetree.py
M target/arm/Makefile.objs
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/helper.h
A target/arm/idau.h
M target/arm/translate-a64.c
M target/arm/translate.c
A target/arm/vec_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180302'
into staging
target-arm queue:
* implement FCMA and RDM v8.1 and v8.3 instructions
* enable Cortex-M33 v8M core, and provide new mps2-an505 board model
that uses it
* decodetree: Propagate return value from translate subroutines
* xlnx-zynqmp: Implement the RTC device
# gpg: Signature made Fri 02 Mar 2018 11:05:40 GMT
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>"
# gpg: aka "Peter Maydell <pmayd...@gmail.com>"
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180302: (39 commits)
target/arm: Enable ARM_FEATURE_V8_FCMA
target/arm: Decode t32 simd 3reg and 2reg_scalar extension
target/arm: Decode aa32 armv8.3 2-reg-index
target/arm: Decode aa32 armv8.3 3-same
target/arm: Decode aa64 armv8.3 fcmla
target/arm: Decode aa64 armv8.3 fcadd
target/arm: Add ARM_FEATURE_V8_FCMA
target/arm: Enable ARM_FEATURE_V8_RDM
target/arm: Decode aa32 armv8.1 two reg and a scalar
target/arm: Decode aa32 armv8.1 three same
target/arm: Decode aa64 armv8.1 scalar/vector x indexed element
target/arm: Decode aa64 armv8.1 three same extra
target/arm: Decode aa64 armv8.1 scalar three same extra
target/arm: Refactor disas_simd_indexed size checks
target/arm: Refactor disas_simd_indexed decode
target/arm: Add ARM_FEATURE_V8_RDM
mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image
hw/arm/iotkit: Model Arm IOT Kit
hw/misc/iotkit-secctl: Add remaining simple registers
hw/misc/iotkit-secctl: Add handling for PPCs
...
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/2e7b766594e1...86f4c7e05b1c
