On 05/20/2011 05:31 PM, Anthony Liguori wrote:
Several alpha system chips MCE when accessed with incorrect sizes.
E.g. only 64-bit accesses are allowed.
But is this a characteristic of devices or is this a characteristic of
the chipset/CPU?
The chipset is modelled by a MemoryRegion too.
On 05/20/2011 05:46 PM, Anthony Liguori wrote:
On 05/20/2011 09:40 AM, Richard Henderson wrote:
On 05/20/2011 07:31 AM, Anthony Liguori wrote:
But is this a characteristic of devices or is this a characteristic
of the chipset/CPU?
Chipset.
So if the chipset only allows accesses that are
On 05/20/2011 09:16 PM, Blue Swirl wrote:
On Fri, May 20, 2011 at 5:46 PM, Anthony Liguorianth...@codemonkey.ws wrote:
On 05/20/2011 09:40 AM, Richard Henderson wrote:
On 05/20/2011 07:31 AM, Anthony Liguori wrote:
But is this a characteristic of devices or is this a characteristic of
On 05/20/2011 08:59 PM, Blue Swirl wrote:
On Thu, May 19, 2011 at 5:12 PM, Avi Kivitya...@redhat.com wrote:
The memory API separates the attributes of a memory region (its size, how
reads or writes are handled, dirty logging, and coalescing) from where it
is mapped and whether it is
On 05/20/2011 05:06 PM, Richard Henderson wrote:
Is this structure honestly any better than 4 function pointers?
I can't see that it is, myself.
That was requested by Anthony. And in fact we have two bits of
information per access size, one is whether the access is allowed or
not, the
On 05/20/2011 08:59 PM, Blue Swirl wrote:
On Thu, May 19, 2011 at 5:12 PM, Avi Kivitya...@redhat.com wrote:
The memory API separates the attributes of a memory region (its size, how
reads or writes are handled, dirty logging, and coalescing) from where it
is mapped and whether it is
On 05/20/2011 08:30 PM, Blue Swirl wrote:
Another case would be the cache-as-ram mode for some x86 CPUs, which
Coreboot people would like to see IIRC.
That's probably best handled as a cache emulation layer, as this is not
associated with any specific address range.
--
I have a truly
On 05/20/2011 05:51 PM, Anthony Liguori wrote:
Of course there is overlap. PCI BARs overlap each other, the VGA windows
and ROM overlap RAM.
Here's what I'm still struggling with:
If children normally overlap their parents, but child priorities are
always less than their parents, then
On 05/20/2011 02:57 PM, Gleb Natapov wrote:
On Fri, May 20, 2011 at 11:59:58AM +0300, Avi Kivity wrote:
On 05/19/2011 07:27 PM, Gleb Natapov wrote:
Think of how a window manager folds windows with priorities onto a
flat framebuffer.
You do a depth-first walk of the tree. For
On 05/20/2011 06:59 PM, Jan Kiszka wrote:
Jan had mentioned previously about registering a new temporary window.
I assume the registration always gets highest_priority++, or do you have
to explicitly specify that PCI container gets priority=1?
The latter.
And I really prefer to have
On 05/20/2011 02:25 PM, Gleb Natapov wrote:
A) Removing regions will change significantly. So far this is done by
setting a region to IO_MEM_UNASSIGNED, keeping truncation. With the new
API that will be a true removal which will additionally restore hidden
regions.
And what problem do
On 05/20/2011 03:08 PM, Gleb Natapov wrote:
On Fri, May 20, 2011 at 12:10:22PM +0300, Avi Kivity wrote:
On 05/19/2011 09:22 PM, Gleb Natapov wrote:
BARs may overlap with other BARs or with RAM. That's well-known, so PCI
bridged need to register their regions with the _overlap
On 22 May 2011, at 00:32, Brad Hards wrote:
My problem is
that, mouse is hanged in the middle of the screen.
I still don't understand the problem. I'm guessing you see the cursor in the
guest, but the host mouse isn't having any effect on that guest cursor.
I do :-)
I'm pretty sure that
Public bug reported:
version 0.14.1 when using qcow2 images, after some time, glibc detects a
double free or corruption.
** Affects: qemu
Importance: Undecided
Status: New
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to
On Sun, May 22, 2011 at 10:37:48AM +0300, Avi Kivity wrote:
On 05/20/2011 02:57 PM, Gleb Natapov wrote:
On Fri, May 20, 2011 at 11:59:58AM +0300, Avi Kivity wrote:
On 05/19/2011 07:27 PM, Gleb Natapov wrote:
Think of how a window manager folds windows with priorities onto a
flat
On 05/22/2011 11:06 AM, Gleb Natapov wrote:
On Sun, May 22, 2011 at 10:37:48AM +0300, Avi Kivity wrote:
On 05/20/2011 02:57 PM, Gleb Natapov wrote:
On Fri, May 20, 2011 at 11:59:58AM +0300, Avi Kivity wrote:
On 05/19/2011 07:27 PM, Gleb Natapov wrote:
Think of how a window
Public bug reported:
unless compiled without optimizations, no system may be ran except the default
with -kvm-enabled
I had to modify config-host.mak and remove -O2 from CFLAGS to be able to work
without kvm.
GCC 4.4.4 qemu-0.14.1
***NOTE: this has been an issue for several versions.
**
On Sun, May 22, 2011 at 10:50:22AM +0300, Avi Kivity wrote:
On 05/20/2011 02:25 PM, Gleb Natapov wrote:
A) Removing regions will change significantly. So far this is done by
setting a region to IO_MEM_UNASSIGNED, keeping truncation. With the new
API that will be a true removal which
On Sun, May 22, 2011 at 11:09:08AM +0300, Avi Kivity wrote:
On 05/22/2011 11:06 AM, Gleb Natapov wrote:
On Sun, May 22, 2011 at 10:37:48AM +0300, Avi Kivity wrote:
On 05/20/2011 02:57 PM, Gleb Natapov wrote:
On Fri, May 20, 2011 at 11:59:58AM +0300, Avi Kivity wrote:
On 05/19/2011
On Sun, May 22, 2011 at 9:45 AM, Avi Kivity a...@redhat.com wrote:
On 05/20/2011 08:59 PM, Blue Swirl wrote:
On Thu, May 19, 2011 at 5:12 PM, Avi Kivitya...@redhat.com wrote:
The memory API separates the attributes of a memory region (its size,
how
reads or writes are handled, dirty
On 05/20/2011 03:19 PM, Stefan Hajnoczi wrote:
I'm interested in what the API for snapshots would look like.
Specifically how does user software do the following:
1. Create a snapshot
2. Delete a snapshot
3. List snapshots
4. Access data from a snapshot
There are plenty of options there:
-
Did this change get submitted? Is it still an issue?
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https://bugs.launchpad.net/bugs/618533
Title:
OpenSolaris guest fails to see the Solaris partitions of a physical
disk in
On 2011-05-22 10:41, Gleb Natapov wrote:
The chipset knows about the priorities. How to communicate them to
the core?
- at runtime, with hierarchical dispatch of -read() and -write():
slow, and doesn't work at all for RAM.
- using registration order: fragile
- using priorities
- by
On Tue, May 17, 2011 at 5:42 PM, Richard Henderson r...@twiddle.net wrote:
On 05/14/2011 12:37 PM, Blue Swirl wrote:
tb_invalidate_page_range() was intended to be used to invalidate an area of
a TB
which the guest explicitly flushes from i-cache. However, QEMU detects writes
to code areas
From: Jan Kiszka jan.kis...@siemens.com
-machine somehow suggests that it selects the machine, but it doesn't.
Fix that before this command is set in stone.
Actually, -machine should supersede -M and allow to introduce arbitrary
per-machine options to the command line. That will change the
There is little in common with user and softmmu versions of cpu_resume_signal(),
split them.
Fix coding style for the user emulator part.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
cpu-exec.c | 303 ++--
1 files changed, 172
Now that all targets use common function signature for do_interrupt(),
there is no
need for the #ifdeffery anymore.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
cpu-exec.c | 26 --
1 files changed, 0 insertions(+), 26 deletions(-)
diff --git a/cpu-exec.c
This is still RFC. All except 9 seem to be OK, but 9 needs review.
M68k patch (5) is untested.
Patch 9 seems to be OK for x86_64 and Sparc64, but i386 crashes for
some reason I can't see. Other architectures are untested, especially
ia64 could be wrong.
Blue Swirl (9):
cpu_loop_exit: avoid
Make cpu_loop_exit() take a parameter for CPUState instead of relying
on global env.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
cpu-exec.c| 16
exec-all.h|2 +-
hw/alpha_palcode.c|2 +-
Before the next patch, fix coding style of the areas affected.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
target-sparc/op_helper.c | 31 +--
1 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
Several x86 specific functions are called from cpu-exec.c with the
assumption that global env register is valid. This will be changed
later, so make the functions use caller supplied CPUState parameter.
It would be cleaner to move the functions to helper.c, but there are
quite a lot of
Pass CPUState to do_interrupt(). This is needed by later patches.
It would be cleaner to move the function to helper.c, but there are
a few dependencies between do_interrupt() and other functions.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
cpu-exec.c |4 ++--
do_interrupt() was mixing CPUState pointer passed from caller
and global env (AREG0).
Fix by moving the function to helper.c. Introduce a helper for calling
change_pstate() safely from outside of execution context.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
target-sparc/cpu.h |
Before the next patch, fix coding style of the areas affected.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
target-alpha/exec.h |2 +-
target-arm/exec.h|4 ++--
target-cris/exec.h |2 +-
target-m68k/exec.h |2 +-
target-microblaze/exec.h |2 +-
Make functions take a parameter for CPUState instead of relying
on global env. Pass CPUState pointer to TCG prologue, which moves
it to AREG0.
Revert the hacks to avoid AREG0 use on Sparc hosts.
Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h.
Compile the file without
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is
needed by later patches.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
exec-all.h |1 +
target-alpha/cpu.h | 12 +++
target-alpha/exec.h | 10 -
target-arm/cpu.h
On 05/22/2011 01:53 PM, Jan Kiszka wrote:
On 2011-05-22 10:41, Gleb Natapov wrote:
The chipset knows about the priorities. How to communicate them to
the core?
- at runtime, with hierarchical dispatch of -read() and -write():
slow, and doesn't work at all for RAM.
- using
On 2011-05-22 13:18, Blue Swirl wrote:
Before the next patch, fix coding style of the areas affected.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
target-alpha/exec.h |2 +-
target-arm/exec.h|4 ++--
target-cris/exec.h |2 +-
target-m68k/exec.h
From: Jan Kiszka jan.kis...@siemens.com
This was obsoleted by 6792a57bf1.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
Noticed while reading your split-up patches.
cpu-exec.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index
On 05/22/2011 12:32 PM, Blue Swirl wrote:
+void memory_region_add_coalescing(MemoryRegion *mr,
+ target_phys_addr_t offset,
+ target_phys_addr_t size);
+/* Disable MMIO coalescing for the region. */
Subject: [PATCH] XBRLE page delta compression for live migration of large
memory apps
From: Aidan Shribman aidan.shrib...@sap.com
By using XBRLE (Xor Based Run-Length-Encoding) we can reduce required
bandwidth for transfering of dirty memory pages during live migration
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
tcg/tcg.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index cecef63..183a446 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -129,7 +129,7 @@ typedef tcg_target_ulong TCGArg;
We use plain int by
Thanks to Tobias Hoffmann t...@gmx.de for this patch.
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
hw/pflash_cfi02.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index 8fdafe6..725cd1e 100644
--- a/hw/pflash_cfi02.c
+++
On Sun, May 22, 2011 at 2:36 PM, Avi Kivity a...@redhat.com wrote:
On 05/22/2011 12:32 PM, Blue Swirl wrote:
+void memory_region_add_coalescing(MemoryRegion *mr,
+ target_phys_addr_t offset,
+
Am 07.05.2011 22:15, schrieb Stefan Weil:
cppcheck report:
rbd.c:246: style: Variable 'snap' is assigned a value that is never used
Remove snap and the related code.
Cc: Christian Brunnerc...@muc.de
Cc: Kevin Wolfkw...@redhat.com
Signed-off-by: Stefan Weilw...@mail.berlios.de
---
block/rbd.c
+static void gen_load_store_alignment(DisasContext *dc, int shift, TCGv_i32
addr)
+{
+TCGv_i32 tmp = tcg_temp_local_new_i32();
+tcg_gen_mov_i32(tmp, addr);
+tcg_gen_andi_i32(addr, addr, ~0 shift);
+if (option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
+
On 05/22/2011 03:06 PM, Blue Swirl wrote:
On Sun, May 22, 2011 at 2:36 PM, Avi Kivitya...@redhat.com wrote:
On 05/22/2011 12:32 PM, Blue Swirl wrote:
+void memory_region_add_coalescing(MemoryRegion *mr,
+ target_phys_addr_t offset,
Am 01.04.2011 13:43, schrieb Isaku Yamahata:
optimize irq routing in piix_pic.c which has been a TODO.
So far piix3 tracks each pirq level and checks whether a given pic pins is
asserted by seeing if each pirq is mapped into the pic pin.
This is independent on irq routing, but data path is on
On 05/22/2011 11:59 AM, Gleb Natapov wrote:
There is no problem. If the PCI bus priority is higher than RAM
priority, then PCI BARs will override RAM.
So if memory region has no subregion that covers part of the region
lower prio region is used? Now the same with the pictures:
-- root
I did a patch for it.
http://lists.gnu.org/archive/html/qemu-devel/2011-05/msg01239.html
On Sun, May 22, 2011 at 20:24, Stefan Weil w...@mail.berlios.de wrote:
Hi,
I got a regression report which was obviously caused by this commit:
$ git bisect bad
ab431c283e7055bcd6fb622f212bb29e84a6a134
On Sun, May 22, 2011 at 3:18 PM, Avi Kivity a...@redhat.com wrote:
On 05/22/2011 03:06 PM, Blue Swirl wrote:
On Sun, May 22, 2011 at 2:36 PM, Avi Kivitya...@redhat.com wrote:
On 05/22/2011 12:32 PM, Blue Swirl wrote:
+void memory_region_add_coalescing(MemoryRegion *mr,
On 05/22/2011 06:32 PM, Blue Swirl wrote:
Can you suggest an alternative naming for the API?
How about
memory_region_container_init()
memory_region_add()
I'm neutral. If someone seconds this, I'll make it so.
--
I have a truly marvellous patch that fixes the bug which this
signature is
On Sun, May 22, 2011 at 1:43 PM, Brad Hards br...@frogmouth.net wrote:
Did this change get submitted? Is it still an issue?
At least the patch hasn't been applied. I don't remember seeing it in the list.
On 05/22/2011 02:38 AM, Avi Kivity wrote:
On 05/20/2011 06:59 PM, Jan Kiszka wrote:
Jan had mentioned previously about registering a new temporary window.
I assume the registration always gets highest_priority++, or do you
have
to explicitly specify that PCI container gets priority=1?
The
On 05/22/2011 01:38 AM, Avi Kivity wrote:
On 05/20/2011 05:31 PM, Anthony Liguori wrote:
Several alpha system chips MCE when accessed with incorrect sizes.
E.g. only 64-bit accesses are allowed.
But is this a characteristic of devices or is this a characteristic of
the chipset/CPU?
The
On 05/22/2011 01:39 AM, Avi Kivity wrote:
On 05/20/2011 05:46 PM, Anthony Liguori wrote:
On 05/20/2011 09:40 AM, Richard Henderson wrote:
On 05/20/2011 07:31 AM, Anthony Liguori wrote:
But is this a characteristic of devices or is this a characteristic
of the chipset/CPU?
Chipset.
So if
On 05/22/2011 06:46 PM, Anthony Liguori wrote:
MemoryRegion *is* the dispatch path. Only done declaratively so we can
flatten it whenever it changes.
We don't want dispatch to be 100% declarative. That's what will cause
the API to get horrendously ugly.
An example is PCI-bus level
On 05/22/2011 06:44 PM, Anthony Liguori wrote:
At any rate, I'm fairly sure it doesn't belong in the MemoryRegion
structure.
Since it isn't a global property, where does it belong?
The chipset should have an intercept in the dispatch path that
enforces this (this assumes hierarchical
apt-get install gobject-introspection libgirepository1.0-dev
./configure --prefix=/usr --build=x86_64-linux-gnu \
--mandir=/usr/share/man --infodir=/usr/share/info --datadir=/usr/share \
--sysconfdir=/etc --localstatedir=/var --libexecdir=/usr/bin \
--with-python --disable-static
# dpkg -i --force-overwrite ./spice-gtk_0.6-1_amd64.deb
Generates :-
root@boris-System-P5Q3:/usr/src/SPICE_GTK_0.6/WORK/usr# ls -CR
.:
bin include lib share
./bin:
snappy spicy
./include:
spice-client-glib-2.0 spice-client-gtk-2.0 spice-controller
./include/spice-client-glib-2.0:
On Sun, May 22, 2011 at 2:18 PM, Blue Swirl blauwir...@gmail.com wrote:
Make functions take a parameter for CPUState instead of relying
on global env. Pass CPUState pointer to TCG prologue, which moves
it to AREG0.
I found the problem with this patch on i386, TCG assumes that its
caller is
On 05/22/2011 05:10 AM, Max Filippov wrote:
There are three alignment possibilities for xtensa: no unaligned
exception, unaligned exception and hardware alignment. In the first
case unaligned access silently goes to aligned address. It looks like
it cannot be done via do_unaligned_access, can
On 22 May 2011 17:55, Blue Swirl blauwir...@gmail.com wrote:
For ARM, the handcrafted instructions below need to be changed to save also
r7:
/* stmdb sp!, { r4 - r6, r8 - r11, lr } */
tcg_out32(s, (COND_AL 28) | 0x092d4f70);
/* ldmia sp!, { r4 - r6, r8 - r11, pc } */
On Sun, May 22, 2011 at 7:10 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 May 2011 17:55, Blue Swirl blauwir...@gmail.com wrote:
For ARM, the handcrafted instructions below need to be changed to save also
r7:
/* stmdb sp!, { r4 - r6, r8 - r11, lr } */
tcg_out32(s, (COND_AL
On 22 May 2011 18:33, Laurent Desnogues laurent.desnog...@gmail.com wrote:
On Sun, May 22, 2011 at 7:10 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 22 May 2011 17:55, Blue Swirl blauwir...@gmail.com wrote:
For ARM, the handcrafted instructions below need to be changed to save also
On Mon, May 16, 2011 at 07:50:55PM +0800, TeLeMan wrote:
If pic_irq is greater than 7, the irq level is always 0 on 32bits.
Signed-off-by: TeLeMan gele...@gmail.com
Good catch
Acked-by: Michael S. Tsirkin m...@redhat.com
---
hw/piix_pci.c |2 +-
1 files changed, 1 insertions(+), 1
Am 22.05.2011 21:06, schrieb Michael S. Tsirkin:
On Mon, May 16, 2011 at 07:50:55PM +0800, TeLeMan wrote:
If pic_irq is greater than 7, the irq level is always 0 on 32bits.
Signed-off-by: TeLeMan gele...@gmail.com
Good catch
Acked-by: Michael S. Tsirkin m...@redhat.com
The patch fixes
** Attachment added: spice-gtk-0.6-1ubuntu1_0.6-1_amd64.deb
https://bugs.launchpad.net/qemu/+bug/723871/+attachment/2138919/+files/spice-gtk-0.6-1ubuntu1_0.6-1_amd64.deb
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There are three alignment possibilities for xtensa: no unaligned
exception, unaligned exception and hardware alignment. In the first
case unaligned access silently goes to aligned address. It looks like
it cannot be done via do_unaligned_access, can it? In the third case
most unaligned
From: Peter Maydell peter.mayd...@linaro.org
Remove a duplicate #include of sysbus.h.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Stefan Hajnoczi stefa...@linux.vnet.ibm.com
---
hw/realview.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git
From: Stefan Weil w...@mail.berlios.de
Signed-off-by: Stefan Weil w...@mail.berlios.de
Signed-off-by: Stefan Hajnoczi stefa...@linux.vnet.ibm.com
---
exec.c|2 +-
target-ppc/STATUS |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index
From: Peter Maydell peter.mayd...@linaro.org
The SDIO specification introduces new commands 52 and 53.
Handle as illegal command but do not complain on stderr,
as SDIO-aware OSes (including Linux) may legitimately use
these in their probing for presence of an SDIO card.
Signed-off-by: Peter
From: TeLeMan gele...@gmail.com
If pic_irq is greater than 7, the irq level is always 0 on 32bits.
Signed-off-by: TeLeMan gele...@gmail.com
Signed-off-by: Stefan Hajnoczi stefa...@linux.vnet.ibm.com
---
hw/piix_pci.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
The following changes since commit dcfd14b3741983c466ad92fa2ae91eeafce3e5d5:
Delete unused tb_invalidate_page_range (2011-05-22 10:47:28 +)
are available in the git repository at:
git://repo.or.cz/qemu/stefanha.git trivial-patches
I must have lost Stefan Weil's patch last pull request.
LinkedIn
This invitation is awaiting your response:
From Paulo Silva
--
(c) 2011, LinkedIn Corporation
Thank you.
Acked-by: Isaku Yamahata yamah...@valinux.co.jp
On Mon, May 16, 2011 at 07:50:55PM +0800, TeLeMan wrote:
If pic_irq is greater than 7, the irq level is always 0 on 32bits.
Signed-off-by: TeLeMan gele...@gmail.com
---
hw/piix_pci.c |2 +-
1 files changed, 1 insertions(+), 1
On Fri, May 20, 2011 at 11:14 PM, Anthony Liguori anth...@codemonkey.ws wrote:
On 05/20/2011 05:59 AM, Stefan Hajnoczi wrote:
To run automated tests for coroutines:
make check-coroutine
./check-coroutine
On success the program terminates with exit status 0. On failure an
error
Hello Stefan,
I have been thinking about this since you sent out this message.
A quick look at the libvirt API indicates that their notion of a
snapshot often refers to a disk+memory snapshot. It would
be good to provide feedback to the libvirt developers to make
sure that proper support for a
On 05/18/2011 04:54 PM, Michael S. Tsirkin wrote:
On Wed, May 18, 2011 at 01:57:37PM +0800, Jason Wang wrote:
Current vm_running was not explicitly initialized and its value was changed by
vm state notifier, this may confuse the virtio device being hotplugged such as
virtio-net with vhost
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