- Original Message -
From: Onkar N Mahajan kern...@gmail.com
To: k...@vger.kernel.org, qemu-devel@nongnu.org
Sent: Thursday, September 29, 2011 6:03:26 AM
Subject: balloon drivers missing in virtio-win-1.1.16.vfd
virtio_balloon drivers are missing in the virtio-win floppy disk
On 2011-10-06 03:13, liu ping fan wrote:
On Wed, Oct 5, 2011 at 7:01 PM, Jan Kiszka jan.kis...@web.de wrote:
On 2011-10-05 12:26, liu ping fan wrote:
And make the creation of apic as part of cpu initialization, so
apic's state has been ready, before setting kvm_apic.
There is no kvm-apic
The MPIC has some funny feature where it maps different registers to an MMIO
region depending which CPU accesses them.
To be able to reflect that, we need to make OpenPIC be compiled in the target
code, so it can access cpu_single_env.
Signed-off-by: Alexander Graf ag...@suse.de
---
We need to find out the host's clock-frequency when running on KVM, so
let's export a respective function.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- enable 64bit values
---
target-ppc/kvm.c | 67 ++
target-ppc/kvm_ppc.h
When running PR style KVM, we need to tell the kernel that we want
to run in PAPR mode now. This means that we need to pass some more
register information down and enable papr mode. We also need to align
the HTAB to htab_size boundary.
Using this patch, -M pseries works with kvm even on non-hv
On 6 October 2011 04:43, TusharK meet...@rediffmail.com wrote:
(1) Does your kernel boot on the real hardware?
I do not have real hardware to test my kernel. But what I did was, I
downloaded pre-built kernel image from
http://code.google.com/p/smp-on-qemu/downloads/list website and
tried to
This patch updates the kvm kernel headers to the latest version.
Signed-off-by: Alexander Graf ag...@suse.de
---
linux-headers/asm-powerpc/kvm.h | 23 +++
linux-headers/asm-x86/kvm_para.h | 14 ++
linux-headers/linux/kvm.h| 25
From: Stefan Hajnoczi stefa...@linux.vnet.ibm.com
The RAM_ADDR_FMT macro hides the type of ram_addr_t so that format
strings can be safely used. Make sure to use RAM_ADDR_FMT so that the
build works on 32-bit hosts with Xen enabled. Whether Xen should affect
ppc TCG targets is questionable but
From: Breno Leitao bren...@br.ibm.com
Currently there is no implementation for set-time-of-day rtas function,
which causes the following warning setting the clock failed (-1) on
the guest.
This patch just creates this function, get the timedate diff and store in
the papr environment, so that the
When running with PR KVM, we need to set HIOR directly. Thankfully there
is now a new interface to set registers individually so we can just use that
and poke HIOR into the guest vcpu's HIOR register.
While at it, this also sets SDR1 because -M pseries requires it to run.
With this patch, -M
From: Paolo Bonzini pbonz...@redhat.com
This also lets the user see the irq in info qtree.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Cc: Alexander Graf ag...@suse.de
Cc: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/spapr_vio.c |8
Hello,
Actually the test case that I suggested is a bit imprecise because
creating a reservation on a CPU does not cause loss of reservation
on other CPUs (I mean in the specification). It is writing to the
memory location that causes loss of reservation. Therefore the correct
test case would be
From: David Gibson da...@gibson.dropbear.id.au
The interrupt controller presented in the device tree for the pseries
machine is manipulated by the guest only through hypervisor calls. It
has no real or emulated registers for the guest to access.
However, it currently has a bogus 'reg' property
The guest OS wants to know where the guest spins, so let's tell him while
updating the CPU nodes with the frequencies anyways.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- use new spin table address
---
hw/ppce500_mpc8544ds.c |6 ++
1 files changed, 6 insertions(+), 0
On 10/05/2011 09:45 PM, Anthony Liguori wrote:
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size1)
{
int size, l;
Can we implement get_buffer in terms of peek_buffer and just increment
f-buf_index in get_buffer?
No, get_buffer works even if size1 is greater than the size of
The MPIC exports a page for each CPU that it controls. To support more than
one CPU, we need to also reserve the MMIO space according to the amount of
CPUs we want to support.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
From: Andreas Färber afaer...@suse.de
Since commit 8733f609 (Fix linker scripts) linking on Linux/ppc64 fails:
LINK ppc64-linux-user/qemu-ppc64
/usr/lib64/gcc/powerpc64-suse-linux/4.3/../../../../powerpc64-suse-linux/bin/ld:/home/afaerber/qemu/ppc64.ld:84:
syntax error
collect2: ld gab 1 als
From: David Gibson da...@gibson.dropbear.id.au
This patch adds support for the H_REMOVE_BULK hypercall on the pseries
machine. Strictly speaking this isn't necessarym since the kernel will
only attempt to use this if hcall-bulk is advertised in the device tree,
which previously it was not.
Update HIOR and generic register get/set.
Signed-off-by: Alexander Graf ag...@suse.de
---
linux-headers/asm-powerpc/kvm.h |2 ++
linux-headers/linux/kvm.h | 33 +
2 files changed, 35 insertions(+), 0 deletions(-)
diff --git
From: Scott Wood scottw...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
hmp-commands.hx |2 +-
monitor.c |5 ++-
target-ppc/cpu.h|2 +
target-ppc/helper.c | 88
From: Paolo Bonzini pbonz...@redhat.com
Restructure common properties for sPAPR devices so that IRQ definitions
can be added in one place.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Cc: Alexander Graf ag...@suse.de
Cc: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf
Hi Blue,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit e4fc8781db7c49b0c5ac5d24762e17c59dfe0871:
Stefan Hajnoczi (1):
qed: fix use-after-free during l2 cache commit
are available in the git repository at:
We use the IDE register with IPIs as a mask to keep track which processors
have already acknowledged the respective interrupt. So we need to initialize
it to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the
first IPI is triggered.
Reported-by: Elie Richa ri...@adacore.com
When creating a VM, we should go through smp_cpus and create a virtual CPU for
every CPU the user requested. This patch adds support for that and moves some
code around to make that more convenient.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppce500_mpc8544ds.c | 44
The BookE timer code had some written-but-not-read variables. Get rid
of them.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc_booke.c | 14 +-
1 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/hw/ppc_booke.c b/hw/ppc_booke.c
index 3e2fff5..8871945 100644
---
Now that we can so nicely find out the host's frequencies, we should also
make sure that we get them into all virtual CPUs' device tree nodes.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppce500_mpc8544ds.c | 10 +++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git
From: David Gibson da...@gibson.dropbear.id.au
PAPR systems support several hypercalls intended for use in real mode
debugging tools. These implement reads and writes to arbitrary guest
physical addresses. This is useful for real mode software because it
allows access to IO addresses and memory
We have some code in generic kvm_ppc.c that is only used by 440. Move to
the 440 specific device code.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc440_bamboo.c | 37 +++--
target-ppc/kvm_ppc.c | 30 --
On 10/05/2011 10:25 PM, Juan Quintela wrote:
Anthony Liguorianth...@codemonkey.ws wrote:
On 10/04/2011 09:49 AM, Juan Quintela wrote:
Anthony Liguorianth...@codemonkey.ws wrote:
On 09/23/2011 07:57 AM, Juan Quintela wrote:
[ much more stuff ]
It avoids s==NULL checks,
In favor of
We only support -M pseries when certain prerequisites are met, such
as a PPC64 guest and libfdt. To only gather these requirements in
a single place, this patch introduces a new CONFIG_PSERIES variable
that gets set when all prerequisites are met.
Signed-off-by: Alexander Graf ag...@suse.de
---
From: David Gibson da...@gibson.dropbear.id.au
The implementation of the XICS interrupt controller contains several
(difficult to trigger) bugs due to the fact that we were not 100%
consistent with which irq numbering we used. In most places, global
numbers were used as handled by the
From: Paolo Bonzini pbonz...@redhat.com
Right now the spapr devices cannot be instantiated with -device,
because the IRQs need to be passed to the spapr_*_create functions.
Do this instead in the bus's init wrapper.
This is particularly important with the conversion from scsi-disk
to
Now that we have generic KVM functions to read out the host tb and clock
frequencies, let's use them in the e500 code!
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppce500_mpc8544ds.c | 44 +---
1 files changed, 9 insertions(+), 35 deletions(-)
From: David Gibson da...@gibson.dropbear.id.au
Paulo Bonzini changed the original spapr code, which manually assigned irq
numbers for each virtual device, to allocate them automatically from the
device initialization. That allowed spapr virtual devices to be constructed
with -device, which is a
From: Paolo Bonzini pbonz...@redhat.com
I introduced this bug in commit 05751d3 (vscsi: always use get_sense,
2011-08-03) because at the time there was no way to expose a sense
condition to SLOF and Linux manages to work around the bug. However,
the bug becomes evident now that SCSI devices also
Another round of KVM features, another round of kernel header updates :)
Signed-off-by: Alexander Graf ag...@suse.de
---
linux-headers/asm-powerpc/kvm.h | 40 +++
linux-headers/linux/kvm.h | 18 +
2 files changed, 58 insertions(+), 0
The MPIC exports a register set for each CPU connected to it. They can all
be accessed through specific registers or using a shadow page that is mapped
differently depending on which CPU accesses it.
This patch implements the shadow map, making it possible for guests to access
the CPU local
From: Fabien Chouteau chout...@adacore.com
Signed-off-by: Fabien Chouteau chout...@adacore.com
Signed-off-by: Alexander Graf ag...@suse.de
---
gdbstub.c |2 +-
target-ppc/translate_init.c |3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/gdbstub.c
Commit 23c5e4ca (convert to memory API) broke the VIA Cuda emulation layer
by not registering the IO structs.
This patch registers them properly and thus makes -M g3beige and -M mac99
work again.
Tested-by: Andreas Färber andreas.faer...@web.de
Signed-off-by: Alexander Graf ag...@suse.de
---
CPUs that are not the boot CPU need to run in spinning code to check if they
should run off to execute and if so where to jump to. This usually happens
by leaving secondary CPUs looping and checking if some variable in memory
changed.
In an environment like Qemu however we can be more clever. We
When we screw up and issue an FDT command that doesn't work, we really need to
know immediately and usually can't continue to create the machine. To make sure
we don't need to add error checking in all device tree modification code users,
we can just add the fail checks to the qemu abstract
During the memory API conversion, the indication on little endianness of
MMIO for the heathrow PIC got dropped. This patch adds it back again.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/heathrow_pic.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
The IPI dispatch registers are write only according to every MPIC
spec I have found. So instead of pretending you could read back something
from them, better not handle them at all.
Reported-by: Elie Richa ri...@adacore.com
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c |7
The current IPI support in the MPIC code is incomplete and doesn't work. This
code adds proper support for IPIs in MPIC by using the IDE register to remember
which CPUs IPIs are still outstanding to. New triggers through the IPI trigger
register only add to the list of CPUs we want to IPI.
From: Scott Wood scottw...@freescale.com
Share the TLB array with KVM. This allows us to set the initial TLB
both on initial boot and reset, is useful for debugging, and could
eventually be used to support migration.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander
The bit definitions for critical interrupt routing are in PowerPC order
(most significant bit is 0), while we end up shifting it with normal bit
order. Turn the numbers around so we actually end up fetching the
right ones.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 10
Now that we have nice and shiny APIs to read out the host's clock and timebase
frequencies, let's use them in the bamboo code as well!
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc440_bamboo.c | 45 -
1 files changed, 12 insertions(+), 33
From: Elie Richa ri...@adacore.com
In the current emulation of the load-and-reserve (lwarx) and
store-conditional (stwcx.) instructions, the internal reservation
mechanism is taken into account, however each CPU has its own
reservation information and this information is not synchronized between
From: Fabien Chouteau chout...@adacore.com
While working on the emulation of the freescale p2010 (e500v2) I realized that
there's no implementation of booke's timers features. Currently mpc8544 uses
ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for
example booke uses
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in
the code exporting the numbers out and fix an integer overflow while at it.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- Max cpus is 15 due to cINT routing
- Report nb_cpus not MAX_CPUS in MPIC
The helper function read_IRQreg was always called with a specific argument on
the type of register to access. Inside the function we were simply doing a
switch on that constant argument again. It's a lot easier to just unfold this
into two separate functions and call each individually.
We don't need mpc8544_copy_soc_cell anymore, since we're explicitly reading
host values and writing guest values respectively.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppce500_mpc8544ds.c | 24
1 files changed, 0 insertions(+), 24 deletions(-)
diff --git
We have a qemu internal abstraction layer on FDT. While I'm not fully convinced
we need it at all, it's missing the nop_node functionality that we now need
on e500. So let's add it and think about the general future of that API later.
Signed-off-by: Alexander Graf ag...@suse.de
---
device_tree.c
From: David Gibson da...@gibson.dropbear.id.au
This patch implements support for the CFAR SPR on POWER7 (Come From
Address Register), which snapshots the PC value at the time of a branch or
an rfid. The latest powerpc-next kernel also catches it and can show it in
xmon or in the signal frames.
We should only keep CPU nodes in the device tree around that we really have
virtual CPUs for. So remove all superfluous entries that we just keep there
in case someone wants to create a lot of vCPUs.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppce500_mpc8544ds.c |6 ++
1 files
Now that we have everything in place, make the machine description
aware of the fact that we can now handle 15 virtual CPUs!
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- Max cpus is 15 because of MPIC
---
hw/ppce500_mpc8544ds.c |1 +
1 files changed, 1 insertions(+), 0
From: Nishanth Aravamudan n...@us.ibm.com
For some time we've had a nicely defined macro with the filename for our
firmware image. However we didn't actually use it in the place we're
supposed to. This patch fixes it.
Signed-off-by: Nishanth Aravamudan n...@us.ibm.com
Signed-off-by: David
We have a bunch of helper functions that don't have any stubs for them in case
we don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc can
optimize them out pretty well, but we should really provide them.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- use
Removes ABI-breaking HIOR parts - KVM patch to follow.
Signed-off-by: Alexander Graf ag...@suse.de
---
linux-headers/asm-powerpc/kvm.h |8
linux-headers/linux/kvm.h |1 -
2 files changed, 0 insertions(+), 9 deletions(-)
diff --git a/linux-headers/asm-powerpc/kvm.h
From: Scott Wood scottw...@freescale.com
This definition is backward compatible with MAV=1.0 as long as
the guest does not set reserved bits in MAS1/MAS4.
Also, fix the shift in booke206_tlb_to_page_size -- it's the base
that should be able to hold a 4G page size, not the shift count.
The helper function write_IRQreg was always called with a specific argument on
the type of register to access. Inside the function we were simply doing a
switch on that constant argument again. It's a lot easier to just unfold this
into two separate functions and call each individually.
One of the things we can't fake on PPC is the timer speed. So
we need to extract the frequency information from the host and
put it back into the guest device tree.
Luckily, we already have functions for that from the non-pseries
targets, so all we need to do is to connect the dots and the guest
From: Laurent Vivier laur...@vivier.eu
Allow to use ADB in non-ppc macintosh
Signed-off-by: Laurent Vivier laur...@vivier.eu
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/adb.c |2 +-
hw/adb.h | 67 +
hw/cuda.c
From: David Gibson da...@gibson.dropbear.id.au
Future devices we will be adding to the pseries machine (e.g. PCI) will
need nodes in the device tree which explicitly reference the top-level
interrupt controller via interrupt-parent or interrupt-map properties.
In order to do this, the interrupt
With this patch, we generate CPU nodes in the machine initialization, giving
us the freedom to generate as many nodes as we want and as the machine supports,
but only those.
This is a first step towards a much cleaner device tree generation
infrastructure, where we would not require precompiled
We want to be able to create subnodes in our device tree, so export it through
the qemu device tree abstraction framework.
Signed-off-by: Alexander Graf ag...@suse.de
---
device_tree.c | 24
device_tree.h |1 +
2 files changed, 25 insertions(+), 0 deletions(-)
We want to generate the CPU nodes in machine init code, so remove them from
the device tree definition that we precompile.
Signed-off-by: Alexander Graf ag...@suse.de
---
pc-bios/mpc8544ds.dtb | Bin 2277 - 2028 bytes
pc-bios/mpc8544ds.dts | 12
2 files changed, 0 insertions(+),
We currently load a device tree blob and then just take its size x2 to
account for modifications we do inside. While this is nice and great,
it fails when we have a small device tree as blob and lots of nodes added
in machine init code.
So for now, just make it 20k bigger than it was before. We
We just got rid of the last user of kvmppc_read_host_property, so we
can now safely remove it.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/kvm_ppc.c | 35 ---
target-ppc/kvm_ppc.h | 11 ---
2 files changed, 0 insertions(+), 46
Now that we can generate multiple envs for all our virtual CPUs, we
also need to tell the MPIC that we have multiple CPUs connected and
connect them all to the respective virtual interrupt lines.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppce500_mpc8544ds.c | 17 -
1
On 30.09 2011 11:45, Sasha Levin wrote:
Subject: [PATCH v2] tap: Add optional parameters to up/down script
This allows the user to add custom parameters to the up or down
scripts.
Extra parameters are useful in more complex networking scenarios
where we would like to configure network
Am 02.10.2011 23:44, schrieb Peter Maydell:
On 2 October 2011 19:56, Andreas Färber andreas.faer...@web.de wrote:
I've been looking into adding support for Cortex-R4F.
Ooh, that will be the first R profile core. In particular the only
other non-M-profile PMSA core we support is the 946 which
From: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/lan9118.c | 29 +++--
1 files changed, 11 insertions(+), 18 deletions(-)
diff --git a/hw/lan9118.c b/hw/lan9118.c
index
Review before push. I see that Alex's patch is also in the ppc queue, I'll
drop it if it's merged before.
Alexander Graf (1):
PPC: Fix via-cuda memory registration
Avi Kivity (7):
palm: convert to memory API
petalogix_ml605: convert to memory API
petalogix_s2adsp1800: convert to memory
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/palm.c | 53 +
1 files changed, 25 insertions(+), 28 deletions(-)
diff --git a/hw/palm.c b/hw/palm.c
index d8f50e3..094bfde 100644
--- a/hw/palm.c
+++ b/hw/palm.c
@@ -54,16 +54,12 @@ static
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/gus.c | 39 +++
1 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/hw/gus.c b/hw/gus.c
index
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/mc146818rtc.c | 15 ---
1 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index
Add a type and methods for manipulating a list of disjoint I/O ports,
used in some older hardware devices.
Based on original patch by Richard Henderson.
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
Makefile.objs |2 +-
Makefile.target |
On 6 October 2011 11:16, Andreas Färber andreas.faer...@web.de wrote:
Am 02.10.2011 23:44, schrieb Peter Maydell:
On 2 October 2011 19:56, Andreas Färber andreas.faer...@web.de wrote:
1) Currently, -cpu is used to look up a Main ID Register value and to base
feature decisions on that. This
From: Jan Kiszka jan.kis...@siemens.com
As we register old portio regions via ioport_register, we are also
responsible for providing the word access wrapper.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Signed-off-by: Avi Kivity a...@redhat.com
---
memory.c | 10 ++
1 files
From: Richard Henderson r...@twiddle.net
[jan: fix cut'n'paste errors]
[avi: adjust pci variants not to use isa functions]
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/qxl.c|2 +-
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/petalogix_s3adsp1800_mmu.c | 18 ++
1 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
index 66fb96d..17da2fd 100644
--- a/hw/petalogix_s3adsp1800_mmu.c
From: Richard Henderson r...@twiddle.net
All users have been converted to either isa_register_ioport
or isa_register_old_portio_list.
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/isa-bus.c | 19 +--
hw/isa.h |2 --
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/fdc.c | 34 --
1 files changed, 4 insertions(+), 30 deletions(-)
diff --git a/hw/fdc.c b/hw/fdc.c
index 0f1cee9..4b06e04
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/parallel.c | 47 ---
1 files changed, 28 insertions(+), 19 deletions(-)
diff --git a/hw/parallel.c
On 10/05/2011 08:50 PM, Luiz Capitulino wrote:
I'm not exactly against the semantics you're proposing, but they don't
seem to fit today's qemu.
Today's qemu is broken here.
For me it's broken because it will abort() if you migrate a paused vm, for
you it seems to be
From: Peter Maydell peter.mayd...@linaro.org
Clean up versatile_pci to expose the various PCI mmio regions
properly as separate mmio regions rather than as a single mmio
which uses callbacks to map and unmap everything.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Avi
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/ppc_newworld.c | 39 +--
1 files changed, 17 insertions(+), 22 deletions(-)
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index b1cc3d7..946070c 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/sb16.c | 32 +---
1 files changed, 13 insertions(+), 19 deletions(-)
diff --git a/hw/sb16.c b/hw/sb16.c
index
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/petalogix_ml605_mmu.c | 15 +++
1 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index 2a0f7fd..fb4ba29 100644
--- a/hw/petalogix_ml605_mmu.c
+++
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/ppc405_boards.c | 84 +++-
1 files changed, 37 insertions(+), 47 deletions(-)
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index ca65ac3..b28bdda 100644
--- a/hw/ppc405_boards.c
+++
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/ne2000-isa.c |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/hw/ne2000-isa.c b/hw/ne2000-isa.c
index 756ed5c..11ffee7 100644
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/ide/core.c | 30 +++---
hw/ide/internal.h |3 ++-
hw/ide/isa.c |4 +---
hw/ide/piix.c |7 ---
I've been doing some experimentation with the QEMU guest agent and have
noticed that when nothing is connected on the host side of the virtio
serial channel, the guest agent just spins in a pool/sleep(100ms) loop.
I know you'd ordinarily expect some mgmt app in the host to be listening
to the
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/pc.c | 16 +---
1 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index 203627d..ded4758 100644
--- a/hw/pc.c
From: Peter Maydell peter.mayd...@linaro.org
Clean up the initialisation of the realview_mpcore device to avoid
using sysbus_init_mmio_cb2(): we can pass through the MemoryRegion
of the private arm11mpcore_priv device directly now.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Preprocessor directives cannot be used in STEXI/ETEXI sections since
they are not passed through the preprocessor. The spicevmc chardev
option help currently uses #if, which is included verbatim in the man
page output.
Fix this by simply stating that spicevmc chardevs are available only in
From: Richard Henderson r...@twiddle.net
The only user of ISADevice.ioports is isabus_get_fw_dev_path, and it
only looks at the first entry of the array. Which suggests that this
entire array+sort operation can be replaced by a simple minimum.
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/isa-bus.c | 17 +
hw/isa.h | 31 ++-
2 files changed, 47 insertions(+), 1 deletions(-)
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index
From: Alexander Graf ag...@suse.de
Commit 23c5e4ca (convert to memory API) broke the VIA Cuda emulation layer
by not registering the IO structs.
This patch registers them properly and thus makes -M g3beige and -M mac99
work again.
Signed-off-by: Alexander Graf ag...@suse.de
Signed-off-by: Avi
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