On 07/10/2013 08:49:35 AM, Richard Henderson wrote:
On 07/09/2013 10:43 AM, Rob Landley wrote:
Do you have a kernel .config that boots on this board? I'd really
like to try
this out myself...
I haven't worked on this in quite some time. But I've located two
branches
that look like they
Il 13/07/2013 17:22, Anthony Liguori ha scritto:
1) MMIO request goes to sPAPR PIO area, the vCPU was in BE mode but by
the time the handler is called, the value is in host byte order.
2) sPAPR (incorrectly) byte swaps by marking the region as little
endian (data is now garbage)
3) The
Il 09/07/2013 03:01, Richard Henderson ha scritto:
Honor the implementation maximum access size, and at least check
the minimum access size.
Signed-off-by: Richard Henderson r...@twiddle.net
---
exec.c | 68
++
1 file
Add support for error containment when a VFIO device assigned to a KVM
guest encounters an error. This is for PCIe devices/drivers that support AER
functionality. When the host OS is notified of an error in a device either
through the firmware first approach or through an interrupt handled by the
On 13 July 2013 23:35, Ed Maste ema...@freebsd.org wrote:
I'm not sure that anonymous union support is universal across
all compilers used to build QEMU though - do you know?
A quick grep shows we already use anonymous unions in
a few places, so it must be OK.
-- PMM
On Sun, Jul 14, 2013 at 1:57 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 14/07/2013 04:53, Liu Ping Fan ha scritto:
Refcnt's atomic inc/dec ops are frequent and its idiom need no seq_cst
order. So to get better performance, it worth to adopt _relaxed
other than _seq_cst memory model on
Hi Peter,
On Sat, Jul 13, 2013 at 6:37 AM, Peter Maydell peter.mayd...@linaro.org wrote:
Make the VEDBoardInfo struct extend arm_boot_info; this will
allow us to get at the VEDBoardInfo information inside callbacks
from arm/boot code.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
On Fri, Jul 12, 2013 at 04:17:28PM +0200, Laszlo Ersek wrote:
On 07/10/13 15:51, Michael S. Tsirkin wrote:
This add a dynamic bios linker/loader.
s/add/adds/
This will be used by acpi table generation
code to:
- load each table in the appropriate memory egment
On 14 July 2013 12:36, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
Hi Peter,
On Sat, Jul 13, 2013 at 6:37 AM, Peter Maydell peter.mayd...@linaro.org
wrote:
Make the VEDBoardInfo struct extend arm_boot_info; this will
allow us to get at the VEDBoardInfo information inside callbacks
Paolo Bonzini pbonz...@redhat.com writes:
Il 13/07/2013 17:22, Anthony Liguori ha scritto:
1) MMIO request goes to sPAPR PIO area, the vCPU was in BE mode but by
the time the handler is called, the value is in host byte order.
2) sPAPR (incorrectly) byte swaps by marking the region as
On 07/13/2013 06:03 PM, David Gibson wrote:
On Fri, Jul 12, 2013 at 05:37:19PM +1000, Alexey Kardashevskiy wrote:
sPAPR PHB emulates IO ports on PCI via a special memory region which
routes all reads/writes further via cpu_in*/cpu_out* which are eventually
processed by MemoryRegionOps
On 14 July 2013 14:05, Anthony Liguori anth...@codemonkey.ws wrote:
Also, what devices exactly would have a non-native byte order?!? I'm
confused...
MMIO/PIO requests don't have a byte order. It's literally 64 or 32 data
pins that are numbered D0..D31 whereas D0 is the LSB. It doesn't
On Sun, Jul 14, 2013 at 9:58 AM, Peter Maydell peter.mayd...@linaro.org wrote:
On 14 July 2013 14:05, Anthony Liguori anth...@codemonkey.ws wrote:
Also, what devices exactly would have a non-native byte order?!? I'm
confused...
MMIO/PIO requests don't have a byte order. It's literally 64 or
On 14 July 2013 16:18, Anthony Liguori anth...@codemonkey.ws wrote:
On Sun, Jul 14, 2013 at 9:58 AM, Peter Maydell peter.mayd...@linaro.org
wrote:
Devices themselves do have a byte order, though, right? Specifically,
if you do a 32 bit read of address 0 on a device and an 8 bit read,
It
On Sun, Jul 07, 2013 at 06:42:35PM +0300, Michael S. Tsirkin wrote:
Add ability for a ROM file to point to
it's image in memory. When file is in memory,
add utility that can patch it, storing
pointers to one file within another file.
Thanks. See my comments below.
[...]
--- /dev/null
+++
On Sun, Jul 07, 2013 at 06:42:43PM +0300, Michael S. Tsirkin wrote:
Load files in /etc/acpi/, link them using
a linker script and use for acpi tables, including the RSDP.
Presense of RSDP in this directory completely disables
generating and loading legacy acpi tables.
Signed-off-by: Michael
Il 08/07/2013 21:02, Eric Blake ha scritto:
On 07/05/2013 12:41 PM, Eduardo Habkost wrote:
On Thu, Jul 04, 2013 at 05:53:08PM +0800, Wanlong Gao wrote:
From: Bandan Das b...@redhat.com
This allows us to use the cpus property multiple times
to specify multiple cpu (ranges) to the -numa option
Il 08/07/2013 11:48, Andreas Färber ha scritto:
- hot-unplug patches not included, as suggested by Vasilis, since
hot-unplug has some more complications with refcounting memory regions.
This should hopefully be addressed with yesterday's merge of Paolo's
MemoryRegion refactoring.
Not
Il 12/07/2013 04:39, Hu Tao ha scritto:
without necessity to specify to be hot-plugged DIMMs at startup, hot-plug
could become more flexible since arbitrarily sized DIMMs with required NUMA
mapping could be specified during hot-plug time, for example:
device_add
On Fri, 2013-07-12 at 14:38 -0600, Alex Williamson wrote:
The Call for Proposals for the 2013 Linux Plumbers Virtualization
Microconference is now open. This uconf is being held as part of Linux
Plumbers Conference in New Orleans, Louisiana, USA September 18-20th and
is co-located with
The only non-alpha patch in the list has now been reviewed.
Please pull.
r~
The following changes since commit c3cb8e77804313e1be99b5f28a34a346736707a5:
ioport: remove LITTLE_ENDIAN mark for portio (2013-07-12 14:37:47 -0500)
are available in the git repository at:
Advancements in the ioport subsystem mean that we need no longer
thunk memory-mapped i/o through the system-io address space.
Signed-off-by: Richard Henderson r...@twiddle.net
---
hw/alpha/alpha_sys.h | 1 -
hw/alpha/pci.c | 44
The memory and i/o core now support passing 64-bit accesses along
from the guest, so we no longer need to emulate them.
Signed-off-by: Richard Henderson r...@twiddle.net
---
hw/alpha/typhoon.c | 53 -
1 file changed, 12 insertions(+), 41
Not really correct, but we don't implement all of the random devices
that the kernel looks for. This is good enough to keep us booting.
Signed-off-by: Richard Henderson r...@twiddle.net
---
hw/alpha/alpha_sys.h | 1 +
hw/alpha/pci.c | 26 ++
hw/alpha/typhoon.c |
The 1980 epoch is used by the ARC PALcode for NT. But we're emulating
a system using the SRM PALcode. Using the proper epoch results in less
confusion in the guest userland.
Signed-off-by: Richard Henderson r...@twiddle.net
---
hw/alpha/dp264.c | 4 +++-
1 file changed, 3 insertions(+), 1
Honor the implementation maximum access size, and at least check
the minimum access size.
Reviewed-by: Paolo Bonzini pbonz...@redhat.com
Signed-off-by: Richard Henderson r...@twiddle.net
---
exec.c | 68 ++
1 file changed, 56
Hi,
On Sat, Jul 13, 2013 at 6:37 AM, Peter Maydell peter.mayd...@linaro.org wrote:
Add some virtio-mmio transports to the vexpress board model,
together with a modify_dtb hook which adds them to the device
tree so that the kernel will probe for them. We put them
in a reserved area of the
Hi Peter,
On Sat, Jul 13, 2013 at 6:36 AM, Peter Maydell peter.mayd...@linaro.org wrote:
We already have a qemu_devtree_setprop_cells() which sets a dtb
property to an array of cells whose values are specified by varargs.
However for the fairly common case of setting a property to a list
of
On 07/13/2013 11:05 PM, Rob Landley wrote:
The -1 branch looks newer, but the -2 branch contains more code specific to
qemu. Both are over 2 years old, so I'm not sure what I was going for...
There are now -3 and -4 branches...
Wow, -4 is current with upstream I think? Cool, I'll try
On Sat, Jul 06, 2013 at 04:52:57PM +0800, Saptarshi Sen wrote:
Is it possible from qemu userspace to identify what type of file access
( DIRECT or SYNC or ASYNC )the guest is performing on its files also along
with their file-names if possible.
I tried to trace bdrv events but I am not
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
include/qom/object.h | 2 +-
qom/object.c | 15 +--
2 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/include/qom/object.h b/include/qom/object.h
index 2e165fb..8426dd1 100644
--- a/include/qom/object.h
Qref is similar to kref. It hides the refcnt detail and provides
a common interface. And this patch is based on the idiom of refcnt,
and adopts some optimization about memory model, which finally
falls back on gcc implementation.
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
On Thu, Jul 11, 2013 at 8:36 PM, Andreas Färber afaer...@suse.de wrote:
Am 11.07.2013 12:31, schrieb Michael S. Tsirkin:
On Thu, Jul 11, 2013 at 11:47:59AM +0200, Igor Mammedov wrote:
On Thu, 11 Jul 2013 11:47:16 +1000
peter.crosthwa...@xilinx.com wrote:
From: Peter Crosthwaite
As it looks like all portio users have migrated to new portio api,
the workaround with memory access to io ports routing is no more
needed.
This also fixes a bug with byte swapping as the io region was marked
as little endian while it should not do any swapping at all.
Signed-off-by: Alexey
Ping!
On Wed, Jul 10, 2013 at 5:38 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 10 July 2013 05:23, peter.crosthwa...@xilinx.com wrote:
From: Nathan Rossi nathan.ro...@xilinx.com
Added Vector Base Address remapping on ARM v7.
This is only present on CPUs with TrustZone. On the
On Mon, Jul 08, 2013 at 07:07:47AM +0200, Stefan Weil wrote:
Currently many buildbots show an exception:
http://buildbot.b1-systems.de/qemu/builders/default_x86_64_out_of_tree/builds/857/steps/git/logs/err.html
No space left on device:
On Mon, Jul 08, 2013 at 11:15:12PM -0500, Yaodong Yang wrote:
I have a question about the qemu block-subsytem. When a user in guest os
perform an io operation, how this io request performed in the qemu. Where
is the start point in qemu code to serve this request.
QEMU emulates a number of
Hi!
I have 2 command lines which I believe should work the same way but they do
not. I run qemu and do dhclient ; ifconfig in the guest. Run #1 assigns
10.0.2.15 and 10.0.2.16 (this is what I expected); runs #2/#3 assign
10.0.2.15 to both emulated interfaces in the guest.
Is there any up-to-date
Hi Andreas, Anthony,
A while ago, TYPE_CPU was refactored to by a child of TYPE_DEVICE. As
something of a hangover though, CPU has a separate reset fn to device.
This means
device_reset(DEVICE(my_cpu));
doesn't actually work as a reset. Should we fix this by getting rif of
cpu_reset and just
On Mon, Jul 08, 2013 at 08:33:55AM +0300, Michael S. Tsirkin wrote:
I noticed two things with buildbot:
http://buildbot.b1-systems.de/qemu/builders/pci_x86_64_debian_6_0
1. up to jun 23 it keept rebuilding same hash - resources could be saved
by not rebuilding if hash is unchanged
2. no
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
This series enables QOM super class access and demostrates some usages.
Replaces the save-override-call via FooClass technique, to reduce
some of the boiler plate in recently fully QOMified devices.
Applied the change to ARM CPU, MB CPU and
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Since commit aca59af612840772f18598363b65a25bf02bb569 QOM
automatically inherits class and instance size from the parent
class. No need to redefine as the same value as the parent.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
ARMCPUClass is only needed for parent-class abstract function access.
Just use parent classes for reset and realize access and remove
ARMCPUClass completely.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
MicroblazeCPUClass is only needed for parent-class abstract function
access. Just use parent classes for reset and realize access and remove
MicroblazeCPUClass completely.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
[KVM]PITClass is only needed for parent-class realize function access.
Just use parent classes for realize access and remove [KVM]PITClass
completely.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/i386/kvm/i8254.c | 19
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
The ARM A9 MPCore has a timer that is global to all CPUs in the mpcore.
The timer is shared but each CPU has a private independent comparator
and interrupt.
Based on version contributed by Francois LEGAL.
Signed-off-by: François LEGAL
From: François LEGAL de...@thom.fr.eu.org
Add the global timer to A9 MPCore.
Signed-off-by: François LEGAL de...@thom.fr.eu.org
[PC Changes:
* new commit message
* split off original version as a separate patch
]
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
This will
On 07/15/2013 05:42 AM, Stefan Hajnoczi wrote:
Christian: Is the buildmaster running low on disk space?
No. It's running low on inodes ;)
But at the moment everything is looking good, the bots are up and running.
Think we should clean up the registered build slaves. Here's a list of
offline
Hi Gleb and Paolo,
What is the status of this patch since the relevant patch for KVM is
accepted? These two patches must cooperate to fix the bug.
Arthur
On Sun, Jul 7, 2013 at 11:13 PM, Arthur Chunqi Li yzt...@gmail.com wrote:
The recent KVM patch adds IA32_FEATURE_CONTROL support. QEMU needs
On Mon, Jul 15, 2013 at 01:44:01PM +0800, Arthur Chunqi Li wrote:
Hi Gleb and Paolo,
What is the status of this patch since the relevant patch for KVM is
accepted? These two patches must cooperate to fix the bug.
Need some reviews from migration and machine type experts. Copying Juan
and
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