On 15.08.2013, at 07:21, Alexander Graf wrote:
Am 15.08.2013 um 05:35 schrieb Alexey Kardashevskiy a...@ozlabs.ru:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions,
On 08/13/2013 08:07 AM, Alex Williamson wrote:
+static void vfio_listener_region_add(MemoryListener *listener,
+ MemoryRegionSection *section)
+{
+VFIOContainer *container = container_of(listener, VFIOContainer,
+
On 15.08.2013, at 07:44, Alexey Kardashevskiy wrote:
On 08/15/2013 03:21 PM, Alexander Graf wrote:
Am 15.08.2013 um 05:35 schrieb Alexey Kardashevskiy a...@ozlabs.ru:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is
于 2013-5-6 15:53, Paolo Bonzini 写道:
Il 03/05/2013 18:03, Michael Roth ha scritto:
This introduces a GlibQContext wrapper around the main GMainContext
event loop, and associates iohandlers with it via a QSource (which
GlibQContext creates a GSource from so that it can be driven via
GLib. A
On 15.08.2013, at 07:54, Benjamin Herrenschmidt wrote:
On Thu, 2013-08-15 at 07:21 +0200, Alexander Graf wrote:
Am 15.08.2013 um 05:35 schrieb Alexey Kardashevskiy a...@ozlabs.ru:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits.
On Thu, 2013-08-15 at 08:10 +0200, Alexander Graf wrote:
So you're saying it's good to remove a well established feature on 5%
of the supported CPUs, leave the others inconsistent with the change
and then declare the whole thing an improvement?
WTF are you talking about ?
To need an exact
On Thu, 2013-08-15 at 08:03 +0200, Alexander Graf wrote:
How does the user select that he wants a v2.3 p7 cpu with this
patch?
Why would he want that? The behaviour would not change because of
the
version - all definitions use the same POWERPC_FAMILY(POWER7) and
PVR is
not
On 15.08.2013, at 08:28, Benjamin Herrenschmidt wrote:
On Thu, 2013-08-15 at 08:10 +0200, Alexander Graf wrote:
So you're saying it's good to remove a well established feature on 5%
of the supported CPUs, leave the others inconsistent with the change
and then declare the whole thing an
On 15.08.2013, at 08:30, Benjamin Herrenschmidt wrote:
On Thu, 2013-08-15 at 08:03 +0200, Alexander Graf wrote:
How does the user select that he wants a v2.3 p7 cpu with this
patch?
Why would he want that? The behaviour would not change because of
the
version - all definitions use the
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU list. Also, new CPU versions of already supported
CPU won't
On 15.08.2013, at 08:43, Alexey Kardashevskiy wrote:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU
This is (very likely) related to this /old/ bug:
http://lists.gnu.org/archive/html/qemu-devel/2013-04/msg02521.html
Could you try the patch at http://lists.gnu.org/archive/html/qemu-
devel/2013-05/msg00248.html ?
--
You received this bug notification because you are a member of qemu-
devel-ml,
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU list. Also, new CPU versions of already supported
CPU won't
On Tue, 07/30 14:53, Stefan Hajnoczi wrote:
On Tue, Jul 30, 2013 at 03:17:47PM +0800, Fam Zheng wrote:
for (sector_num = 0; sector_num end; sector_num += n) {
-uint64_t delay_ns = 0;
-bool copy;
-wait:
-/* Note that even when no rate limit is applied we
On Thu, Aug 15, 2013 at 10:26:36AM +0800, Wenchao Xia wrote:
于 2013-8-14 15:53, Stefan Hajnoczi 写道:
On Wed, Aug 14, 2013 at 3:54 AM, Wenchao Xia xiaw...@linux.vnet.ibm.com
wrote:
于 2013-8-13 16:21, Stefan Hajnoczi 写道:
On Tue, Aug 13, 2013 at 4:53 AM, Wenchao Xia
于 2013-8-14 23:32, Kevin Wolf 写道:
Am 14.08.2013 um 16:26 hat Kaveh Razavi geschrieben:
On 08/14/2013 03:50 PM, Alex Bligh wrote:
Assuming the cache quota is not exhausted, how do you know how that
a VM has finished 'creating' the cache? At any point it might
read a bit more from the backing
On 15.08.2013, at 09:45, Alexey Kardashevskiy wrote:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU
On Thu, Aug 15, 2013 at 08:05:11AM +0800, liu ping fan wrote:
On Mon, Aug 12, 2013 at 8:49 PM, Stefan Hajnoczi stefa...@redhat.com wrote:
@@ -376,13 +411,16 @@ bool timerlist_run_timers(QEMUTimerList *timer_list)
current_time = qemu_clock_get_ns(timer_list-clock-type);
for(;;) {
于 2013-8-15 15:49, Stefan Hajnoczi 写道:
On Thu, Aug 15, 2013 at 10:26:36AM +0800, Wenchao Xia wrote:
于 2013-8-14 15:53, Stefan Hajnoczi 写道:
On Wed, Aug 14, 2013 at 3:54 AM, Wenchao Xia xiaw...@linux.vnet.ibm.com wrote:
于 2013-8-13 16:21, Stefan Hajnoczi 写道:
On Tue, Aug 13, 2013 at 4:53 AM,
On 08/15/2013 05:55 PM, Alexander Graf wrote:
On 15.08.2013, at 09:45, Alexey Kardashevskiy wrote:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to
On Wed, Aug 14, 2013 at 05:32:16PM +0200, Kevin Wolf wrote:
Am 14.08.2013 um 16:26 hat Kaveh Razavi geschrieben:
On 08/14/2013 03:50 PM, Alex Bligh wrote:
Assuming the cache quota is not exhausted, how do you know how that
a VM has finished 'creating' the cache? At any point it might
This patch eliminates limitation of committing the active device.
bdrv_drop_intermediate is reimplemented to take pointers to
(BlockDriverState *), so it can modify the caller's local pointers to
preserve their semantics, while updating active BDS in-place by
bdrv_swap active and base: we need
Previously live commit of active block device is not supported, this series
implements it and updates corresponding qemu-iotests cases.
Please see commit messages for implementation details.
v3: [addressing Stefan's comments]
- Sleep in dirty map setup loop.
- Handle error of
Factor out commit test common logic into super class, and update test
of committing the active image.
Signed-off-by: Fam Zheng f...@redhat.com
---
tests/qemu-iotests/040 | 73 +-
1 file changed, 31 insertions(+), 42 deletions(-)
diff --git
On Thu, Aug 15, 2013 at 4:01 PM, Stefan Hajnoczi stefa...@gmail.com wrote:
On Thu, Aug 15, 2013 at 08:05:11AM +0800, liu ping fan wrote:
On Mon, Aug 12, 2013 at 8:49 PM, Stefan Hajnoczi stefa...@redhat.com wrote:
@@ -376,13 +411,16 @@ bool timerlist_run_timers(QEMUTimerList *timer_list)
On Thu, Aug 15, 2013 at 4:22 PM, liu ping fan qemul...@gmail.com wrote:
On Thu, Aug 15, 2013 at 4:01 PM, Stefan Hajnoczi stefa...@gmail.com wrote:
On Thu, Aug 15, 2013 at 08:05:11AM +0800, liu ping fan wrote:
On Mon, Aug 12, 2013 at 8:49 PM, Stefan Hajnoczi stefa...@redhat.com
wrote:
@@
On Wed, Aug 14, 2013 at 04:20:27PM +0200, Kaveh Razavi wrote:
Hi,
On 08/14/2013 11:29 AM, Stefan Hajnoczi wrote:
100 MB is small enough for RAM. Did you try enabling the host kernel
page cache for the backing file? That way all guests running on this
host share a single RAM-cached
On 15 Aug 2013, at 09:22, liu ping fan wrote:
How about new_list for vcpu to add timer, an before walking, splice
the new_list to timer_list?
If I understand you right, you would have to be careful
any timer routine modified itself or (less likely) any
other timer, as that timer would no
On 15.08.2013, at 10:06, Alexey Kardashevskiy wrote:
On 08/15/2013 05:55 PM, Alexander Graf wrote:
On 15.08.2013, at 09:45, Alexey Kardashevskiy wrote:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant
hi,
please, can anyone recommend me a distribution that offers a barebone linux
kernel.
minimum that I need on that image are:
_ the kernel
_ the compiler and development infrastructure to build it
regards,
dacian
Am 15.08.2013 10:45, schrieb Alexander Graf:
On 15.08.2013, at 10:06, Alexey Kardashevskiy wrote:
On 08/15/2013 05:55 PM, Alexander Graf wrote:
On 15.08.2013, at 09:45, Alexey Kardashevskiy wrote:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in
On 15.08.2013, at 12:52, Andreas Färber wrote:
Am 15.08.2013 10:45, schrieb Alexander Graf:
On 15.08.2013, at 10:06, Alexey Kardashevskiy wrote:
On 08/15/2013 05:55 PM, Alexander Graf wrote:
On 15.08.2013, at 09:45, Alexey Kardashevskiy wrote:
IBM POWERPC processors encode PVR as a
Bit extraction for the FP BF and L field of the MTFSFI and MTFSF
instructions is wrong and doesn't match the reference manual (which
explain the bit number in big endian format). It has been broken in
commit 7d08d85645def18eac2a9d672c1868a35e0bcf79.
This patch fixes this, which in turn fixes the
On 15.08.2013, at 13:32, Aurelien Jarno wrote:
Bit extraction for the FP BF and L field of the MTFSFI and MTFSF
instructions is wrong and doesn't match the reference manual (which
explain the bit number in big endian format). It has been broken in
commit
Am 15.08.2013 13:03, schrieb Alexander Graf:
On 15.08.2013, at 12:52, Andreas Färber wrote:
Am 15.08.2013 10:45, schrieb Alexander Graf:
Yes, I think it makes sense to keep the full PVR around when we want to be
specific. What I'm referring to is class specific logic that can assemble
Hi,
Am 15.08.2013 10:57, schrieb Herbei Dacian:
please, can anyone recommend me a distribution that offers a barebone
linux kernel.
minimum that I need on that image are:
_ the kernel
_ the compiler and development infrastructure to build it
Aboriginal Linux.
Andreas
--
SUSE LINUX
On 15.08.2013, at 13:48, Andreas Färber wrote:
Am 15.08.2013 13:03, schrieb Alexander Graf:
On 15.08.2013, at 12:52, Andreas Färber wrote:
Am 15.08.2013 10:45, schrieb Alexander Graf:
Yes, I think it makes sense to keep the full PVR around when we want to be
specific. What I'm
On Thu, Aug 15, 2013 at 04:24:57PM +0800, liu ping fan wrote:
On Thu, Aug 15, 2013 at 4:22 PM, liu ping fan qemul...@gmail.com wrote:
On Thu, Aug 15, 2013 at 4:01 PM, Stefan Hajnoczi stefa...@gmail.com wrote:
On Thu, Aug 15, 2013 at 08:05:11AM +0800, liu ping fan wrote:
On Mon, Aug 12, 2013
On Thu, Aug 15, 2013 at 09:57:09AM +0100, Herbei Dacian wrote:
please, can anyone recommend me a distribution that offers a barebone linux
kernel.
minimum that I need on that image are:
_ the kernel
_ the compiler and development infrastructure to build it
If you want something small and
On Sat, Aug 10, 2013 at 12:21:27PM +0100, Alex Bligh wrote:
Currently we use a separate timer list group (main_loop_tlg)
for the main loop. This patch replaces this with a dummy AioContext
used just for timers in the main loop.
Things get interesting when we make main loop
On 08/15/2013 10:32 AM, Stefan Hajnoczi wrote:
I don't buy the argument about the page cache being evicted at any time:
At the scale where caching is important, provisioning a measily 100 MB
of RAM per guest should not be a challenge.
cgroups can be used to isolate page cache between VMs if
On Sun, Aug 11, 2013 at 05:43:13PM +0100, Alex Bligh wrote:
@@ -314,7 +314,18 @@ void qemu_clock_warp(QEMUClock *clock)
}
vm_clock_warp_start = qemu_get_clock_ns(rt_clock);
-deadline = qemu_clock_deadline(vm_clock);
+/* We want to use the earliest deadline from ALL
On 15 Aug 2013, at 13:30, Stefan Hajnoczi wrote:
On Sun, Aug 11, 2013 at 05:43:13PM +0100, Alex Bligh wrote:
@@ -314,7 +314,18 @@ void qemu_clock_warp(QEMUClock *clock)
}
vm_clock_warp_start = qemu_get_clock_ns(rt_clock);
-deadline = qemu_clock_deadline(vm_clock);
+/* We
On 15 Aug 2013, at 13:16, Stefan Hajnoczi wrote:
Things get interesting when we make main loop qemu_set_fd_handler() and
timers just use AioContext.
Basically, we are distilling out the main-loop.c stuff which is a
low-level glib-style event loop from the AioContext fd handlers, timers,
On Sun, Aug 11, 2013 at 05:42:54PM +0100, Alex Bligh wrote:
[ This patch set is available from git at:
https://github.com/abligh/qemu/tree/aio-timers10
As autogenerated patch 30 of the series is too large for the mailing list. ]
This patch series adds support for timers attached to an
Hi all,
I'm struggling with the QEMU VNC on qemu-kvm-1.2.0 a bit, the following two
things are not working properly:
1) Shift key pressed and hold for several seconds causes multiple shift key
press + release events = I would expect getting one press, one or more hold and
one release event
On 13.08.2013, at 08:45, Felix Deichmann wrote:
Hi,
I tried to install NetBSD/prep 6.1 in qemu-ppc (-M prep), but qemu
crashes during installation with floating point exception in a
reproducible way.
qemu is version 1.5.2-1 from Arch Linux (sorry, didn't have the time
to build a
On 15 Aug 2013, at 13:40, Stefan Hajnoczi wrote:
This is looking pretty good. Jan, Ping Fan, and I have already worked
on top of this series. I'd like to merge it soon.
Are you ready to roll v11?
The only things I have queued for v11 are:
* Disentangle typedef struct vs struct in header
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Thu, 2013-08-15 at 08:03 +0200, Alexander Graf wrote:
How does the user select that he wants a v2.3 p7 cpu with this
patch?
Why would he want that? The behaviour would not change because of
the
version - all definitions use
Christoph Hellwig h...@lst.de writes:
On Wed, Jul 31, 2013 at 08:19:51AM +0200, Paolo Bonzini wrote:
Most of the block layer is under the BSD license, thus it is reasonable
to license block/raw.c the same way. CCed people should ACK by replying
with a Signed-off-by line.
The coded was
In the end I went for debian cause it is widely used.
So I'm using the following command to install linux:
qemu-system-arm -m 1024 -hda arm.img -cdrom debian-7.1.0-armel-CD-1.iso -boot d
And I get this error:
Kernel image must be specified
In the documentation is mentioned that i don't need a
On 15 August 2013 14:22, Herbei Dacian dacian_her...@yahoo.fr wrote:
In the end I went for debian cause it is widely used.
So I'm using the following command to install linux:
qemu-system-arm -m 1024 -hda arm.img -cdrom debian-7.1.0-armel-CD-1.iso
-boot d
This command line is totally
On 15.08.2013, at 15:12, Anthony Liguori wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Thu, 2013-08-15 at 08:03 +0200, Alexander Graf wrote:
How does the user select that he wants a v2.3 p7 cpu with this
patch?
Why would he want that? The behaviour would not change
Hi,
# qemu-system-ppc -nographic -M prep -m 128M -hda hda.qcow2 -cdrom
NetBSD-6.1-prep.iso -serial ... -kernel sysinst_com0.fs
There seems to be a connection between the amount of RAM chosen
and the point where the crash happens. With 128M, qemu will crash
when the installer extracts
OK but which command should I use if that is broken and where I can find some
documentation that is actually up to date?
From: Peter Maydell peter.mayd...@linaro.org
To: Herbei Dacian dacian_her...@yahoo.fr
Cc: QEmu Devel qemu-devel@nongnu.org
Sent:
On 15 August 2013 14:46, Herbei Dacian dacian_her...@yahoo.fr wrote:
OK but which command should I use if that is broken and where I can find
some documentation that is actually up to date?
You need to start by finding out which of the boards QEMU
models your distribution actually supports, and
On 08/15/2013 09:48 PM, Andreas Färber wrote:
Am 15.08.2013 13:03, schrieb Alexander Graf:
On 15.08.2013, at 12:52, Andreas Färber wrote:
Am 15.08.2013 10:45, schrieb Alexander Graf:
Yes, I think it makes sense to keep the full PVR around when we want to be
specific. What I'm referring to
yes but which binary do I use to call to run an emulated arm image?
is there an actual binary that can emulate an existing arm board, anyboard?
qemu?
if not which is the emulator that works with arm?
If not where is the project that I can tweak to build such a binary.
I can search for the
On 15.08.2013, at 15:39, Gerd Hoffmann wrote:
Hi,
# qemu-system-ppc -nographic -M prep -m 128M -hda hda.qcow2 -cdrom
NetBSD-6.1-prep.iso -serial ... -kernel sysinst_com0.fs
There seems to be a connection between the amount of RAM chosen
and the point where the crash happens. With
On 15 August 2013 15:01, Herbei Dacian dacian_her...@yahoo.fr wrote:
yes but which binary do I use to call to run an emulated arm image?
qemu-system-arm.
is there an actual binary that can emulate an existing arm board, anyboard?
qemu-system-arm -M help lists the boards we support.
but you said that qemu-system-arm is not maintained and it doesn't work.
The link below contains only links to kernel images that don't work.
Anyway I'll figure it somehow cause this doesn't help me.
From: Peter Maydell peter.mayd...@linaro.org
To: Herbei
Hi
I am seeing a regression with 1.5.0 release where the following program
#include stdio.h
#include math.h
int main(int argc, char * argv[])
{
double f = 1234.67;
printf(floor(%f) = %f\n, f, floor(f));
return 0;
}
when compiled without any -O options
On Aug 15, 2013, at 4:32 AM, Aurelien Jarno aurel...@aurel32.net wrote:
Bit extraction for the FP BF and L field of the MTFSFI and MTFSF
instructions is wrong and doesn't match the reference manual (which
explain the bit number in big endian format). It has been broken in
commit
On 15 August 2013 15:18, Herbei Dacian dacian_her...@yahoo.fr wrote:
but you said that qemu-system-arm is not maintained and it doesn't work.
No, I said that the arguments you were giving it were requesting a
model of an obsolete board, and you should ask it to emulate a
different board.
-- PMM
On 08/15/2013 06:45 PM, Alexander Graf wrote:
On 15.08.2013, at 10:06, Alexey Kardashevskiy wrote:
On 08/15/2013 05:55 PM, Alexander Graf wrote:
On 15.08.2013, at 09:45, Alexey Kardashevskiy wrote:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in
Am 15.08.2013 15:55, schrieb Alexey Kardashevskiy:
On 08/15/2013 09:48 PM, Andreas Färber wrote:
Am 15.08.2013 13:03, schrieb Alexander Graf:
On 15.08.2013, at 12:52, Andreas Färber wrote:
Am 15.08.2013 10:45, schrieb Alexander Graf:
Yes, I think it makes sense to keep the full PVR around
Hi Jacques,
On 15.08.2013, at 16:42, Jacques Mony wrote:
Hello,
After going through the archives, I read an interesting thread regarding
unimplemented instruction set from PowerISA 2.06. The specific instruction
that seems to be called by AIX is stxvd2x, from VSX Instruction Set (new in
Am 15.08.2013 15:12, schrieb Anthony Liguori:
Everyone is talking past each other and no one is addressing the real
problem. There are two distinct issues here:
1) We have two ABIs that cannot be changed unless there's a very good
reason to. Alexey's original patch breaks both. The
On 15.08.2013, at 16:43, Alexey Kardashevskiy wrote:
On 08/15/2013 06:45 PM, Alexander Graf wrote:
On 15.08.2013, at 10:06, Alexey Kardashevskiy wrote:
On 08/15/2013 05:55 PM, Alexander Graf wrote:
On 15.08.2013, at 09:45, Alexey Kardashevskiy wrote:
IBM POWERPC processors encode
Quoting Wenchao Xia (2013-08-13 03:44:39)
于 2013-8-13 1:01, Michael Roth 写道:
Quoting Paolo Bonzini (2013-08-12 02:30:28)
1) rename AioContext to AioSource.
This is my major purpose, which declare it is not a context concept,
and GMainContext is the entity represent the thread's
From: Paolo Bonzini pbonz...@redhat.com
Reviewed-by: Mike Day ncm...@ncultra.org
---
tests/Makefile | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/tests/Makefile b/tests/Makefile
index b4a52b4..4d68d28 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -44,9
This series applies on top today's git.qemu.org/master and is online at:
https://github.com/ncultra/qemu/tree/rcu-for-1.7
Paolo Bonzini (2):
fixed tests/Makefile to correctly link rcutorture
enable TLS in build and activate test-tls in make check
configure | 63
From: Paolo Bonzini pbonz...@redhat.com
Reviewed-by: Mike Day ncm...@ncultra.org
---
configure | 63 ++
include/qemu/tls.h | 127 +
include/qom/cpu.h | 2 +-
tests/Makefile | 2 +-
tests/test-tls.c |
On 15.08.2013, at 17:11, Andreas Färber wrote:
Am 15.08.2013 15:12, schrieb Anthony Liguori:
Everyone is talking past each other and no one is addressing the real
problem. There are two distinct issues here:
1) We have two ABIs that cannot be changed unless there's a very good
reason
On 15.08.2013, at 16:47, Andreas Färber wrote:
Am 15.08.2013 15:55, schrieb Alexey Kardashevskiy:
On 08/15/2013 09:48 PM, Andreas Färber wrote:
Am 15.08.2013 13:03, schrieb Alexander Graf:
On 15.08.2013, at 12:52, Andreas Färber wrote:
Am 15.08.2013 10:45, schrieb Alexander Graf:
Am 15.08.2013 17:29, schrieb Alexander Graf:
On 15.08.2013, at 16:47, Andreas Färber wrote:
There is nothing wrong with finding a mask or wildcard solution to that
problem, I already indicated so on the original POWER+ patch. The point
of the whole discussion is how to get there in the
Am 15.08.2013 17:30, schrieb Alexander Graf:
On 15.08.2013, at 17:11, Andreas Färber wrote:
Am 15.08.2013 15:12, schrieb Anthony Liguori:
Everyone is talking past each other and no one is addressing the real
problem. There are two distinct issues here:
1) We have two ABIs that cannot be
On 15.08.2013, at 17:43, Andreas Färber wrote:
Am 15.08.2013 17:29, schrieb Alexander Graf:
On 15.08.2013, at 16:47, Andreas Färber wrote:
There is nothing wrong with finding a mask or wildcard solution to that
problem, I already indicated so on the original POWER+ patch. The point
of
On Mon, Aug 05, 2013 at 08:07:18AM -1000, Richard Henderson wrote:
No point in splitting the write into 32-bit pieces.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/i386/tcg-target.c | 3 +--
tcg/tcg.c | 6 ++
2 files changed, 7 insertions(+), 2 deletions(-)
On Mon, Aug 05, 2013 at 08:07:19AM -1000, Richard Henderson wrote:
Use a 7 byte lea before the ultimate 10 byte movq.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/i386/tcg-target.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git
On Mon, Aug 05, 2013 at 08:07:20AM -1000, Richard Henderson wrote:
Use existing stack space for arguments; don't push/pop.
Use less ifdefs and more C ifs.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/i386/tcg-target.c | 159
+-
On Mon, Aug 05, 2013 at 08:07:22AM -1000, Richard Henderson wrote:
Avoid a loop in the tlb_fill path; the fill will either succeed or
generate an exception.
Inline the slow_ld/st function; it was a complete copy of the main
helper except for the actual cross-page unaligned code, and the
On Mon, Aug 05, 2013 at 08:07:21AM -1000, Richard Henderson wrote:
Allow the code that tcg generates to be less obtuse, passing in
the return address directly instead of computing it in the helper.
Maintain the old entrance point unchanged as an alternate entry point.
Signed-off-by:
On Mon, Aug 05, 2013 at 08:07:23AM -1000, Richard Henderson wrote:
Discontinue the jump-around-jump-to-jump scheme, trading it for a single
immediate move instruction. The two extra jumps always consume 7 bytes,
whereas the immediate move is either 5 or 7 bytes depending on where the
On MIPS ext8s and ext16s ops are implemented with a dedicated
instruction only on MIPS32R2, otherwise the same kind of implementation
than at TCG level (shift left followed by shift right) is used.
Change that by only implementing the ext8s and ext16s ops on MIPS32R2 so
that optimizations can be
Now that TCG supports enabling and disabling ops at runtime, it's
possible to detect the available host instructions at runtime, and
enable the corresponding ops accordingly.
Unfortunately it's not easy to probe for available instructions on
MIPS, the information is partially available in
Andreas Färber afaer...@suse.de writes:
Am 15.08.2013 15:12, schrieb Anthony Liguori:
Everyone is talking past each other and no one is addressing the real
problem. There are two distinct issues here:
1) We have two ABIs that cannot be changed unless there's a very good
reason to.
On 15.08.2013, at 17:48, Andreas Färber wrote:
Am 15.08.2013 17:30, schrieb Alexander Graf:
On 15.08.2013, at 17:11, Andreas Färber wrote:
Am 15.08.2013 15:12, schrieb Anthony Liguori:
Everyone is talking past each other and no one is addressing the real
problem. There are two distinct
Am 15.08.2013 17:51, schrieb Alexander Graf:
On 15.08.2013, at 17:43, Andreas Färber wrote:
Am 15.08.2013 17:29, schrieb Alexander Graf:
On 15.08.2013, at 16:47, Andreas Färber wrote:
There is nothing wrong with finding a mask or wildcard solution to that
problem, I already indicated so
Am 15.08.2013 17:58, schrieb Alexander Graf:
On 15.08.2013, at 17:48, Andreas Färber wrote:
Am 15.08.2013 17:30, schrieb Alexander Graf:
On 15.08.2013, at 17:11, Andreas Färber wrote:
Am 15.08.2013 15:12, schrieb Anthony Liguori:
Everyone is talking past each other and no one is
On 15.08.2013, at 18:08, Andreas Färber wrote:
Am 15.08.2013 17:51, schrieb Alexander Graf:
On 15.08.2013, at 17:43, Andreas Färber wrote:
Am 15.08.2013 17:29, schrieb Alexander Graf:
On 15.08.2013, at 16:47, Andreas Färber wrote:
There is nothing wrong with finding a mask or
Quoting Michael Roth (2013-08-15 10:23:20)
Quoting Wenchao Xia (2013-08-13 03:44:39)
于 2013-8-13 1:01, Michael Roth 写道:
Quoting Paolo Bonzini (2013-08-12 02:30:28)
1) rename AioContext to AioSource.
This is my major purpose, which declare it is not a context
concept,
and
On Thu, 15 Aug 2013, Aurelien Jarno wrote:
+/* Probe for MIPS32 instructions. As no subsetting is allowed
+ by the specification, it is only necessary to probe for one
+ of the instructions. */
+#ifndef use_mips32_instructions
+got_sigill = 0;
+asm volatile(.set
On 15.08.2013, at 18:22, Andreas Färber wrote:
Am 15.08.2013 17:58, schrieb Alexander Graf:
On 15.08.2013, at 17:48, Andreas Färber wrote:
Am 15.08.2013 17:30, schrieb Alexander Graf:
On 15.08.2013, at 17:11, Andreas Färber wrote:
Am 15.08.2013 15:12, schrieb Anthony Liguori:
On 13 August 2013 04:40, Guenter Roeck li...@roeck-us.net wrote:
Patch tested and working with qemu 1.5.2, using the configuration file
from the yocto project. Patch applied on top of kernel version 3.11-rc5.
OK, I tested this on PB926+PCI backplane hardware, and it is
definitely better than
On Thu, Aug 15, 2013 at 05:52:55PM +0100, Maciej W. Rozycki wrote:
On Thu, 15 Aug 2013, Aurelien Jarno wrote:
+/* Probe for MIPS32 instructions. As no subsetting is allowed
+ by the specification, it is only necessary to probe for one
+ of the instructions. */
+#ifndef
On Thu, Aug 15, 2013 at 05:45:42PM +0100, Peter Maydell wrote:
On 13 August 2013 04:40, Guenter Roeck li...@roeck-us.net wrote:
Patch tested and working with qemu 1.5.2, using the configuration file
from the yocto project. Patch applied on top of kernel version 3.11-rc5.
OK, I tested this
On Thu, 15 Aug 2013, Aurelien Jarno wrote:
The MIPS32 instructions missing from Vr5500 are the EJTAG stuff (DERET
and SDBBP), JR.HB/JALR.HB (hmm, weird -- these are actually not guaranteed
to work on all MIPS32 chips either, e.g. the 4Kc didn't support these
encodings and trapped),
I confirmed it wasn't my host, I successfully ran a test on the same
host with a 32-bit QEMU build and SLIRP works fine, for 1.6.0-rc3 as
well.
It could be my x86_64-w64-mingw32-gcc compiler version, I tested 4.8 and
4.7, maybe they're too new? Is there a specific gcc version known to
work? I can
On 15 August 2013 18:54, Guenter Roeck li...@roeck-us.net wrote:
On Thu, Aug 15, 2013 at 05:45:42PM +0100, Peter Maydell wrote:
On 13 August 2013 04:40, Guenter Roeck li...@roeck-us.net wrote:
Patch tested and working with qemu 1.5.2, using the configuration file
from the yocto project.
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