The existing quirks aim config space and MSIX BAR accesses interception.
These are not always needed, for example, on pseries machines,
config space and MSI/MSIX configuration are handled by hypervisor.
This adds a quirks property to control whether to enable quirks or not;
the property is set to
On 6/13/15 21:21, Chen Gang wrote:
+static void gen_st_add(struct DisasContext *dc,
+ uint8_t rsrc, uint8_t rsrcb, uint8_t imm8,
It needs int8_t instead of uint8_t for imm8, or it will cause memmove()
of glibc generates incorrect result with -O1/2/s optimization.
And
On 6/13/15 21:21, Chen Gang wrote:
+
+static void decode_x1(struct DisasContext *dc, tilegx_bundle_bits bundle)
+{
+unsigned int opcode = get_Opcode_X1(bundle);
+uint8_t rsrc = (uint8_t)get_SrcA_X1(bundle);
+uint8_t rdst = (uint8_t)get_Dest_X1(bundle);
+int16_t imm16 =
Despite L32E and S32E primary use is for window underflow and overflow
exception handlers they are just normal instructions, and thus need to
check for window overflow.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 6 --
1 file
On 7/19/15 17:42, Chen Gang wrote:
On 6/13/15 21:21, Chen Gang wrote:
+static void gen_st_add(struct DisasContext *dc,
+ uint8_t rsrc, uint8_t rsrcb, uint8_t imm8,
It needs int8_t instead of uint8_t for imm8, or it will cause memmove()
of glibc generates incorrect
I tested this patch series, plus 'AioContext: fix missing wakeups due
to event_notifier_test_and_clear' overnight, and there were no
failures after something like 2500 iterations. So:
Tested-by: Richard W.M. Jones rjo...@redhat.com
Rich.
--
Richard Jones, Virtualization Group, Red Hat
On 19 July 2015 at 06:40, Igor R boost.li...@gmail.com wrote:
On x86 one can get the current PGD from CR3. What's the right way to
do this on ARM?
What's a PGD ?
Page global directory
That doesn't help much -- I don't know x86 terminology and
it's not an ARM term.
But in the recent QEMU
On 2015-07-18 23:18, Aurelien Jarno wrote:
On 2015-07-18 08:58, Richard Henderson wrote:
Enforce the invariant that 32-bit quantities are zero extended
in the register. This avoids having to re-zero-extend at memory
accesses for 32-bit guests.
Signed-off-by: Richard Henderson
Hello,
There is no change in userland tools after resizing qcow2 image except
file utility.
For example when resize qcow2 image, the file utility is detectable
increased size.
However, the ls, “stat”, and “du” utility still don't know how many
change size of image is changed.
The following
Hello,
There is no change in userland tools after resizing qcow2 image except
file utility.
For example when resize qcow2 image, the file utility is detectable
increased size.
However, the ls, “stat”, and “du” utility still don't know how many
change size of image is changed.
The following
On 6/13/15 21:10, Chen Gang wrote:
+
+void cpu_loop(CPUTLGState *env)
+{
+CPUState *cs = CPU(tilegx_env_get_cpu(env));
+int trapnr;
+
+while (1) {
+cpu_exec_start(cs);
+trapnr = cpu_tilegx_exec(env);
+cpu_exec_end(cs);
+switch (trapnr) {
+
When computing the TLB address we are likely to mask out the high
32-bits by using shr + and. We can use 32-bit instructions in that
case. This saves 2 bytes per TLB access.
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
tcg/i386/tcg-target.c | 16
On 19/07/2015 00:20, Benjamin Herrenschmidt wrote:
+ * For BookE, we need in theory 8 MMU modes, which would
+ * reduce performance, so instead, we ignore msr_hv and
+ * will flush on HV context switches. We *could* improve
+ * things a bit if needed by using 4 and 5 as HV
On Sun, 2015-07-19 at 13:56 +0200, Paolo Bonzini wrote:
On 19/07/2015 00:20, Benjamin Herrenschmidt wrote:
+ * For BookE, we need in theory 8 MMU modes, which would
+ * reduce performance, so instead, we ignore msr_hv and
+ * will flush on HV context switches. We *could*
Hello,
There is no change in userland tools after resizing qcow2 image except
file utility.
For example when resize qcow2 image, the file utility is detectable
increased size.
However, the ls, “stat”, and “du” utility still don't know how many
change size of image is changed.
The following
On Wed, Jun 24, 2015 at 07:57:45AM +0200, Michael S. Tsirkin wrote:
On Wed, Jun 24, 2015 at 02:46:30PM +0900, Tetsuya Mukawa wrote:
On 2015/06/23 18:41, Michael S. Tsirkin wrote:
On Tue, Jun 23, 2015 at 05:31:06PM +0900, Tetsuya Mukawa wrote:
On 2015/06/22 17:14, Michael S. Tsirkin wrote:
On Sun, 2015-07-19 at 18:19 +1000, Alexey Kardashevskiy wrote:
The existing quirks aim config space and MSIX BAR accesses interception.
These are not always needed, for example, on pseries machines,
config space and MSI/MSIX configuration are handled by hypervisor.
This adds a quirks
Hello!
We are excited to see the GICv3 patches making progress. Thanks for putting
in the effort.
Thank you :)
I see in your message below that software emulation is not supported yet. I
was wondering if you
could
elaborate on what the issues are preventing GICv3 in TCG mode? Is it
Yes, vhost-user need a fix in qemu related to memory regions.
Is there any Plans to implement in Multi-queue for vhost-user?.
Thanks
Jana
On 17 July 2015 at 17:25, Marc-André Lureau marcandre.lur...@gmail.com
wrote:
Hi Naredula
On Mon, Jul 13, 2015 at 10:35 AM, Naredula Janardhana Reddy
On Sun, 2015-07-19 at 06:50 -0600, Alex Williamson wrote:
On Sun, 2015-07-19 at 18:19 +1000, Alexey Kardashevskiy wrote:
The existing quirks aim config space and MSIX BAR accesses interception.
These are not always needed, for example, on pseries machines,
config space and MSI/MSIX
On 19/07/2015 14:11, Benjamin Herrenschmidt wrote:
Ok, I assumed incorrectly that 8 was too much based on your changeset
comment:
At 8k per TLB (for 64-bit host or target), 8 or more modes
make the TLBs bigger than 64k, and some RISC TCG backends do
not like that. On the
On 19/07/2015 10:12, Taeha Kim wrote:
$ ./qemu/qemu-img resize 100G.qcow2 200G
Image resized.
$ ./qemu/qemu-img check 100G.qcow2
No errors were found on the image.
1638400/3276800 = 50.00% allocated, 0.00% fragmented, 0.00% compressed
clusters
Image end offset: 107390894080
You are
From: Carlos L. Torres carlos.tor...@rackspace.com
Add wrapper for strtol() function. Include unit tests.
Signed-off-by: Carlos L. Torres carlos.tor...@rackspace.com
---
include/qemu-common.h | 2 +
tests/test-cutils.c | 319 ++
util/cutils.c
From: Carlos L. Torres carlos.tor...@rackspace.com
Introduce qemu_ wrappers for strtol/strtoul/strtoll/strtoull
C functions, ensure that errno is checked, and if NULL is
passed as the endptr argument, then whole string has to be
a valid number on the given base, otherwise return appropriate
On 2015-07-19 13:56, Paolo Bonzini wrote:
On 19/07/2015 00:20, Benjamin Herrenschmidt wrote:
+ * For BookE, we need in theory 8 MMU modes, which would
+ * reduce performance, so instead, we ignore msr_hv and
+ * will flush on HV context switches. We *could* improve
+ *
Currently, we get to the slow path for any unaligned access in the
backend, because we effectively preserve the bottom address bits
below the alignment requirement when comparing with the TLB entry,
so any non-0 bit there will cause the compare to fail.
For the same number of instructions, we can
From: Carlos L. Torres carlos.tor...@rackspace.com
Add wrapper for strtoll() function. Include unit tests.
Signed-off-by: Carlos L. Torres carlos.tor...@rackspace.com
---
include/qemu-common.h | 2 +
tests/test-cutils.c | 320 ++
util/cutils.c
From: Carlos L. Torres carlos.tor...@rackspace.com
Add wrapper for strtoull() function. Include unit tests.
Signed-off-by: Carlos L. Torres carlos.tor...@rackspace.com
---
include/qemu-common.h | 2 +
tests/test-cutils.c | 323 ++
From: Carlos L. Torres carlos.tor...@rackspace.com
Add wrapper for strtoul() function. Include unit tests.
Signed-off-by: Carlos L. Torres carlos.tor...@rackspace.com
---
include/qemu-common.h | 2 +
tests/test-cutils.c | 318 ++
util/cutils.c
From: Carlos L. Torres carlos.tor...@rackspace.com
Signed-off-by: Carlos L. Torres carlos.tor...@rackspace.com
---
qmp.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/qmp.c b/qmp.c
index 403805a..aa8c084 100644
--- a/qmp.c
+++ b/qmp.c
@@ -49,14 +49,20 @@
Currently, we get to the slow path for any unaligned access in the
backend, because we effectively preserve the bottom address bits
below the alignment requirement when comparing with the TLB entry,
so any non-0 bit there will cause the compare to fail.
For the same number of instructions, we can
On Sat, 07/18 22:21, Paolo Bonzini wrote:
It is pretty rare for aio_notify to actually set the EventNotifier. It
can happen with worker threads such as thread-pool.c's, but otherwise it
should never be set thanks to the ctx-notify_me optimization. The
previous patch, unfortunately, added an
On Mon, 2015-07-20 at 01:01 +0200, Aurelien Jarno wrote:
One way to improve this would be to reduce the size of a TLB entry.
Currently we store the page address separately for read, write and
code. The information is therefore quite redundant.
We might want to have only one page address
On 7/19/15 19:31, Chen Gang wrote:
On 6/13/15 21:10, Chen Gang wrote:
+
+void cpu_loop(CPUTLGState *env)
+{
+CPUState *cs = CPU(tilegx_env_get_cpu(env));
+int trapnr;
+
+while (1) {
+cpu_exec_start(cs);
+trapnr = cpu_tilegx_exec(env);
+
On Sun, 2015-07-19 at 19:42 +0200, Paolo Bonzini wrote:
On 19/07/2015 14:11, Benjamin Herrenschmidt wrote:
Ok, I assumed incorrectly that 8 was too much based on your changeset
comment:
At 8k per TLB (for 64-bit host or target), 8 or more modes
make the TLBs bigger than 64k,
On 07/16/2015 05:52 PM, Igor Mammedov wrote:
On Thu, 16 Jul 2015 10:45:41 +0800
Zhu Guihua zhugh.f...@cn.fujitsu.com wrote:
ping...
I'll look at it once 2.4 is released.
Got it, thanks.
By the way, do you know what state of qemu socket topology ?
Regards,
Zhu
On 07/03/2015 05:38 PM,
On 07/20/2015 03:15 AM, Alex Williamson wrote:
On Sun, 2015-07-19 at 06:50 -0600, Alex Williamson wrote:
On Sun, 2015-07-19 at 18:19 +1000, Alexey Kardashevskiy wrote:
The existing quirks aim config space and MSIX BAR accesses interception.
These are not always needed, for example, on pseries
On Mon, 2015-07-20 at 11:54 +1000, Benjamin Herrenschmidt wrote:
Currently, we get to the slow path for any unaligned access in the
backend, because we effectively preserve the bottom address bits
below the alignment requirement when comparing with the TLB entry,
so any non-0 bit there will
On 19/07/2015 01:52, Carlos L. Torres wrote:
+int err;
info-qemu = g_new0(VersionTriple, 1);
-info-qemu-major = strtol(version, tmp, 10);
+err = qemu_strtol(version, tmp, 10, (info-qemu-major));
There are usually no parentheses around the argument of the operator.
+
Hi,
On Tue, 2015-07-14 at 10:13 -0400, Frediano Ziglio wrote:
Hi,
This patch rely on some change in spice-protocol which are not still
accepted. See
http://lists.freedesktop.org/archives/spice-devel/2015-June/020221.html.
What is the upstream status here? accepted
On Sun, 2015-07-19 at 01:05 +1000, David Gibson wrote:
On Fri, Jul 17, 2015 at 12:25:31PM -0600, Alex Williamson wrote:
On Fri, 2015-07-17 at 15:20 +1000, David Gibson wrote:
On Thu, Jul 16, 2015 at 08:44:59AM -0600, Alex Williamson wrote:
On Thu, 2015-07-16 at 15:11 +1000, David Gibson
On 19/07/2015 11:15, Taeha Kim wrote:
However, the ls, “stat”, and “du” utility still don't know how many
change size of image is changed.
That's not a bug. qcow2 images only need as much space as required,
plus some for the metadata. This lets you use small files, and copy
them around
Add documentation comments for various utility string functions
which we have implemented in util/cutils.c:
pstrcpy()
strpadcpy()
pstrcat()
strstart()
stristart()
qemu_strnlen()
qemu_strsep()
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
We recommend pstrcpy() c in HACKING but
From: Nils Carlson pyssl...@ludd.ltu.se
Commit 812c1057 introduced HUP detection on unix and tcp sockets prior
to a read in tcp_chr_read. This unfortunately broke CloudStack 4.2
which relied on the old behaviour where data on a socket was readable
even if a HUP was present.
A working solution is
On 17 July 2015 at 20:24, Programmingkid programmingk...@gmail.com wrote:
Is pstrcpy() ansi c? I'm having trouble finding documentation for it.
No, it's something we provide in util/cutils.c. We recommend it
in HACKING, but we don't actually document the semantics, which
is a bit unhelpful. I've
I am running Ubuntu Wily (the 20150717 daily build) can reproduce this
problem, whatever the guest is Linux or Windows, after host got resumed
from suspend, the kvm (qemu-system-x86_64) process becomes a 100% cpu
usage,
user@ubuntu-mate:~$ kvm --version
QEMU emulator version 2.3.0 (Debian
On Fri, Jul 17, 2015 at 01:56:40PM +0200, Andrew Jones wrote:
I've started playing with adding ppc support to kvm-unit-tests,
using spapr for the machine model. I wanted to link the unit test
at 0x40 to match qemu's load address, making the unit test
startup code simpler, but ended up with
On Fri, Jul 17, 2015 at 01:56:38PM +0200, Andrew Jones wrote:
I've started playing with adding ppc support to kvm-unit-tests,
using spapr for the machine model. Here are a couple patches
to spapr I've made.
For future reference, I prefer if patches intended for upstream are
sent to my external
On 20/07/2015 07:25, Paolo Bonzini wrote:
/* fill pollfds */
+i = 0;
QLIST_FOREACH(node, ctx-aio_handlers, node) {
if (!node-deleted node-pfd.events) {
add_pollfd(node);
+if (node-pfd.fd == event_notifier_get_fd(ctx-notifier)) {
+
On Sat, 07/18 22:21, Paolo Bonzini wrote:
event_notifier_test_and_clear must be called before processing events.
Otherwise, an aio_poll could eat the notification before the main
I/O thread invokes ppoll(). The main I/O thread then never wakes up.
This is an example of what could happen:
On 2015-07-20 12:50, Benjamin Herrenschmidt wrote:
Currently, we get to the slow path for any unaligned access in the
backend, because we effectively preserve the bottom address bits
below the alignment requirement when comparing with the TLB entry,
so any non-0 bit there will cause the
you may have tu run puredarwin but thats cool and okay you just have to
fake the processor and chipset enough so that darwin thinks its on a
powerpc.
which will totally rock by the way.
but yeah tutorials on every aspect of this would be super good, then you
can start making your own computers
i am here to ask tutorials on every part of emulating processors and things
of that nature.
my goal is to be able to run hackintosh...tonymacx86.com or puredarwin...
puredarwin.org on the raspberry pi and have access to the pins still.
seems like a lot but i know it can be done.
also if you
you can also go about this by writing in a super custom chipset for
virtualbox then have full access to hackintosh in virtualbox.
On Fri, Jul 17, 2015 at 06:19:40PM +0530, Bharata B Rao wrote:
pc_dimm_realize() validates the NUMA node to which memory hotplug is
being performed only in case of NUMA configuration. Include a check
to fail invalid nodes in case of non-NUMA configuration too.
Signed-off-by: Bharata B Rao
On 20/07/2015 04:27, Fam Zheng wrote:
For aio-posix, how about keeping the optimization local which doesn't need
atomic operation? (no idea for win32 :)
diff --git a/aio-posix.c b/aio-posix.c
index 5c8b266..7e98123 100644
--- a/aio-posix.c
+++ b/aio-posix.c
@@ -236,6 +236,7 @@ bool
On 20/07/2015 05:55, Fam Zheng wrote:
On Sat, 07/18 22:21, Paolo Bonzini wrote:
event_notifier_test_and_clear must be called before processing events.
Otherwise, an aio_poll could eat the notification before the main
I/O thread invokes ppoll(). The main I/O thread then never wakes up.
This
On Tue, Jul 07, 2015 at 05:26:49PM +1000, David Gibson wrote:
On Fri, Jul 03, 2015 at 01:42:16PM +1000, Sam Bobroff wrote:
This patch set contains several small fixes to make QEMU more PAPR
compliant.
Applied to spapr-next, thanks.
In future, please CC me on PAPR related patches -
event_notifier_test_and_clear must be called before processing events.
Otherwise, an aio_poll could eat the notification before the main
I/O thread invokes ppoll(). The main I/O thread then never wakes up.
This is an example of what could happen:
i/o thread vcpu thread
On Fri, Jul 17, 2015 at 01:56:39PM +0200, Andrew Jones wrote:
Signed-off-by: Andrew Jones drjo...@redhat.com
Looks good to me, but I'd like an actual commit message: what's
dumpdtb, how and why would you use it.
---
hw/ppc/spapr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On Sun, Jul 19, 2015 at 07:51:00PM +0200, Paolo Bonzini wrote:
On 19/07/2015 01:52, Carlos L. Torres wrote:
+int err;
info-qemu = g_new0(VersionTriple, 1);
-info-qemu-major = strtol(version, tmp, 10);
+err = qemu_strtol(version, tmp, 10, (info-qemu-major));
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