Re: [Qemu-devel] rfc: vhost user enhancements for vm2vm communication

On Fri, Sep 11, 2015 at 05:39:07PM +0200, Claudio Fontana wrote: > On 09.09.2015 09:06, Michael S. Tsirkin wrote: > > On Mon, Sep 07, 2015 at 02:38:34PM +0200, Claudio Fontana wrote: > >> Coming late to the party, > >> > >> On 31.08.2015 16:11, Michael S. Tsirkin wrote: > >>> Hello! > >>> During

[Qemu-devel] [PATCH v2 7/8] target-arm: Break out mpidr_read_val()

From: "Edgar E. Iglesias" Break out mpidr_read_val() to allow future sharing of the code that conditionally sets the M and U bits of MPIDR. No functional changes. Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 7 ++- 1

[Qemu-devel] [PATCH v2 6/8] target-arm: Add VPIDR_EL2

From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h| 1 + target-arm/helper.c | 42 +- 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h

[Qemu-devel] [PATCH v2 8/8] target-arm: Add VMPIDR_EL2

From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h| 1 + target-arm/helper.c | 26 -- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h

[Qemu-devel] [PATCH v2 5/8] target-arm: Suppress EPD for S2, EL2 and EL3 translations

From: "Edgar E. Iglesias" Stage-2 translations, EL2 and EL3 regimes don't have the EPD control. Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

Re: [Qemu-devel] [RFC PATCH 1/3] pc: fw_cfg: move ioport base constant to pc.h

On Sat, 12 Sep 2015 19:30:40 -0400 "Gabriel L. Somlo" wrote: > Move BIOS_CFG_IOPORT define from pc.c to pc.h, and rename > it to FW_CFG_IO_BASE. Also, add FW_CFG_IO_SIZE define (set > to 0x02, to cover the overlapping 16-bit control and 8-bit > data ports). > > Signed-off-by:

Re: [Qemu-devel] [PATCH v2 0/2] intel_iommu: Add support for translation for devices behind bridges

On Sun, 2015-09-13 at 09:12 +1000, Benjamin Herrenschmidt wrote: > On Sat, 2015-09-12 at 20:37 +0200, Knut Omang wrote: > > As the thread went silent after our conclusions, I have made a > > second > > implementation for the Intel IOMMU according to this alternate > > scheme, > > It keeps the

Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode

On 09/06/2015 10:36 PM, Richard Henderson wrote: On Sep 5, 2015 14:35, Bastian Koppelmann wrote: IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and the manual is fairly clear about that. User mode cpu ought not to read these registers

Re: [Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd

On 09/03/2015 02:17 AM, Richard Henderson wrote: Note that the specification for lf.madd.s is confused. It's the only mention of supposed FPMADDHI/FPMADDLO special registers. On the other hand, or1ksim implements a somewhat normal non-fused multiply and add. Mirror that. Signed-off-by:

Re: [Qemu-devel] [PATCH] q35: Remove old machine versions

On Fri, Sep 11, 2015 at 03:44:47PM -0300, Eduardo Habkost wrote: > Ping? > > So, what's the reason we are still keeping those old machines in the > code? Victor also wanted to clean out some very old machine types for the PIIX, too. But if someone created a machine with libvirt, these machine

[Qemu-devel] [PATCH v2 3/8] target-arm: Add VTTBR_EL2

From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h| 1 + target-arm/helper.c | 34 -- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h

[Qemu-devel] [PATCH v2 2/8] target-arm: Add VTCR_EL2

From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h| 1 + target-arm/helper.c | 43 +-- 2 files changed, 42 insertions(+), 2 deletions(-) diff --git

[Qemu-devel] [PATCH v2 0/8] arm: Steps towards EL2 support round 4

From: "Edgar E. Iglesias" Hi, This is another series with small steps towards EL2 emulation. Patch 1 is a fix to allow easier testing of EL3-less cores. Patches 2 and on add regs and a few small steps towards 2-stage MMU. Comments welcome! Best regards, Edgar v1

[Qemu-devel] [PATCH v2 4/8] target-arm: Suppress TBI for S2 translations

From: "Edgar E. Iglesias" Stage-2 MMU translations do not have configurable TBI as the top byte is always 0 (48-bit IPAs). Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

[Qemu-devel] [PATCH v2 1/8] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully

From: "Edgar E. Iglesias" Handle missing CPU support for EL3 gracefully. Signed-off-by: Edgar E. Iglesias --- hw/cpu/a15mpcore.c | 2 +- hw/cpu/a9mpcore.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [Qemu-devel] Python problem

On 13 September 2015 at 03:19, Programmingkid wrote: > Excellent. This fixed the problem. Thank you very much. The minimum > version of python QEMU supports is 2.6? At the moment it should be 2.4, apart from this bug. However we're about to raise it to 2.6 (and there's

[Qemu-devel] [PATCH v2 2/2] hw/arm/virt-acpi-build: Add DBG2 table

Add a DBG2 table, describing the pl011 UART. Signed-off-by: Leif Lindholm --- hw/arm/virt-acpi-build.c | 60 +++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c

[Qemu-devel] [PATCH v2 0/2] ACPI/arm-virt: add DBG2

The Debug Port Table 2 (DBG2) is mandated by the ARM Server Base Boot Requirements specification. Add the DBG2 table definitions, and set up an entry in the ARM virt machine for the pl011 UART. Changes since v1: - Static structure replaced with separate Header/Device structs. - Missing

[Qemu-devel] [PATCH v2 1/2] ACPI: Add definitions for the DBG2 table

The DBG2 table can be considered a "companion" to SPCR - it points out debug consoles available in the system. Also update SPCR comments to reflect DBG2 is now described in this file, and update the supported SPCR specification revision (no functional change). Signed-off-by: Leif Lindholm

[Qemu-devel] [PATCH FYI 05/13] hw/acpi: add more flexible acpi_add_table() and build_header() variants

acpi_add_table() and build_header() hardcode a number of traits that we'd like to pass in later on, on a table-by-table basis. These are: - The fw_cfg file name of the blob that contains the ACPI table. ACPI_BUILD_TABLE_FILE is hard-coded at the moment. - The OEM Table ID field. Due to the way

[Qemu-devel] [PATCH FYI 08/13] hw/i386: build UEFI ACPI Data Table for VMGENID in the dedicated blob (WIP)

Using the tools - acpi_add_table2(), - build_header2() and the blob - ACPI_BUILD_QEMUPARAM_FILE that have been added in the previous patches, we can now implement the UEFI ACPI Data Table (and the related linker/loader commands) that are specified in "docs/vmgenid.txt". At this point the UEFI

[Qemu-devel] [PATCH FYI 13/13] hw/i386: generate AML for the VMGENID device (WIP)

This patch implements the "ACPI device, control methods" section of "docs/vmgenid.txt", with dynamic AML generation. A small portion of this patch was inspired by Gal Hammer's [PATCH V15 4/5] i386: add a Virtual Machine Generation ID device

[Qemu-devel] [PATCH FYI 12/13] hw/acpi: add AML generator function for CreateQWordField()

It follows the pattern of CreateDWordField() / aml_create_dword_field(). Cc: Paolo Bonzini Cc: Gal Hammer Cc: Igor Mammedov Cc: "Michael S. Tsirkin" Signed-off-by: Laszlo Ersek ---

[Qemu-devel] [PATCH FYI 06/13] hw/acpi: introduce ACPI_BUILD_QEMUPARAM_FILE

We'll build the UEFI ACPI Data Table for the VMGENID device in a separate fw_cfg blob (see "docs/vmgenid.txt"). When introducing a new fw_cfg blob for ACPI linker/loader purposes, we have to decide first if the new blob will be subject to patching on first guest access. (1) If so, then the blob

[Qemu-devel] [PATCH FYI 11/13] hw/acpi: add AML generator function for AccessAs()

The AccessAs(AccessType) macro can be used inside the Field() operator in ASL, for diverging from the Field's default access type, for the fields that follow AccessAs(). The new helper function allows us to generate the matching AML. The AccessAttribute parameter of the macro (described in the

Re: [Qemu-devel] Windows does not support DataTableRegion at all [was: docs: describe QEMU's VMGenID design]

On Sun, Sep 13, 2015 at 01:56:44PM +0200, Laszlo Ersek wrote: > As the subject suggests, I have terrible news. > > I'll preserve the full context here, so that it's easy to scroll back to > the ASL for reference. > > I'm also CC'ing edk2-devel, because a number of BIOS developers should > be

Re: [Qemu-devel] Python problem

On Sep 13, 2015, at 7:28 AM, Peter Maydell wrote: > On 13 September 2015 at 03:19, Programmingkid > wrote: >> Excellent. This fixed the problem. Thank you very much. The minimum >> version of python QEMU supports is 2.6? > > At the moment it should be 2.4, apart

Re: [Qemu-devel] [RFC PATCH 2/3] acpi: pc: add fw_cfg device node to ssdt

On Sat, Sep 12, 2015 at 07:30:41PM -0400, Gabriel L. Somlo wrote: > Add a fw_cfg device node to the ACPI SSDT. While the guest-side > BIOS can't utilize this information (since it has to access the > hard-coded fw_cfg device to extract ACPI tables to begin with), > having fw_cfg listed in ACPI

[Qemu-devel] [PATCH FYI 03/13] hw/acpi: rename "AcpiBuildTables.table_data" to "main_blob"

The identifier "table_data" is used in wildly different name spaces and scopes, which makes it practically impossible to grep for uses of "AcpiBuildTables.table_data" specifically. Rename the field to "main_blob" (which is a unique identifier across the tree), and update all references with the

[Qemu-devel] [PATCH FYI 02/13] hw/acpi: add i386 callbacks for injecting GPE 04 when the VMGENID changes

Add a new method called "vm_generation_id_changed" to the AcpiDeviceIfClass interface. The new method sends an ACPI notfication when the VM generation ID is changed. This contributes to the implementation of requirement R5, from "docs/vmgenid.txt". This patch is a slight modification of Gal

[Qemu-devel] [PATCH FYI 09/13] hw/acpi: expose more parameters for aml_method()

ACPI 1.0b defines the SerializeFlag in MethodFlags. We have not exposed this until now, but serializing methods that create named objects is warmly recommended by (recent versions of) the ACPI spec, and recent iasl actually warns about it. Therefore expose SerializeFlag in a new function. The old

[Qemu-devel] [PATCH FYI 10/13] hw/acpi: add AML generator function for DataTableRegion()

This ASL operator (and the underlying AML) enables named ACPI data tables to be located from AML code, and to be accessed field-wise, like an operation region. This is useful for passing down "parameter tables" to the guest; the ACPI linker/loader can relocate pointers in them, and then the AML

[Qemu-devel] Windows does not support DataTableRegion at all [was: docs: describe QEMU's VMGenID design]

As the subject suggests, I have terrible news. I'll preserve the full context here, so that it's easy to scroll back to the ASL for reference. I'm also CC'ing edk2-devel, because a number of BIOS developers should be congregating there. On 08/28/15 22:18, Laszlo Ersek wrote: > Cc: Paolo Bonzini

Re: [Qemu-devel] Windows does not support DataTableRegion at all [was: docs: describe QEMU's VMGenID design]

On 09/13/15 14:34, Michael S. Tsirkin wrote: > On Sun, Sep 13, 2015 at 01:56:44PM +0200, Laszlo Ersek wrote: >> As the subject suggests, I have terrible news. >> >> I'll preserve the full context here, so that it's easy to scroll back to >> the ASL for reference. >> >> I'm also CC'ing edk2-devel,

[Qemu-devel] [PATCH FYI 00/13] ACPI stuff for the DataTableRegion()-based VMGenID

So, as I wrote in the parent, this does not actually work in Windows, because Windows doesn't support the DataTableRegion() operator; not even modern Windows versions. I'm nonetheless posting the series for the following purposes: - Posterity. I think the series is worth preserving in the

[Qemu-devel] [PATCH FYI 01/13] docs: describe QEMU's VMGenID design

Cc: Paolo Bonzini Cc: Gal Hammer Cc: Igor Mammedov Cc: "Michael S. Tsirkin" Signed-off-by: Laszlo Ersek Acked-by: Michael S. Tsirkin --- Notes: fyi: - move from

[Qemu-devel] [PATCH FYI 07/13] hw/acpi: introduce the AcpiQemuParamTable structure

This ACPI table is supposed to carry various parameters for OSPM. We introduce it with a single parameter field, "vmgenid_addr_base_ptr", which is described as ADBP / "ADDR base pointer" in "docs/vmgenid.txt" (along with the general structure of the table). Cc: Paolo Bonzini

[Qemu-devel] [PATCH FYI 04/13] hw/acpi: allow RSDT entries to be relocated to various fw_cfg blobs

The build_rsdt() function can relocate RSDT entries only to ACPI tables that exist inside the same ACPI_BUILD_TABLE_FILE blob. In order to relax this limitation, change the element type of the "table_offsets" array from plain offset (always into ACPI_BUILD_TABLE_FILE) to a (pointed-to-blob,

Re: [Qemu-devel] [PATCH v2] hw/misc: Add support for ADC controller in Xilinx Zynq 7000

On Sat, Sep 12, 2015 at 2:08 PM, Guenter Roeck wrote: > Add support for the Xilinx XADC core used in Zynq 7000. > > References: > - Zynq-7000 All Programmable SoC Technical Reference Manual > - 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC > Dual 12-Bit 1 MSPS

Re: [Qemu-devel] [RFC PATCH 1/3] pc: fw_cfg: move ioport base constant to pc.h

On Sun, Sep 13, 2015 at 12:51:53PM +0200, Marc Marí wrote: > On Sat, 12 Sep 2015 19:30:40 -0400 > "Gabriel L. Somlo" wrote: > > > Move BIOS_CFG_IOPORT define from pc.c to pc.h, and rename > > it to FW_CFG_IO_BASE. Also, add FW_CFG_IO_SIZE define (set > > to 0x02, to cover the

Re: [Qemu-devel] [PATCH] imx_serial: Generate interrupt on tx empty if enabled

On Fri, Sep 11, 2015 at 12:37 AM, Michael Tokarev wrote: > > Can we please have some r-b or ACK for this? :) > > 20.08.2015 18:52, Guenter Roeck wrote: >> Generate an interrupt if the tx buffer is empty and the tx empty interrupt >> is enabled. This fixes a problem seen when

[Qemu-devel] [PATCH 2/2] target-ppc: fix xscmpodp and xscmpudp decoding

The xscmpodp and xscmpudp instructions only have the AX, BX bits in there encoding, the lowest bit (usually TX) is marked as an invalid bit. We therefore can't decode them with GEN_XX2FORM, which decodes the two lowest bit. Introduce a new form GEN_XX2FORM, which decodes AX and BX and mark the

[Qemu-devel] [PATCH 0/2] target-ppc: vector instruction fixes

This patchset fixes some vector instructions which are incorrectly decoded or implemented. The first patch is needed to run recent version of openssl, as it enabled POWER8 instrutctions when it detects such a CPU. Aurelien Jarno (2): target-ppc: fix vcipher, vcipherlast, vncipherlast and

[Qemu-devel] [PULL 6/6] sh4: Fix initramfs initialization for endiannes-mismatched targets

From: Guenter Roeck If host and target endianness does not match, loding an initramfs does not work. Fix by writing boot parameters with appropriate endianness conversion. Signed-off-by: Guenter Roeck Signed-off-by: Aurelien Jarno

[Qemu-devel] [PULL 2/6] target-sh4: use deposit in swap.b instruction

Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-sh4/translate.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index be0cb32..50043cf 100644 ---

[Qemu-devel] [PULL 3/6] target-sh4: improve cmp/str instruction

Instead of testing bytes one by one, we can use the following trick from https://graphics.stanford.edu/~seander/bithacks.html: haszero(v) = (v - 0x01010101) & ~v & 0x80808080 The subexpression v - 0x01010101, evaluates to a high bit set in any byte whenever the corresponding byte in v is zero

Re: [Qemu-devel] [RFC PATCH 2/3] acpi: pc: add fw_cfg device node to ssdt

On Sun, Sep 13, 2015 at 02:45:23PM +0300, Michael S. Tsirkin wrote: > On Sat, Sep 12, 2015 at 07:30:41PM -0400, Gabriel L. Somlo wrote: > > Add a fw_cfg device node to the ACPI SSDT. While the guest-side > > BIOS can't utilize this information (since it has to access the > > hard-coded fw_cfg

Re: [Qemu-devel] [RFC PATCH 1/3] pc: fw_cfg: move ioport base constant to pc.h

On Sun, 13 Sep 2015 13:28:24 -0400 "Gabriel L. Somlo" wrote: > On Sun, Sep 13, 2015 at 12:51:53PM +0200, Marc Marí wrote: > > On Sat, 12 Sep 2015 19:30:40 -0400 > > "Gabriel L. Somlo" wrote: > > > > > Move BIOS_CFG_IOPORT define from pc.c to pc.h, and rename > > >

Re: [Qemu-devel] [PATCH v2] hw/misc/zynq_slcr: Change CPU clock rate for Linux boots

On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote: > The Linux kernel only accepts 34 Khz and 67 Khz clock rates, and > may crash if the actual clock rate is too low. The clock rate used to be > (ps-clk-frequency * 26 / 4), which resulted in a CPU frequency of >

Re: [Qemu-devel] [PATCH v2] hw/misc/zynq_slcr: Change CPU clock rate for Linux boots

On 09/13/2015 01:22 PM, Peter Crosthwaite wrote: On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote: The Linux kernel only accepts 34 Khz and 67 Khz clock rates, and may crash if the actual clock rate is too low. The clock rate used to be (ps-clk-frequency * 26 /

[Qemu-devel] [PATCH 1/2] target-ppc: fix vcipher, vcipherlast, vncipherlast and vpermxor

For vector instructions, the helpers get pointers to the vector register in arguments. Some operands might point to the same register, including the operand holding the result. When emulating instructions which access the vector elements in a non-linear way, we need to store the result in an

Re: [Qemu-devel] [PATCH v2] hw/misc/zynq_slcr: Change CPU clock rate for Linux boots

On 13 September 2015 at 21:22, Peter Crosthwaite wrote: > On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote: >> The Linux kernel only accepts 34 Khz and 67 Khz clock rates, and >> may crash if the actual clock rate is too low. The clock

[Qemu-devel] [PULL 4/6] target-sh4: improve shld instruction

The SH4 shld instruction can shift in both direction, depending on the sign of the shift. This is currently implemented using branches, which is not really efficient and prevents the optimizer to do its job. In practice it is often used with a constant loaded in a register just before. Simplify

[Qemu-devel] [PULL 1/6] target-sh4: add flags markups for FP helpers

Most floating point helpers can trigger an exception, but don't change the globals. Mark these helpers as TCG_CALL_NO_WG. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-sh4/helper.h | 34 +- 1 file

[Qemu-devel] [PULL 0/6] sh4-next queue

-20150913 for you to fetch changes up to cdd14a8cf25c34ff8d0777530e8d16565f6bf7a1: sh4: Fix initramfs initialization for endiannes-mismatched targets (2015-09-13 23:08:51 +0200) sh4-next: - TCG optimizations - fix initramfs endianness

[Qemu-devel] [PULL 5/6] target-sh4: improve shad instruction

The SH4 shad instruction can shift in both direction, depending on the sign of the shift. This is currently implemented using branches, which is not really efficient and prevents the optimizer to do its job. In practice it is often used with a constant loaded in a register just before. Simplify

Re: [Qemu-devel] [PATCH V1] sdhci: Fix hostctl2 write logic.

On Fri, Sep 11, 2015 at 3:30 AM, Sai Pavan Boddu wrote: > From: Peter Crosthwaite > > This should be a shifted MASKED_WRITE like all other instances of > non-word aligned registers. > > Signed-off-by: Peter Crosthwaite

Re: [Qemu-devel] [RFC 00/20] Do away with TB retranslation

On 2015-09-10 19:48, Aurelien Jarno wrote: > On 2015-09-01 22:51, Richard Henderson wrote: > > I've been looking at this problem off and on for the last week or so, > > prompted by the sparc performance work. Although I havn't been able > > to get a proper sparc64 guest install working, I see the

[Qemu-devel] [PATCH 1/2] target-mips: get rid of MIPS_DEBUG

MIPS_DEBUG is a define used to dump the instruction disassembling. It has to be defined at compile time. In practice I believe it's more efficient to just look at the instruction disassembly and op dump using -d in_asm,op. This patch therefore removes the corresponding code, which clutters

[Qemu-devel] [PATCH 0/2] target-mips: get rid of old debugging code

This patchset get rid of old debugging code in translate.c, that has been superseded by other debugging way (e.g. (-d in_asm,op). It comes from the discussion there: https://lists.gnu.org/archive/html/qemu-devel/2015-07/msg03162.html I had it ready for some time, now that 2.4 has been release,

[Qemu-devel] [PATCH 2/2] target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS

MIPS_DEBUG_SIGN_EXTENSIONS was used sometimes ago to verify that 32-bit instructions correctly sign extend their results. It's now not need anymore, remove it. Cc: Leon Alrae Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 39

Re: [Qemu-devel] [PATCH v2] hw/misc/zynq_slcr: Change CPU clock rate for Linux boots

Peter, On 09/13/2015 01:47 PM, Peter Maydell wrote: On 13 September 2015 at 21:22, Peter Crosthwaite wrote: On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote: The Linux kernel only accepts 34 Khz and 67 Khz clock rates, and may

Re: [Qemu-devel] [PATCH v2 1/8] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully

On Sun, Sep 13, 2015 at 2:07 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Handle missing CPU support for EL3 gracefully. > What is the use case here? A9 and A15 should be able to not have EL3, but in this case the property

Re: [Qemu-devel] [PATCH v3] ppc/spapr: Implement H_RANDOM hypercall in QEMU

On Fri, Sep 11, 2015 at 11:17:01AM +0200, Thomas Huth wrote: > The PAPR interface defines a hypercall to pass high-quality > hardware generated random numbers to guests. Recent kernels can > already provide this hypercall to the guest if the right hardware > random number generator is available.

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 1/2] spapr: Add support for hwrng when available

On Fri, Sep 11, 2015 at 09:30:28AM +0200, Thomas Huth wrote: > On 11/09/15 02:45, David Gibson wrote: > > On Thu, Sep 10, 2015 at 02:03:39PM +0200, Thomas Huth wrote: > >> On 10/09/15 12:40, David Gibson wrote: > >>> On Thu, Sep 10, 2015 at 09:33:21AM +0200, Thomas Huth wrote: > On 09/09/15

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 1/2] spapr: Add support for hwrng when available

On Fri, Sep 11, 2015 at 11:43:02AM +0200, Alexander Graf wrote: > > > On 11.09.15 02:46, David Gibson wrote: > > On Thu, Sep 10, 2015 at 02:13:26PM +0200, Alexander Graf wrote: > >> > >> > >>> Am 10.09.2015 um 14:03 schrieb Thomas Huth : > >>> > On 10/09/15 12:40, David

Re: [Qemu-devel] [PATCH v2] hw/misc/zynq_slcr: Change CPU clock rate for Linux boots

On Sun, Sep 13, 2015 at 1:47 PM, Peter Maydell wrote: > On 13 September 2015 at 21:22, Peter Crosthwaite > wrote: >> On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote: >>> The Linux kernel only accepts 34 Khz and

Re: [Qemu-devel] [opnfv-tech-discuss] rfc: vhost user enhancements for vm2vm communication

Michael S. Tsirkin wrote on 2015-09-13: > On Fri, Sep 11, 2015 at 05:39:07PM +0200, Claudio Fontana wrote: >> On 09.09.2015 09:06, Michael S. Tsirkin wrote: >> >> There are many consequences to this, offset within BAR alone is not >> enough, there are multiple things at the virtio level that need

[Qemu-devel] [PATCH v8 3/7] scripts: Submit changes while updating linux headers

This submits changes with formatted commit log while updating Linux headers using scripts/update-linux-headers.sh. Signed-off-by: Gavin Shan --- scripts/update-linux-headers.sh | 30 ++ 1 file changed, 30 insertions(+) diff --git

[Qemu-devel] [PATCH v8 2/7] scripts: Include arch/powerpc/include/uapi/asm/eeh.h

This includes linux/arch/powerpc/include/uapi/asm/eeh.h while updating linux header files. The specific header file, introduced by the following Linux upstream commits for EEH on sPAPR platform: ed3e81f ("powerpc/eeh: Move PE state constants around") ec33d36 ("powerpc/eeh: Introduce

Re: [Qemu-devel] [RFC PATCH] spapr: Reduce creation of LMB DR connectors from O(n^3) to O(n^2)

On Fri, Sep 11, 2015 at 02:43:43PM +0200, Paolo Bonzini wrote: > > > On 10/09/2015 08:28, David Gibson wrote: > > The dynamic reconfiguration (hotplug) code for the pseries machine type > > uses a "DR connector" QOM object for each resource it will be possible > > to hotplug. Each of these is

[Qemu-devel] [RFCv2 2/2] spapr: Don't use QOM [*] syntax for DR connectors.

The dynamic reconfiguration (hotplug) code for the pseries machine type uses a "DR connector" QOM object for each resource it will be possible to hotplug. Each of these is added to its owner using object_property_add_child(owner, "dr-connector[*], ...); That works ok, mostly, but it means

[Qemu-devel] [PATCH v8 1/7] scripts: Allow include "stdint.h" in virtio headers

This allows to include "stdint.h" in virtio header files. Otherwise, scripts/update-linux-headers.sh fails when updating headers from Linux 4.2.rc8 kernel. include/uapi/linux/virtio_ring.h starts to include "stdint.h" from commit d768f32a ("virtio: Fix typecast of pointer in vring_init()").

[Qemu-devel] [PATCH v8 6/7] sPAPR: Support RTAS call ibm, {open, close}-errinjct

This supports RTAS calls "ibm,{open,close}-errinjct" to manupliate the token, which is passed to RTAS call "ibm,errinjct" to indicate the valid context for error injection. Each VM is permitted to have only one token at once and we simply have sequential number for that. The token is resetted in

[Qemu-devel] [PATCH v8 5/7] Obsolete PCI_MSIX_FLAGS_BIRMASK

This replaces PCI_MSIX_FLAGS_BIRMASK with PCI_MSIX_TABLE_BIR. Also, 3 more macros regarding MSIx table offset, MSIx PBA BAR index and MSIx PBA offset and this uses them. Besides, PCI_ERR_UNC_TRAIN is replaced with PCI_ERR_UNC_UND. The changes were introduced by below Linux upstream commits:

[Qemu-devel] [PATCH v8 4/7] Synchronize Linux headers from kernel 4.3.0-rc1

Synchronize the Linux headers from kernel version 4.3.0-rc1 (commit 6ff33f3) This commit was created automatically by update-linux-headers.sh. Signed-off-by: Gavin Shan --- include/standard-headers/linux/pci_regs.h| 381 ---

[Qemu-devel] [PATCH v8 0/7] sPAPR: Support EEH Error Injection

The patchset depends on below Linux upstream commits: commit ed3e81f ("powerpc/eeh: Move PE state constants around") commit ec33d36 ("powerpc/eeh: Introduce eeh_pe_inject_err()") According to PAPR specification 2.7, there're 3 RTAS calls relevent to error injection: "ibm,open-errinjct",

[Qemu-devel] [PATCH v8 7/7] sPAPR: Support RTAS call ibm,errinjct

The patch supports RTAS call "ibm,errinjct" to allow injecting EEH errors to VFIO PCI devices. The implementation is similiar to EEH support for VFIO PCI devices: The RTAS request is captured by QEMU and routed to spapr_phb_vfio_eeh_inject_error() where the request is translated to VFIO container

[Qemu-devel] [RFCv2 1/2] spapr: Remove unnecessary owner field from sPAPRDRConnector

The sPAPRDRConnector pseudo-device contains an owner field which is set in spapr_dr_connector_new(). However, that function also calls object_property_add_child() to set the DRConnector as the QOM child of the owner object. That means that owner is always the same as the QOM parent, and so

Re: [Qemu-devel] [RFC PATCH] spapr: Reduce creation of LMB DR connectors from O(n^3) to O(n^2)

On Fri, Sep 11, 2015 at 09:42:06PM +0530, Bharata B Rao wrote: > On Thu, Sep 10, 2015 at 04:28:25PM +1000, David Gibson wrote: > > The dynamic reconfiguration (hotplug) code for the pseries machine type > > uses a "DR connector" QOM object for each resource it will be possible > > to hotplug.

[Qemu-devel] [RFCv2 0/2] spapr: Cleanups to dynamic reconfiguration mechanism

Here are some cleanups and improvements to the "dynamic reconfiguration" (hotplug) infrastructure for the "pseries" machine type. There's an improved version of my patch to mitigate the O(n^3) time for large maxmem values, and another small cleanup to remove a redundant field in the structure.

Re: [Qemu-devel] [PATCH v8 3/7] scripts: Submit changes while updating linux headers

On Mon, Sep 14, 2015 at 11:36:11AM +1000, Gavin Shan wrote: > This submits changes with formatted commit log while updating Linux > headers using scripts/update-linux-headers.sh. > > Signed-off-by: Gavin Shan Reviewed-by: David Gibson >

Re: [Qemu-devel] [PATCH v8 0/7] sPAPR: Support EEH Error Injection

On Mon, Sep 14, 2015 at 11:36:08AM +1000, Gavin Shan wrote: > The patchset depends on below Linux upstream commits: > > commit ed3e81f ("powerpc/eeh: Move PE state constants around") > commit ec33d36 ("powerpc/eeh: Introduce eeh_pe_inject_err()") > > According to PAPR specification 2.7,

Re: [Qemu-devel] [PATCH v10 00/10] Add a netfilter object and netbuffer filter

On 09/14/2015 01:22 PM, Jason Wang wrote: On 09/14/2015 01:09 PM, Yang Hongyang wrote: Hi Stefan,Jason, I've convert this series to base on QOM, and introducing NetQueue apis instead of using Netqueue internals as Stefan suggested. Could you please take a look at it? Will go through this

Re: [Qemu-devel] [PATCH 5/7] vhost_net: move vhost_net_set_vq_index ahead at vhost_net_init

On Thu, Sep 10, 2015 at 02:54:02PM +0800, Jason Wang wrote: > > > On 09/10/2015 02:18 PM, Yuanhan Liu wrote: > > On Thu, Sep 10, 2015 at 01:52:30PM +0800, Jason Wang wrote: > >> > >> On 09/10/2015 01:17 PM, Yuanhan Liu wrote: > >>> On Thu, Sep 10, 2015 at 12:46:00PM +0800, Jason Wang wrote: >

Re: [Qemu-devel] [PATCH qemu v2 2/2] spapr_pci: Remove constraints about VFIO-PCI devices

On Fri, Sep 11, 2015 at 02:03:38PM -0600, Alex Williamson wrote: > On Wed, 2015-09-09 at 20:43 -0600, Alex Williamson wrote: > > On Thu, 2015-09-03 at 14:40 +1000, Alexey Kardashevskiy wrote: > > > So far there were 2 limitations enforced on an emulated PHB > > > regarding VFIO: > > > 1) only one

Re: [Qemu-devel] [PATCH 2/4] Fix bad error handling after memory_region_init_ram()

On Fri, Sep 11, 2015 at 7:51 AM, Markus Armbruster wrote: > Symptom: > > $ qemu-system-x86_64 -m 1000 > Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456: > upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory >

Re: [Qemu-devel] [PATCH 0/4] Don't abort when we can't allocate guest memory (again)

On Fri, Sep 11, 2015 at 7:51 AM, Markus Armbruster wrote: > Not nice: > > $ qemu-system-x86_64 -m 1000 > Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456: > upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory >

Re: [Qemu-devel] [RFCv2 2/2] spapr: Don't use QOM [*] syntax for DR connectors.

On Mon, Sep 14, 2015 at 09:37:16AM +0530, Bharata B Rao wrote: > On Mon, Sep 14, 2015 at 11:41:53AM +1000, David Gibson wrote: > > The dynamic reconfiguration (hotplug) code for the pseries machine type > > uses a "DR connector" QOM object for each resource it will be possible > > to hotplug.

Re: [Qemu-devel] [RFCv2 2/2] spapr: Don't use QOM [*] syntax for DR connectors.

On Mon, Sep 14, 2015 at 10:11:50AM +0530, Bharata B Rao wrote: > On Mon, Sep 14, 2015 at 02:14:59PM +1000, David Gibson wrote: > > On Mon, Sep 14, 2015 at 09:37:16AM +0530, Bharata B Rao wrote: > > > On Mon, Sep 14, 2015 at 11:41:53AM +1000, David Gibson wrote: > > > > The dynamic reconfiguration

Re: [Qemu-devel] [RFCv2 2/2] spapr: Don't use QOM [*] syntax for DR connectors.

On Mon, Sep 14, 2015 at 11:41:53AM +1000, David Gibson wrote: > The dynamic reconfiguration (hotplug) code for the pseries machine type > uses a "DR connector" QOM object for each resource it will be possible > to hotplug. Each of these is added to its owner using >

Re: [Qemu-devel] [RFCv2 2/2] spapr: Don't use QOM [*] syntax for DR connectors.

On Mon, Sep 14, 2015 at 02:14:59PM +1000, David Gibson wrote: > On Mon, Sep 14, 2015 at 09:37:16AM +0530, Bharata B Rao wrote: > > On Mon, Sep 14, 2015 at 11:41:53AM +1000, David Gibson wrote: > > > The dynamic reconfiguration (hotplug) code for the pseries machine type > > > uses a "DR connector"

Re: [Qemu-devel] [PATCH v10 00/10] Add a netfilter object and netbuffer filter

Hi Stefan,Jason, I've convert this series to base on QOM, and introducing NetQueue apis instead of using Netqueue internals as Stefan suggested. Could you please take a look at it? Most of the details have been reviewed by Jason, and the whole filter logic isn't changed. One missing feature

Re: [Qemu-devel] [PATCH v10 00/10] Add a netfilter object and netbuffer filter

On 09/14/2015 01:09 PM, Yang Hongyang wrote: > Hi Stefan,Jason, > > I've convert this series to base on QOM, and introducing NetQueue apis > instead of using Netqueue internals as Stefan suggested. Could you > please take a > look at it? Will go through this in next few days. > Most of the

Re: [Qemu-devel] [PATCH v3 2/4] block: Add 'ignore-backing' field to BlockdevOptionsGenericCOWFormat

On Fri 11 Sep 2015 07:33:41 PM CEST, Max Reitz wrote: >>> So why do we need the new flag? Because "backing: ''" is ugly? >> >> I guess it's just because you're the only one who actually reads the >> documentation. When discussing this, I didn't remember that we >> already had