Re: [Qemu-devel] [PATCH v19 08/10] Implement new driver for block replication

On 05/20/2016 03:36 PM, Changlong Xie wrote: +if (!failover) { +/* + * This BDS will be closed, and the job should be completed + * before the BDS is closed, because we will access hidden + * disk, secondary disk in backup_job_completed().

Re: [Qemu-devel] [PATCH v3 1/3] IOMMU: add VTD_CAP_CM to vIOMMU capability exposed to guest

On 6/7/2016 3:58 PM, Alex Williamson wrote: On Tue, 7 Jun 2016 11:20:32 +0800 Peter Xu wrote: On Mon, Jun 06, 2016 at 11:02:11AM -0600, Alex Williamson wrote: On Mon, 6 Jun 2016 21:43:17 +0800 Peter Xu wrote: On Mon, Jun 06, 2016 at 07:11:41AM

[Qemu-devel] [PATCH v3] spapr: Ensure all LMBs are represented in ibm, dynamic-memory

Memory hotplug can fail for some combinations of RAM and maxmem when DDW is enabled in the presence of devices like nec-usb-xhci. DDW depends on maximum addressable memory returned by guest and this value is currently being calculated wrongly by the guest kernel routine memory_hotplug_max(). While

Re: [Qemu-devel] [PATCH] net: mipsnet: check transmit buffer size before sending

+-- On Fri, 3 Jun 2016, P J P wrote --+ | +-- On Thu, 2 Jun 2016, Peter Maydell wrote --+ | | > case MIPSNET_TX_DATA_COUNT: | | > - s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; | | > +s->tx_count = (val < MAX_ETH_FRAME_SIZE) ? val : MAX_ETH_FRAME_SIZE; | | >

Re: [Qemu-devel] [PATCH v3 1/3] IOMMU: add VTD_CAP_CM to vIOMMU capability exposed to guest

On Mon, Jun 06, 2016 at 09:58:09PM -0600, Alex Williamson wrote: > On Tue, 7 Jun 2016 11:20:32 +0800 > Peter Xu wrote: [...] > > Only if cap_caching_mode() is set (which is bit 7, the CM bit), we > > will send these invalidations. What I meant is that, we should allow > > user

Re: [Qemu-devel] [PATCH v19 08/10] Implement new driver for block replication

On 05/20/2016 03:36 PM, Changlong Xie wrote: + +/* + * Must protect backup target if backup job was stopped/cancelled + * unexpectedly + */ +bdrv_ref(s->hidden_disk->bs); + +backup_start(s->secondary_disk->bs, s->hidden_disk->bs, 0, +

Re: [Qemu-devel] [PATCH v2 5/5] qcow2: Implement .bdrv_co_pwritev()

On 06/06/2016 08:59 AM, Kevin Wolf wrote: > This changes qcow2 to implement the byte-based .bdrv_co_pwritev > interface rather than the sector-based old one. > > As preallocation uses the same allocation function as normal writes, and > the interface of that function needs to be changed, it is

Re: [Qemu-devel] [PATCH v3 1/3] IOMMU: add VTD_CAP_CM to vIOMMU capability exposed to guest

On Tue, 7 Jun 2016 11:20:32 +0800 Peter Xu wrote: > On Mon, Jun 06, 2016 at 11:02:11AM -0600, Alex Williamson wrote: > > On Mon, 6 Jun 2016 21:43:17 +0800 > > Peter Xu wrote: > > > > > On Mon, Jun 06, 2016 at 07:11:41AM -0600, Alex Williamson wrote: >

Re: [Qemu-devel] [PATCH v2 4/5] qcow2: Use bytes instead of sectors for QCowL2Meta

On 06/06/2016 08:59 AM, Kevin Wolf wrote: > In preparation for implementing .bdrv_co_pwritev in qcow2. > > Signed-off-by: Kevin Wolf > --- > block/qcow2-cluster.c | 32 > block/qcow2.h | 13 +++-- > 2 files changed, 15

Re: [Qemu-devel] [PATCH v2 3/5] qcow2: Make copy_sectors() byte based

On 06/06/2016 08:59 AM, Kevin Wolf wrote: > This will allow copy on write operations where the overwritten part of > the cluster is not aligned to sector boundaries. > > Also rename the function because it has nothing to do with sectors any > more. > > Signed-off-by: Kevin Wolf

Re: [Qemu-devel] [PATCH qemu v17 06/12] memory: Add reporting of supported page sizes

On 06/06/16 23:31, Paolo Bonzini wrote: > > > On 02/06/2016 05:35, David Gibson wrote: >> On Wed, Jun 01, 2016 at 06:57:37PM +1000, Alexey Kardashevskiy wrote: Every IOMMU has some granularity which MemoryRegionIOMMUOps::translate uses when translating, however this information is not

Re: [Qemu-devel] [PATCH v2 01/22] migration: Define VMSTATE_UINT64_2DARRAY

On 2016/5/26 22:55, Peter Maydell wrote: > Define a VMSTATE_UINT64_2DARRAY macro, to go with the ones we > already have for other type sizes. > > Signed-off-by: Peter Maydell Reviewed-by: Shannon Zhao > --- > include/migration/vmstate.h |

[Qemu-devel] [PATCH 2/9] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors

The processor only uses some bits of the address and invalidates an entire congruence class. Some OSes such as Darwin and HelenOS take advantage of this and occasionally invalidate the entire TLB by just doing a series of 64 consecutive tlbie for example. Our code tries to be too smart here only

[Qemu-devel] [PATCH 3/9] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode

This ports the existing 64-bit mechanism to 32-bit, thus series of 64 tlbie's followed by a sync like some versions of Darwin (ab)use will result in a single flush. We apply a pending flush on any sync instruction though, as Darwin doesn't use tlbsync on non-SMP systems. Signed-off-by: Benjamin

Re: [Qemu-devel] [PATCH 0/6] Small tests/docker fixes

On Mon, 06/06 16:46, Paolo Bonzini wrote: > Small fixes, some of them being very close to personal preference. Looks good to me. Queued in my docker tree. https://github.com/famz/qemu/tree/docker.next Thanks, Fam

[Qemu-devel] [PATCH 4/9] ppc: POWER7 had ACOP and PID registers

We only had them on POWER8, add them to POWER7 as well Signed-off-by: Benjamin Herrenschmidt --- target-ppc/translate_init.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index

[Qemu-devel] [PATCH 8/9] ppc: Add missing slbfee. instruction on ppc64 BookS processors

Used to lookup SLB entries by address, for some reason it was missing. Signed-off-by: Benjamin Herrenschmidt --- target-ppc/helper.h | 1 + target-ppc/mmu-hash64.c | 30 ++ target-ppc/translate.c | 26 ++ 3

[Qemu-devel] [PATCH 7/9] ppc: Fix slbia decode

Since at least the 2.05 architecture, the slbia instruction takes an IH field in the opcode to provide some control on the effect of the slbia on the ERATs (level-1 TLB). We can safely ignore it as we always flush the whole qemu TLB but we should allow the bits in the decode. Signed-off-by:

Re: [Qemu-devel] [PATCH] docker: Don't use eval trick on Makefile

On Mon, 06/06 12:53, Eduardo Habkost wrote: > The eval trick for defining DOCKER_SRC_COPY doesn't do anything > useful, as DOCKER_SRC_COPY is immediately expanded just after it > is defined, and CUR_TIME is already defined using ":=". Simply > define it using ":=" so it is evaluated only once. >

Re: [Qemu-devel] [PATCH v3 1/3] IOMMU: add VTD_CAP_CM to vIOMMU capability exposed to guest

On Mon, Jun 06, 2016 at 11:02:11AM -0600, Alex Williamson wrote: > On Mon, 6 Jun 2016 21:43:17 +0800 > Peter Xu wrote: > > > On Mon, Jun 06, 2016 at 07:11:41AM -0600, Alex Williamson wrote: > > > On Mon, 6 Jun 2016 13:04:07 +0800 > > > Peter Xu wrote: > >

Re: [Qemu-devel] [PATCH qemu v17 07/12] vfio: spapr: Add DMA memory preregistering (SPAPR IOMMU v2)

On 07/06/16 03:20, Alex Williamson wrote: > On Mon, 6 Jun 2016 16:04:57 +1000 > Alexey Kardashevskiy wrote: > >> On 04/06/16 02:13, Alex Williamson wrote: >>> On Wed, 1 Jun 2016 18:57:38 +1000 >>> Alexey Kardashevskiy wrote: >>> This makes use of the new

Re: [Qemu-devel] [PATCH 2/2] Explicitly print out default vnc option in use

On Tue, 2016-06-07 at 08:28 +0800, Robert Hu wrote: > On Mon, 2016-06-06 at 09:28 +0200, Markus Armbruster wrote: > > Robert Hu writes: > > > > > On Tue, 2016-05-31 at 13:17 +0200, Markus Armbruster wrote: > > >> Robert Hu writes: > > >>

[Qemu-devel] [PATCH 1/9] ppc: Properly tag the translation cache based on MMU mode

We used to always flush the TLB when changing relocation mode in MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data). We don't anymore since we have split mmu_idx for instruction and data. However, since we hard code the mmu_idx in the translated code, we now need to also make sure

Re: [Qemu-devel] [RFC PATCH v4 1/3] Mediated device Core driver

> From: Alex Williamson [mailto:alex.william...@redhat.com] > Sent: Tuesday, June 07, 2016 3:31 AM > > On Mon, 6 Jun 2016 10:44:25 -0700 > Neo Jia wrote: > > > On Mon, Jun 06, 2016 at 04:29:11PM +0800, Dong Jia wrote: > > > On Sun, 5 Jun 2016 23:27:42 -0700 > > > Neo Jia

[Qemu-devel] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in privileged mode

The architecture specifies that mtspr/mfspr on an unknown SPR number should act as a nop in privileged mode. I haven't removed the warning however as it can be useful for diagnosing. Signed-off-by: Benjamin Herrenschmidt --- target-ppc/translate.c | 11 +-- 1

[Qemu-devel] [PATCH 6/9] ppc: Fix mtmsr decoding

We had code to handle the L bit in the opcode but we didn't allow it in the decode mask. Signed-off-by: Benjamin Herrenschmidt --- target-ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c

[Qemu-devel] [PATCH 5/9] ppc: POWER7 has lq/stq instructions and stq need to check ISA

The PPC_64BX instruction flag is used for a couple of newer instructions currently on POWER8 but our implementation for them works for POWER7 too (and already does the proper checking of what is permitted) with one exception: stq needs to check the ISA version. This fixes the latter and add the

[Qemu-devel] [PATCH v5 1/3] target-arm: kvm64: set guest PMUv3 feature bit if supported

From: Shannon Zhao Check if kvm supports guest PMUv3. If so, set the corresponding feature bit for vcpu. Signed-off-by: Shannon Zhao Reviewed-by: Andrew Jones --- target-arm/cpu.h | 2 ++ target-arm/kvm64.c | 5 + 2

[Qemu-devel] [PATCH v5 3/3] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table

From: Shannon Zhao Add PMU IRQ number in ACPI table, then we can use PMU in guest through ACPI. Signed-off-by: Shannon Zhao Reviewed-by: Andrew Jones --- hw/arm/virt-acpi-build.c | 4 1 file changed, 4 insertions(+)

[Qemu-devel] [PATCH v5 2/3] hw/arm/virt: Add PMU node for virt machine

From: Shannon Zhao Add a virtual PMU device for virt machine while use PPI 7 for PMU overflow interrupt number. Signed-off-by: Shannon Zhao Reviewed-by: Andrew Jones --- hw/arm/virt.c | 33

Re: [Qemu-devel] [RFC PATCH v3 3/3] VFIO Type1 IOMMU change: to support with iommu and without iommu

> From: Dong Jia > Sent: Monday, June 06, 2016 2:59 PM > [...] > Channel I/O is quite different to PCI, so I copied some more details > here. Hope these could help. > > Channel subsystem: > The channel subsystem directs the flow of information between I/O devices > and main storage. It

[Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt

From: Shannon Zhao KVM-ARM64 supports guest PMU now. This series add the support in machine virt so that guest could use PMU. The ACPI part is tested with below guest kernel patches. https://lkml.org/lkml/2016/4/12/755 Changes since v4: * fix building failure due to

Re: [Qemu-devel] coroutines: block: Co-routine re-entered recursively when migrating disk with iothreads

On Mon, 06/06 14:55, Jason J. Herne wrote: > > I'll see if I can reproduce it here. > > > > Fam > > > > Hi Fam, > Have you had any luck reproducing this? No I cannot reproduce so far.

Re: [Qemu-devel] [PATCH 1/6] tests/docker: fix make-archive-maybe

On Mon, 06/06 16:46, Paolo Bonzini wrote: > make-archive-maybe expects an archive path relative > to $1, but receives a path relative to the current directory. Redirect > the output outside the subshell to bypass the "cd $1". > > Signed-off-by: Paolo Bonzini > --- >

Re: [Qemu-devel] [PATCH v4 2/3] hw/arm/virt: Add PMU node for virt machine

On 2016/6/6 23:59, Peter Maydell wrote: > On 26 April 2016 at 12:40, Shannon Zhao wrote: >> > From: Shannon Zhao >> > >> > Add a virtual PMU device for virt machine while use PPI 7 for PMU >> > overflow interrupt number. >> > >> >

Re: [Qemu-devel] [RFC PATCH v2] spapr: Ensure all LMBs are represented in ibm, dynamic-memory

On Mon, Jun 06, 2016 at 07:46:53PM -0500, Michael Roth wrote: > Quoting Bharata B Rao (2016-06-06 06:37:49) > > Memory hotplug can fail for some combinations of RAM and maxmem when > > DDW is enabled in the presence of devices like nec-usb-xhci. DDW depends > > on maximum addressable memory

Re: [Qemu-devel] [PATCH 2/2] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors

On Tue, 2016-06-07 at 11:40 +1000, David Gibson wrote: > Ugh, this patch too is showing as corrupt for me.  I suspect the > problem is on my end, but I have no idea what, yet. No it's on mine. The latest update of evolution in Fedora broke sending patches :-( It unconditionally replaces 2 or

[Qemu-devel] [PATCH 1/6] ppc: POWER7 had ACOP and PID registers

We only had them on POWER8, add them to POWER7 as well Signed-off-by: Benjamin Herrenschmidt ---  target-ppc/translate_init.c | 18 ++  1 file changed, 18 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index

[Qemu-devel] [PATCH 1/6] ppc: POWER7 had ACOP and PID registers

We only had them on POWER8, add them to POWER7 as well Signed-off-by: Benjamin Herrenschmidt ---  target-ppc/translate_init.c | 18 ++  1 file changed, 18 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index

Re: [Qemu-devel] [PATCH 2/2] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors

On Mon, Jun 06, 2016 at 07:52:48PM +1000, Benjamin Herrenschmidt wrote: > The processor only uses some bits of the address and invalidates an > entire congruence class. Some OSes such as Darwin and HelenOS take > advantage of this and occasionally invalidate the entire TLB by just > doing a series

Re: [Qemu-devel] [PATCH 1/2] ppc: Properly tag the translation cache based on MMU mode

On Mon, Jun 06, 2016 at 07:52:44PM +1000, Benjamin Herrenschmidt wrote: > We used to always flush the TLB when changing relocation mode in > MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data). > > We don't anymore since we have split mmu_idx for instruction and data. > > However, since

Re: [Qemu-devel] [PATCH] scsi-disk: fix reads from scsi-disk devices

On Fri, 2016-06-03 at 06:17 +0100, Mark Cave-Ayland wrote: > Commit fcaafb1001b9c42817714dd3b2aadcfdb997b53d accidentally broke > reads from > scsi-disk devices when being updated from its original form to use > the new > byte-based block functions. Add the extra missing sector to offset >

[Qemu-devel] [PATCH 6/6] ppc: Do not take exceptions on unknown SPRs in privileged mode

The architecture specifies that mtspr/mfspr on an unknown SPR number should act as a nop in privileged mode. I haven't removed the warning however as it can be useful for diagnosing. Signed-off-by: Benjamin Herrenschmidt ---  target-ppc/translate.c | 11 +--  1

[Qemu-devel] [PATCH 4/6] ppc: Fix slbia decode

Since at least the 2.05 architecture, the slbia instruction takes an IH field in the opcode to provide some control on the effect of the slbia on the ERATs (level-1 TLB). We can safely ignore it as we always flush the whole qemu TLB but we should allow the bits in the decode. Signed-off-by:

[Qemu-devel] [PATCH 5/6] ppc: Add missing slbfee. instruction on ppc64 BookS processors

Used to lookup SLB entries by address, for some reason it was missing. Signed-off-by: Benjamin Herrenschmidt --- A version of this was in my earlier powernv series but had a bug, this one should be correct.  target-ppc/helper.h |  1 +  target-ppc/mmu-hash64.c | 30

[Qemu-devel] [PATCH 3/6] ppc: Fix mtmsr decoding

We had code to handle the L bit in the opcode but we didn't allow it in the decode mask. Signed-off-by: Benjamin Herrenschmidt ---  target-ppc/translate.c | 2 +-  1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c

[Qemu-devel] [PATCH 2/6] ppc: POWER7 has lq/stq instructions and stq need to check ISA version

The PPC_64BX instruction flag is used for a couple of newer instructions currently on POWER8 but our implementation for them works for POWER7 too (and already does the proper checking of what is permitted) with one exception: stq needs to check the ISA version. This fixes the latter and add the

[Qemu-devel] [Bug 1580459] Re: Windows (10?) guest freezes entire host on shutdown if using PCI passthrough

I've been not using USB host passthrough this whole time, as my PCI USB3 card covers that need pretty well. Speaking of those cards, for those of you who also use one, does it work perfectly? If so, I'd like to know its model so I can go buy it, because while my card works, about 50% of the time I

Re: [Qemu-devel] [PATCH v6 08/15] qdist: add module to represent frequency distributions of data

On Sat, May 28, 2016 at 21:15:06 +0300, Sergey Fedorov wrote: > On 25/05/16 04:13, Emilio G. Cota wrote: > > diff --git a/util/qdist.c b/util/qdist.c > > new file mode 100644 > > index 000..3343640 > > --- /dev/null > > +++ b/util/qdist.c > > @@ -0,0 +1,386 @@ > (snip) > > + > > +void

Re: [Qemu-devel] [RFC PATCH v2] spapr: Ensure all LMBs are represented in ibm, dynamic-memory

Quoting Bharata B Rao (2016-06-06 06:37:49) > Memory hotplug can fail for some combinations of RAM and maxmem when > DDW is enabled in the presence of devices like nec-usb-xhci. DDW depends > on maximum addressable memory returned by guest and this value is currently > being calculated wrongly by

Re: [Qemu-devel] [PATCH 2/2] Explicitly print out default vnc option in use

On Mon, 2016-06-06 at 09:28 +0200, Markus Armbruster wrote: > Robert Hu writes: > > > On Tue, 2016-05-31 at 13:17 +0200, Markus Armbruster wrote: > >> Robert Hu writes: > >> > >> > On Tue, 2016-05-31 at 09:51 +0200, Markus Armbruster

[Qemu-devel] [Bug 1580459] Re: Windows (10?) guest freezes entire host on shutdown if using PCI passthrough

So guys, new information. I was having trouble getting the HTC Vive passed through in host mode. The thing shows up as 10+ devices! I've also some logitech webcams that don't seem to work via usb host passthrough. So I gave windows my entire usb controller (only 1 for all my ports on this mobo).

Re: [Qemu-devel] [PATCH v6 08/15] qdist: add module to represent frequency distributions of data

On Fri, Jun 03, 2016 at 20:46:07 +0300, Sergey Fedorov wrote: > On 03/06/16 20:29, Sergey Fedorov wrote: > > On 03/06/16 20:22, Emilio G. Cota wrote: > >> On Sat, May 28, 2016 at 21:15:06 +0300, Sergey Fedorov wrote: > >>> On 25/05/16 04:13, Emilio G. Cota wrote: > >>> (snip) > +double

Re: [Qemu-devel] [PATCH v4 8/9] target-avr: adding instruction translation

On 06/06/2016 03:37 AM, Michael Rolnik wrote: +int avr_translate_AND(CPUAVRState *env, DisasContext *ctx, uint32_t opcode) +{ +TCGv Rd = cpu_r[AND_Rd(opcode)]; +TCGv Rr = cpu_r[AND_Rr(opcode)]; +TCGv R = tcg_temp_new_i32(); + +/* op */ +tcg_gen_and_tl(R, Rd, Rr);

Re: [Qemu-devel] [RFC/PATCH] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode

On Mon, 2016-06-06 at 23:36 +0100, Mark Cave-Ayland wrote: > > After another run of the OpenBIOS tests with this patch applied on top > of the previous 2 patches, I see no regressions introduced. Like Cédric > I don't get the feeling that the Mac machines necessarily run faster, > however the

Re: [Qemu-devel] [RFC/PATCH] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode

On 06/06/16 11:23, Benjamin Herrenschmidt wrote: > This ports the existing 64-bit mechanism to 32-bit, thus series > of 64 tlbie's followed by a sync like some versions of Darwin > (ab)use will result in a single flush. > > We apply a pending flush on any sync instruction though, as Darwin >

[Qemu-devel] [Bug 1580459] Re: Windows (10?) guest freezes entire host on shutdown if using PCI passthrough

SYSLINUX.CFG default /syslinux/menu.c32 menu title Lime Technology, Inc. prompt 0 timeout 50 label unRAID OS kernel /bzimage append isolcpus=4,16,5,17,6,18,7,19,8,20,9,21,10,22,11,23 pci-stub.ids=1b6f:7052,10de:13c2,10de:0fbb intel_iommu=on iommu=pt

Re: [Qemu-devel] [PATCH 1/2] ppc: Properly tag the translation cache based on MMU mode

On 06/06/16 10:52, Benjamin Herrenschmidt wrote: > We used to always flush the TLB when changing relocation mode in > MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data). > > We don't anymore since we have split mmu_idx for instruction and data. > > However, since we hard code the

[Qemu-devel] [Bug 1580459] Re: Windows (10?) guest freezes entire host on shutdown if using PCI passthrough

Current VM Config csmccarronwx00 82c5e4f6-6991-cd5f-8207-49db04386cc9 csmccarronwx00 i440fx-2.5 OVMF 10485760 10485760 12 /machine hvm

[Qemu-devel] [Bug 1580459] Re: Windows (10?) guest freezes entire host on shutdown if using PCI passthrough

Well for now my issue is resolved. This morning when I was shutting down my unRaid server to blacklist the intel sound module, snd-hda- intel, I first stopped my ubuntu vm and my two dockers then logged out of unraid. I then proceeded to shutdown my Windows 10 VM and like magic it shutdown

Re: [Qemu-devel] [PATCH v4 1/9] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

On 6 June 2016 at 11:37, Michael Rolnik wrote: > Signed-off-by: Michael Rolnik > --- > arch_init.c | 2 + > configure | 5 + > default-configs/avr-softmmu.mak | 1 + > disas/Makefile.objs | 1 + >

Re: [Qemu-devel] [PATCH v4 5/9] target-avr: adding AVR interrupt handling

On 6 June 2016 at 22:44, Richard Henderson wrote: > On 06/06/2016 03:37 AM, Michael Rolnik wrote: >> >> +if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { >> +stb_phys(cs->as, env->sp--, (ret & 0xff)); >> +stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >> 8);

Re: [Qemu-devel] [PATCH v4 4/9] target-avr: adding instructions encodings

On 6 June 2016 at 22:38, Richard Henderson wrote: > On 06/06/2016 03:37 AM, Michael Rolnik wrote: >> >> Signed-off-by: Michael Rolnik >> --- >> target-avr/translate-inst.h | 730 >> >> 1 file changed, 730

Re: [Qemu-devel] [PATCH v4 7/9] target-avr: adding instruction decoder

On 06/06/2016 03:37 AM, Michael Rolnik wrote: +void avr_decode(uint32_t pc, uint32_t *length, uint32_t code, translate_function_t *translate) +{ +uint32_t opcode = extract32(code, 0, 16); + +switch (opcode & 0xd000) { +case0x: { +uint32_t opcode =

[Qemu-devel] [PATCH] crypto: aes: always rename internal symbols

From: Mike Frysinger OpenSSL's libcrypto always defines AES symbols with the same names as qemu's local aes code. This is problematic when enabling at least curl as that frequently also uses libcrypto. It might not be noticed when running, but if you try to statically

Re: [Qemu-devel] [PATCH v4 6/9] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions

On 06/06/2016 03:37 AM, Michael Rolnik wrote: Signed-off-by: Michael Rolnik --- target-avr/helper.c | 153 target-avr/helper.h | 5 ++ 2 files changed, 147 insertions(+), 11 deletions(-) diff --git a/target-avr/helper.c

Re: [Qemu-devel] [PATCH v4 3/9] target-avr: adding a sample AVR board

On 6 June 2016 at 11:37, Michael Rolnik wrote: > Signed-off-by: Michael Rolnik > --- > hw/Makefile.objs | 1 + > hw/avr/Makefile.objs | 1 + > hw/avr/sample-io.c | 217 > +++ > hw/avr/sample.c

Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier

On 07/06/16 00:00, Peter Maydell wrote: > On 6 June 2016 at 21:30, Sergey Fedorov wrote: >> On 06/06/16 22:28, Pranith Kumar wrote: >>> On Mon, Jun 6, 2016 at 3:23 PM, Richard Henderson wrote: On 06/06/2016 10:11 AM, Pranith Kumar wrote: > If I

Re: [Qemu-devel] [PATCH v2 05/19] linux-user: Define macro for size of host kernel sigset_t

Le 27/05/2016 à 16:51, Peter Maydell a écrit : > Some host syscalls take an argument specifying the size of a > host kernel's sigset_t (which isn't necessarily the same as > that of the host libc's type of that name). Instead of hardcoding > _NSIG / 8 where we do this, define and use a

Re: [Qemu-devel] [PATCH v4 5/9] target-avr: adding AVR interrupt handling

On 06/06/2016 03:37 AM, Michael Rolnik wrote: +if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { +stb_phys(cs->as, env->sp--, (ret & 0xff)); +stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >> 8); +stb_phys(cs->as, env->sp--, (ret & 0xff) >> 16); +} else if

Re: [Qemu-devel] [PATCH v2 04/19] linux-user: Factor out uses of do_sigprocmask() from sigreturn code

Le 27/05/2016 à 16:51, Peter Maydell a écrit : > All the architecture specific handlers for sigreturn include calls > to do_sigprocmask(SIGSETMASK, , NULL) to set the signal mask > from the uc_sigmask in the context being restored. Factor these > out into calls to a set_sigmask() function. The

Re: [Qemu-devel] [PATCH v2 03/19] linux-user: Fix stray tab-indent

Le 27/05/2016 à 16:51, Peter Maydell a écrit : > Fix a stray tab-indented linux in linux-user/signal.c. > > Signed-off-by: Peter Maydell Reviewed-by: Laurent Vivier > --- > linux-user/signal.c | 3 ++- > 1 file changed, 2 insertions(+), 1

Re: [Qemu-devel] [PATCH v2 02/19] linux-user: Move handle_pending_signal() to avoid need for declaration

Le 27/05/2016 à 16:51, Peter Maydell a écrit : > Move the handle_pending_signal() function above process_pending_signals() > to avoid the need for a forward declaration. (Whitespace only change.) > > Signed-off-by: Peter Maydell Reviewed-by: Laurent Vivier

Re: [Qemu-devel] [PATCH v2 01/19] linux-user: Factor out handle_signal code from process_pending_signals()

Le 27/05/2016 à 16:51, Peter Maydell a écrit : > Factor out the code to handle a single signal from the > process_pending_signals() function. The use of goto for flow control > is OK currently, but would get significantly uglier if extended to > allow running the handle_signal code multiple

Re: [Qemu-devel] [PATCH v4 4/9] target-avr: adding instructions encodings

On 06/06/2016 03:37 AM, Michael Rolnik wrote: Signed-off-by: Michael Rolnik --- target-avr/translate-inst.h | 730 1 file changed, 730 insertions(+) create mode 100644 target-avr/translate-inst.h Reviewed-by: Richard Henderson

Re: [Qemu-devel] [PATCH v2 2/5] qcow2: Implement .bdrv_co_preadv()

On 06/06/2016 08:59 AM, Kevin Wolf wrote: > Reading from qcow2 images is now byte granularity. > > Most of the affected code in qcow2 actually gets simpler with this > change. The only exception is encryption, which is fixed on 512 bytes > blocks; in order to keep this working,

Re: [Qemu-devel] [PATCH v2] linux-user: provide frame information in x86-64 safe_syscall

On 06/06/2016 11:56 AM, Peter Maydell wrote: Use cfi directives in the x86-64 safe_syscall to allow gdb to get backtraces right from within it. (In particular this will be quite a common situation if the user interrupts QEMU while it's in a blocked safe-syscall: at the point of the syscall insn

Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier

On 6 June 2016 at 21:30, Sergey Fedorov wrote: > On 06/06/16 22:28, Pranith Kumar wrote: >> On Mon, Jun 6, 2016 at 3:23 PM, Richard Henderson wrote: >>> On 06/06/2016 10:11 AM, Pranith Kumar wrote: If I read it correctly TCG_BAR_SYNC is equivalent to

[Qemu-devel] [Bug 1581796] Re: console-gl.c:96:surface_gl_create_texture:code should not be reached

Hi T. yes the official git 2.6 from qemu.org No video come with all type of machine i had been tested: ppc, ppc64, i386, x86_64 , but this only on Ubuntu 16.10 on Fedora 24 all is working right . I think there is something broken on ubuntu 16.10. ah sorry i forgot ... on Fedora 24 qemu

Re: [Qemu-devel] [PATCH v4 3/9] target-avr: adding a sample AVR board

On 06/06/2016 03:37 AM, Michael Rolnik wrote: +void write_Rx(CPUAVRState *env, int inst, uint8_t data) +{ +env->r[inst] = data; +} +uint8_t read_Rx(CPUAVRState *env, int inst) Spacing. But more importantly... +static +void sample_io_write(void *opaque, hwaddr offset, uint64_t value,

Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier

On 06/06/16 22:28, Pranith Kumar wrote: > On Mon, Jun 6, 2016 at 3:23 PM, Richard Henderson wrote: >> On 06/06/2016 10:11 AM, Pranith Kumar wrote: >>> If I read it correctly TCG_BAR_SYNC is equivalent to OR of all the >>> other four barriers. I am not sure if we can just

[Qemu-devel] [PULL v2 0/9] Misc changes for 2016-06-06

The following changes since commit 76462405809d29bab65a3699686998ba124ab942: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160606-1' into staging (2016-06-06 17:02:42 +0100) are available in the git repository at: git://github.com/bonzini/qemu.git tags/for-upstream

Re: [Qemu-devel] [PATCH v4 2/9] target-avr: adding AVR CPU features/flavors

On 06/06/2016 03:37 AM, Michael Rolnik wrote: @@ -55,12 +55,14 @@ static void avr_cpu_reset(CPUState *s) AVRCPU *cpu = AVR_CPU(s); AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu); CPUAVRState *env = >env; +uint32_t features = env->features; mcc->parent_reset(s);

Re: [Qemu-devel] [PATCH v4 0/9] 8bit AVR cores

On 06/06/2016 12:49 PM, Michael Rolnik wrote: please advise. I have the following warning. but all print_instn_XXX functions are declared this way. so, I am kind of confused. I can fix it, but the file won't look the same. WARNING: space prohibited between function name and open parenthesis '('

Re: [Qemu-devel] [PATCH v4 1/9] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

On 06/06/2016 03:37 AM, Michael Rolnik wrote: +int print_insn_avr(bfd_vma addr, disassemble_info *info) +{ +int length = 0;; +/* TODO*/ +return length; +} Again, delete this file. This prohibits the default implementation from working. +static void avr_cpu_reset(CPUState

Re: [Qemu-devel] [PATCH v4 0/9] 8bit AVR cores

On 06/06/2016 12:53 PM, Michael Rolnik wrote: WARNING: architecture specific defines should be avoided #574: FILE: target-avr/cpu.h:32: +#if !defined(__CPU_AVR_H__) it was not my invention, I took it from either target-alpha or target-ppc. Let's not introduce any more mistakes. Follow

[Qemu-devel] [PATCH v2 5/6] target-i386: Use "-" instead of "_" on all feature names

This makes the feature name tables in feature_word_info all match the actual QOM property names we use. This will make the command-line interface more consistent, allowing the QOM property names to be used as "-cpu" arguments directly. Add extra feat2prop() calls to x86_cpu_parse_featurestr() to

[Qemu-devel] [PATCH v2 3/6] target-i386: Define CPUID filtering functions before x86_cpu_list()

Just move code to another place so the it can be reused by the query-cpu-definitions code. Signed-off-by: Eduardo Habkost --- target-i386/cpu.c | 68 +++ 1 file changed, 34 insertions(+), 34 deletions(-) diff --git

[Qemu-devel] [PATCH v2 4/6] qmp: Add runnability information to query-cpu-definitions

Extend query-cpu-definitions schema to allow it to return two new optional fields: "runnable" and "unavailable-features". "runnable" will tell if the CPU model can be run in the current host. "unavailable-features" will contain a list of CPU properties that are preventing the CPU model from

[Qemu-devel] [PATCH v2 6/6] target-i386: Return runnability information on query-cpu-definitions

Fill the "unavailable-features" field on the x86 implementation of query-cpu-definitions. Cc: Jiri Denemark Cc: libvir-l...@redhat.com Signed-off-by: Eduardo Habkost --- Changes v1 -> v2: * Updated to the new schema: no @runnable field, and always

[Qemu-devel] [PATCH v2 2/6] target-i386: Move warning code outside x86_cpu_filter_features()

x86_cpu_filter_features() will be reused by code that shouldn't print any warning. Move the warning code to a new x86_cpu_report_filtered_features() function, and call it from x86_cpu_realizefn(). Signed-off-by: Eduardo Habkost --- target-i386/cpu.c | 28

[Qemu-devel] [PATCH v2 1/6] target-i386: List CPU models using subclass list

Instead of using the builtin_x86_defs array, use the QOM subclass list to list CPU models on "-cpu ?" and "query-cpu-definitions". Signed-off-by: Andreas Färber [ehabkost: copied code from a patch by Andreas: "target-i386: QOM'ify CPU", from March 2012] Signed-off-by: Eduardo

[Qemu-devel] [PATCH v2 0/6] Add runnability info to query-cpu-definitions

This series extends query-cpu-definitions to include an extra field: "unavailable-features". The new field can be used to find out reasons that prevent the CPU model from running in the current host. This will return information based on the current machine and accelerator only. In the future we

[Qemu-devel] [PATCH] ui/console-gl: Add support for big endian display surfaces

This is required for running QEMU on big endian hosts (like PowerPC machines) that use RGB instead of BGR byte ordering. Ticket: https://bugs.launchpad.net/qemu/+bug/1581796 Signed-off-by: Thomas Huth --- ui/console-gl.c | 5 + 1 file changed, 5 insertions(+) diff --git

Re: [Qemu-devel] QEMU 2.7 release schedule?

On 06/06/2016 05:34 PM, Peter Maydell wrote: > Well, time to make a decision about our release date for 2.7. > > If you start out with "let's put the release in august like it > usually is but not so close to KVM Forum (24-26 Aug) as to > be likely to slip in to it", then you get something like:

Re: [Qemu-devel] [PATCH v4 0/9] 8bit AVR cores

WARNING: architecture specific defines should be avoided #574: FILE: target-avr/cpu.h:32: +#if !defined(__CPU_AVR_H__) it was not my invention, I took it from either target-alpha or target-ppc. On Mon, Jun 6, 2016 at 10:49 PM, Michael Rolnik wrote: > please advise. > I have

Re: [Qemu-devel] [PATCH v4 0/9] 8bit AVR cores

please advise. I have the following warning. but all print_instn_XXX functions are declared this way. so, I am kind of confused. I can fix it, but the file won't look the same. WARNING: space prohibited between function name and open parenthesis '(' #132: FILE: include/disas/bfd.h:424: +int

[Qemu-devel] [Bug 1581796] Re: console-gl.c:96:surface_gl_create_texture:code should not be reached

When you say it's failing with qemu 2.6, are you using the official release 2.6.0 or the current version from the git repository? Also, which target machine are you emulating? x86_64? ppc64? -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to

[Qemu-devel] [PATCH] Report error when opening device with locked tray

This commit causes qmp_blockdev_change_medium to report an error if an attempt is made to open a device with a locked tray. Signed-off-by: Colin Lord This is based off my previous patch regarding the do_open_tray function (currently at v3). Probably should have been submitted

Re: [Qemu-devel] [PATCH v4 0/9] 8bit AVR cores

On 06/06/2016 03:37 AM, Michael Rolnik wrote: changes since v3 1. rampD/X/Y/Z registers are encoded as 0x00ff and not 0x00ff for faster address manipulaton 2. ffs changed to ctz32 3. duplicate code removed at avr_cpu_do_interrupt 4. using andc instead of not + and 5. fixing V flag

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