[Qemu-devel] [PULL 4/8] ppc: Improve PCR bit selection in ppc_set_compat()

From: Thomas Huth When using an olderr PowerISA level, all the upper compatibility bits have to be enabled, too. For example when we want to run something in PowerISA 2.05 compatibility mode on POWER8, the bit for 2.06 has to be set beside the bit for 2.05. Additionally, to

[Qemu-devel] [PULL 1/8] ppc/spapr: Refactor h_client_architecture_support() CPU parsing code

From: Thomas Huth The h_client_architecture_support() function has become quite big and nested already. So factor out the code that takes care of the sPAPR compatibility PVRs (which will be modified by the following patches). Signed-off-by: Thomas Huth

[Qemu-devel] [PULL 7/8] macio: call dma_memory_unmap() at the end of each DMA transfer

From: Mark Cave-Ayland This ensures that the underlying memory is marked dirty once the transfer is complete and resolves cache coherency problems under MacOS 9. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson

[Qemu-devel] [PULL 3/8] ppc: Provide function to get CPU class of the host CPU

From: Thomas Huth When running with KVM, we might be interested in some details of the host CPU class, too, so provide a function to get the corresponding CPU class. Signed-off-by: Thomas Huth Reviewed-by: Michael Roth

Re: [Qemu-devel] [PATCH] hw/timer: Add value matching support to aspeed_timer

On Fri, 2016-06-10 at 11:42 +0100, Peter Maydell wrote: > On 10 June 2016 at 01:59, Andrew Jeffery wrote: > > > > On Thu, 2016-06-09 at 19:15 +0100, Peter Maydell wrote: > > > > > > On 27 May 2016 at 06:08, Andrew Jeffery wrote: > > > > > > > > > > > > Value

Re: [Qemu-devel] [PATCH] target-i386: kvm: cache KVM_GET_SUPPORTED_CPUID data

On Mon, Jun 13, 2016 at 12:02:41PM +0200, Paolo Bonzini wrote: > > > On 13/06/2016 04:21, Chao Peng wrote: > > KVM_GET_SUPPORTED_CPUID ioctl is called frequently when initializing > > CPU. Depends on CPU features and CPU count, the number of calls can be > > extremely high which slows down QEMU

Re: [Qemu-devel] [PATCH 5/5] block: Move request_alignment into BlockLimit

On 06/07/2016 04:08 AM, Kevin Wolf wrote: >> Found it; squash this in (or use it as an argument why we don't want >> request_alignment in bs->bl after all): > > This hunk doesn't make sense to me. For the correctness of the code it > shouldn't make a difference whether the alignment happens

Re: [Qemu-devel] [PATCH] net: mipsnet: check transmit buffer size before sending

On 2016年06月13日 16:35, Aurelien Jarno wrote: On 2016-06-02 10:28, Peter Maydell wrote: On 2 June 2016 at 07:44, P J P wrote: From: Prasad J Pandit When processing MIPSnet I/O port write operation, it uses a transmit buffer

[Qemu-devel] [Bug 1588328] Re: Qemu 2.6 Solaris 9 Sparc Segmentation Fault

Hi Mark, Attached is the new link: https://mega.nz/#!94ZVXBra!8QMsQ2d9eKKkMuawg_0YelfyWTy47CyyD1f6tvSv1bQ -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1588328 Title: Qemu 2.6 Solaris 9 Sparc

Re: [Qemu-devel] [PATCH v4] spapr: Ensure all LMBs are represented in ibm, dynamic-memory

On Fri, Jun 10, 2016 at 10:44:48AM +0530, Bharata B Rao wrote: > Memory hotplug can fail for some combinations of RAM and maxmem when > DDW is enabled in the presence of devices like nec-usb-xhci. DDW depends > on maximum addressable memory returned by guest and this value is currently > being

Re: [Qemu-devel] [PATCH v2 12/22] hw/intc/arm_gicv3: Implement GICv3 redistributor registers

On 2016/5/26 22:55, Peter Maydell wrote: > From: Shlomo Pongratz > > Implement the redistributor registers of a GICv3. > > Signed-off-by: Shlomo Pongratz > [PMM: significantly overhauled/rewritten: > * use the new data structures > *

Re: [Qemu-devel] [PATCH RFC 10/16] hw/ppc/spapr: don't use smp_cores, smp_threads

On Fri, Jun 10, 2016 at 07:40:21PM +0200, Andrew Jones wrote: > Use CPUState nr_cores,nr_threads and MachineState > cores,threads instead. > > Signed-off-by: Andrew Jones > --- > hw/ppc/spapr.c | 9 + > hw/ppc/spapr_rtas.c | 2 +- > 2 files changed, 6

Re: [Qemu-devel] [PATCH RFC 07/16] qom/cpu: make nr-cores, nr-threads real properties

On Sun, Jun 12, 2016 at 03:48:10PM +0200, Andrew Jones wrote: > On Sat, Jun 11, 2016 at 08:54:35AM +0200, Thomas Huth wrote: > > On 10.06.2016 19:40, Andrew Jones wrote: > > > Signed-off-by: Andrew Jones > > > --- > > > qom/cpu.c | 8 > > > 1 file changed, 8

Re: [Qemu-devel] [PATCH RFC 05/16] hw/core/machine: add smp properites

On Fri, Jun 10, 2016 at 07:40:16PM +0200, Andrew Jones wrote: > Signed-off-by: Andrew Jones > --- > hw/core/machine.c | 81 > + > include/hw/boards.h | 6 > 2 files changed, 87 insertions(+) > > diff --git

Re: [Qemu-devel] [PATCH v2 04/22] target-arm: Provide hook to tell GICv3 about changes of security state

On 2016/5/26 22:55, Peter Maydell wrote: > The GICv3 CPU interface needs to know when the CPU it is attached > to makes an exception level or mode transition that changes the > security state, because whether it is asserting IRQ or FIQ can change > depending on these things. Provide a mechanism

Re: [Qemu-devel] [PATCH RFC 02/16] vl: smp: add checks for maxcpus based topologies

On Fri, Jun 10, 2016 at 07:40:13PM +0200, Andrew Jones wrote: > smp_parse computes missing smp options. Unfortunately cores and > threads are computed by dividing smp_cpus, instead of max_cpus. > This is incorrect because the topology doesn't leave room for > hotplug. More unfortunately, we can't

Re: [Qemu-devel] [PATCH RFC 04/16] hw/core/machine: Introduce pre_init

On Fri, Jun 10, 2016 at 07:40:15PM +0200, Andrew Jones wrote: > From: Igor Mammedov > > Signed-off-by: Igor Mammedov > Signed-off-by: Andrew Jones I think this needs some kind of rationale. Since with this patch it is called

Re: [Qemu-devel] [PATCH RFC 01/16] vl: smp_parse: cleanups

On Fri, Jun 10, 2016 at 07:40:12PM +0200, Andrew Jones wrote: > No functional changes; only some code movement and removal of > dead code (impossible conditions). Also, max_cpus can be > initialized to 1, like smp_cpus, because it's either set by the > user or set to smp_cpus, when smp_cpus is set

Re: [Qemu-devel] [PATCH] macio: Use blk_drain instead of blk_drain_all

On Mon, 06/13 17:33, John Snow wrote: > > > On 06/12/2016 02:56 AM, Fam Zheng wrote: > > We only care about the associated backend, so blk_drain is more > > appropriate here. > > > > Signed-off-by: Fam Zheng > > --- > > hw/ide/macio.c | 2 +- > > 1 file changed, 1

Re: [Qemu-devel] [Qemu-block] [PATCH] macio: Use blk_drain instead of blk_drain_all

On Mon, 06/13 11:39, Kevin Wolf wrote: > Am 12.06.2016 um 08:56 hat Fam Zheng geschrieben: > > We only care about the associated backend, so blk_drain is more > > appropriate here. > > > > Signed-off-by: Fam Zheng > > [ Cc: John ] > > > --- > > hw/ide/macio.c | 2 +- > > 1

Re: [Qemu-devel] [QEMU 3/7] Add the hmp and qmp interface for dropping cache

> * Li, Liang Z (liang.z...@intel.com) wrote: > > > Because writing to this file is a nondestructive operation and dirty > > > objects are not freeable, the user should run sync(1) first. > > > [/quote] > > > > > > IOW, by 'slab' you mean dentries and inodes ? > > > > > Yes. > > > > > > +## > > >

Re: [Qemu-devel] [PULL 4/4] vl: Eliminate usb_enabled()

On Mon, Jun 13, 2016 at 03:10:29PM +0200, Gerd Hoffmann wrote: > From: Eduardo Habkost > > This wrapper for machine_usb(current_machine) is not necessary, > replace all usages of usb_enabled() with machine_usb(). > > Cc: Peter Maydell > Cc:

Re: [Qemu-devel] [PATCH] macio: call dma_memory_unmap() at the end of each DMA transfer

On Fri, Jun 10, 2016 at 07:26:37PM +0100, Mark Cave-Ayland wrote: > This ensures that the underlying memory is marked dirty once the transfer > is complete and resolves cache coherency problems under MacOS 9. > > Signed-off-by: Mark Cave-Ayland Applied to

[Qemu-devel] [PATCH 16/25] target-openrisc: Write back result before FPE exception

The architecture manual is unclear about this, but the or1ksim does writeback before the exception. This requires splitting the helpers in half, with the exception raised by the second. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH 24/25] target-openrisc: Generate goto_tb for direct branches

Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 348 ++-- 1 file changed, 173 insertions(+), 175 deletions(-) diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index cb9267d..4d29d22 100644 ---

[Qemu-devel] [PATCH 21/25] target-openrisc: Tidy insn dumping

Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 31f4307..3102190 100644 --- a/target-openrisc/translate.c +++

[Qemu-devel] [PATCH 22/25] target-openrisc: Tidy handling of delayed branches

Signed-off-by: Richard Henderson --- target-openrisc/cpu.h| 12 +--- target-openrisc/gdbstub.c| 2 +- target-openrisc/interrupt.c | 4 ++-- target-openrisc/sys_helper.c | 2 +- target-openrisc/translate.c | 40 5

[Qemu-devel] [PATCH 09/25] target-openrisc: Implement ff1 and fl1 for 64-bit

True, this is unused so far, but commented out is worse than actually implemented properly. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/int_helper.c | 23 --- 1 file changed, 12

[Qemu-devel] [PATCH 17/25] target-openrisc: Implement lwa, swa

Signed-off-by: Richard Henderson --- linux-user/main.c | 45 target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 9 + target-openrisc/interrupt.c| 1 + target-openrisc/interrupt_helper.c | 1 +

[Qemu-devel] [PATCH 19/25] target-openrisc: Tidy ppc/npc implementation

The NPC SPR is really only supposed to be used for FPGA debugging. It contains the same contents as PC, unless one plays games. Follow the or1ksim implementation in flushing delayed branch state when it is changed. The PPC SPR need not be updated every instruction, merely when we exit the TB or

[Qemu-devel] [PATCH 11/25] target-openrisc: Rationalize immediate extraction

The architecture manual is consistent in using "I" for signed fields and "K" for unsigned fields. Mirror that. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 200

[Qemu-devel] [PATCH 20/25] target-openrisc: Optimize l.jal to next

This allows the tcg optimizer to see, and fold, all of the constants involved in a GOT base register load sequence. Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH 23/25] target-openrisc: Optimize for r0 being zero

Signed-off-by: Richard Henderson --- target-openrisc/cpu.h | 5 +++- target-openrisc/exception_helper.c | 1 + target-openrisc/translate.c| 47 ++ 3 files changed, 52 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH 12/25] target-openrisc: Enable m[tf]spr from user mode

The architecture manual doesn't say these opcodes are user only. Leaving them disabled excludes user mode from accessing interesting SPRs like MACLO/MACHI. Signed-off-by: Richard Henderson --- target-openrisc/helper.h | 4 +-- target-openrisc/sys_helper.c | 77

[Qemu-devel] [PATCH 18/25] target-openrisc: Implement l.adrp

Not part of the v1.1 standard, but a proposed extension to vastly simplify both PIC and 64-bit mode. Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target-openrisc/translate.c

[Qemu-devel] [PATCH 07/25] target-openrisc: Keep SR_CY and SR_OV in a separate variables

This significantly streamlines carry and overflow production. Signed-off-by: Richard Henderson --- target-openrisc/cpu.h | 13 +++- target-openrisc/exception_helper.c | 33 --- target-openrisc/helper.h | 4 +- target-openrisc/translate.c

[Qemu-devel] [PATCH 04/25] target-openrisc: Keep SR_F in a separate variable

This avoids having to keep merging and extracting the flag from SR. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/cpu.h | 15 +- target-openrisc/gdbstub.c | 4 +-

[Qemu-devel] [PATCH 08/25] target-openrisc: Set flags on helpers

Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/helper.h | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h

[Qemu-devel] [PATCH 15/25] target-openrisc: Fix madd

Note that the specification for lf.madd.s is confused. It's the only mention of supposed FPMADDHI/FPMADDLO special registers. On the other hand, or1ksim implements a somewhat normal non-fused multiply and add. Mirror that. Reviewed-by: Bastian Koppelmann

[Qemu-devel] [PATCH 25/25] target-openrisc: Generate goto_tb for conditional branches

Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 54 +++-- 1 file changed, 28 insertions(+), 26 deletions(-) diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 4d29d22..be95248 100644 ---

[Qemu-devel] [PATCH 02/25] target-openrisc: Streamline arithmetic and OVE

Simplify overflow calculation. Move overflow exception check to a helper function, to eliminate inline branches. Remove some incorrect special casing of R0. Implement multiply inline. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH 05/25] target-openrisc: Use movcond where appropriate

Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target-openrisc/translate.c

[Qemu-devel] [PATCH 10/25] target-openrisc: Represent MACHI:MACLO as a single unit

Significantly simplifies the implementation of the use of MAC. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/cpu.h| 3 +- target-openrisc/sys_helper.c | 13 + target-openrisc/translate.c |

[Qemu-devel] [PATCH 06/25] target-openrisc: Put SR[OVE] in TB flags

Removes a call at execution time for overflow exceptions. Signed-off-by: Richard Henderson --- target-openrisc/cpu.h | 4 ++-- target-openrisc/exception_helper.c | 2 +- target-openrisc/translate.c| 24 +++- 3 files changed, 18

[Qemu-devel] [PATCH 14/25] target-openrisc: Implement muld, muldu, macu, msbu

Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 106 1 file changed, 106 insertions(+) diff --git a/target-openrisc/translate.c

[Qemu-devel] [PATCH 00/25] target-openrisc improvements

This is an update of a patch set last posted in September, and partially reviewed by Bastian at the time. r~ Richard Henderson (25): target-openrisc: Always enable OPENRISC_DISAS target-openrisc: Streamline arithmetic and OVE target-openrisc: Invert the decoding in dec_calc

[Qemu-devel] [PATCH 13/25] target-openrisc: Enable trap, csync, msync, psync for user mode

Not documented as disabled for user mode. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 32 1 file changed, 32 deletions(-) diff --git

[Qemu-devel] [PATCH 01/25] target-openrisc: Always enable OPENRISC_DISAS

Avoids warnings from unused variables etc. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 20 1 file changed, 4 insertions(+), 16 deletions(-) diff --git

[Qemu-devel] [PATCH 03/25] target-openrisc: Invert the decoding in dec_calc

Decoding the opcodes in the right order reduces by 100+ lines. Also, it happens to put the opcodes in the same order as Chapter 17. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 300

[Qemu-devel] Determining interest in PPC e500spin, yield, and openpic patches

We've used older versions of QEMU for several years as a virtual target for our OS. Many thanks to the community for providing this platform. We've been working to get our OS running under QEMU 2.x and have identified a few bugs in QEMU, have made some enhancements, and are still tracking down

Re: [Qemu-devel] qemu-img segfaults on MIPS hosts due to not having an executable stack

On Mon, Jun 13, 2016 at 04:16:02PM +0100, Peter Maydell wrote: > On 13 June 2016 at 15:45, Daniel P. Berrange wrote: > > On Mon, Jun 13, 2016 at 03:11:08PM +0100, Peter Maydell wrote: > >> QEMU currently allocates coroutine stacks with a plain g_malloc(), > >> which makes

Re: [Qemu-devel] [PATCH v3 2/3] error: Remove unnecessary local_err variables

On 06/13/2016 03:57 PM, Eduardo Habkost wrote: > This patch simplifies code that uses a local_err variable just to > immediately use it for an error_propagate() call. > > Coccinelle patch used to perform the changes added to > scripts/coccinelle/remove_local_err.cocci. > > Reviewed-by: Eric

Re: [Qemu-devel] [PATCH 4/6] linux-user: Provide safe_syscall for aarch64

On 13 June 2016 at 23:38, Richard Henderson wrote: > On 06/13/2016 03:28 PM, Peter Maydell wrote: >> glibc's syscall() takes the system parameter as an int and >> does a sign-extending move into x0 with an uxtw. >> safe_syscall() takes a long, so it's already 64 bits. > > >

Re: [Qemu-devel] [PATCH 4/6] linux-user: Provide safe_syscall for aarch64

On 06/13/2016 03:28 PM, Peter Maydell wrote: On 13 June 2016 at 23:21, Richard Henderson wrote: On 06/13/2016 03:04 PM, Peter Maydell wrote: +.global safe_syscall_base +.global safe_syscall_start +.global safe_syscall_end +.type

Re: [Qemu-devel] [PATCH 4/6] linux-user: Provide safe_syscall for aarch64

On 13 June 2016 at 23:21, Richard Henderson wrote: > On 06/13/2016 03:04 PM, Peter Maydell wrote: >>> >>> +.global safe_syscall_base >>> +.global safe_syscall_start >>> +.global safe_syscall_end >>> +.type safe_syscall_base, #function >>> +

Re: [Qemu-devel] [PATCH 4/6] linux-user: Provide safe_syscall for aarch64

On 13 June 2016 at 23:28, Peter Maydell wrote: > glibc's syscall() takes the system parameter as an int and > does a sign-extending move into x0 with an uxtw. ...zero-extending... -- PMM

Re: [Qemu-devel] [PATCH 6/6] linux-user: Provide safe_syscall for ppc64

On 13 June 2016 at 22:45, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > linux-user/host/ppc64/hostdep.h | 34 + > linux-user/host/ppc64/safe-syscall.inc.S | 87 > > 2 files changed,

Re: [Qemu-devel] [PATCH 4/6] linux-user: Provide safe_syscall for aarch64

On 06/13/2016 03:04 PM, Peter Maydell wrote: +.global safe_syscall_base +.global safe_syscall_start +.global safe_syscall_end +.type safe_syscall_base, #function +.type safe_syscall_start, #function +.type safe_syscall_end, #function _start

Re: [Qemu-devel] [PATCH 0/6] linux-user: safe_syscall updates

On 13 June 2016 at 22:53, Peter Maydell wrote: > On 13 June 2016 at 22:45, Richard Henderson wrote: >> Richard Henderson (6): >> linux-user: fix x86_64 safe_syscall >> linux-user: Provide safe_syscall for i386 >> linux-user: Provide safe_syscall

Re: [Qemu-devel] linux-user: drop support for "unknown" host CPUs (ie hppa and m68k) ?

On 06/13/2016 02:26 AM, Peter Maydell wrote: Currently our configure script allows linux-user targets to be built for "unknown" host CPU architectures (which must be using the TCI interpreter). However, code like user-exec.c has host-architecture #ifdef ladders which in practice mean you can't

Re: [Qemu-devel] [PATCH 4/6] linux-user: Provide safe_syscall for aarch64

On 13 June 2016 at 22:45, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > linux-user/host/aarch64/hostdep.h | 34 ++ > linux-user/host/aarch64/safe-syscall.inc.S | 72 > ++ > 2 files

[Qemu-devel] [PATCH v3 2/3] error: Remove unnecessary local_err variables

This patch simplifies code that uses a local_err variable just to immediately use it for an error_propagate() call. Coccinelle patch used to perform the changes added to scripts/coccinelle/remove_local_err.cocci. Reviewed-by: Eric Blake Acked-by: Cornelia Huck

[Qemu-devel] [PATCH v3 3/3] coccinelle: Remove unnecessary variables for function return value

Use Coccinelle script to replace 'ret = E; return ret' with 'return E'. The script will do the substitution only when the function return type and variable type are the same. Sending as RFC because the patch looks more intrusive than the others. Probably better to split it per subsystem and let

[Qemu-devel] [PATCH v3 0/3] coccinelle: Clean up error checks and return value variables

Changes v1 -> v2: * The Coccinelle scripts were simplified by using "when" constraints to detect when a variable is not used elsewhere inside the function. * Added script to remove unnecessary variables for function return value. * Coccinelle scripts added to scripts/coccinelle. Changes v2

[Qemu-devel] [PATCH v3 1/3] error: Remove NULL checks on error_propagate() calls

error_propagate() already ignores local_err==NULL, so there's no need to check it before calling. Coccinelle patch used to perform the changes added to scripts/coccinelle/error_propagate_null.cocci. Reviewed-by: Eric Blake Acked-by: Cornelia Huck

[Qemu-devel] [Bug 1589272] Re: qemu-system-x86_64: There is no option group 'vnc'

the latest commit i can works with with qemu is 70f87e0 -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1589272 Title: qemu-system-x86_64: There is no option group 'vnc' Status in QEMU: New Bug

[Qemu-devel] [PATCH 2/6] linux-user: Provide safe_syscall for i386

Signed-off-by: Richard Henderson --- linux-user/host/i386/hostdep.h | 34 ++ linux-user/host/i386/safe-syscall.inc.S | 110 2 files changed, 144 insertions(+) create mode 100644 linux-user/host/i386/hostdep.h create mode

Re: [Qemu-devel] [PATCH 0/6] linux-user: safe_syscall updates

On 13 June 2016 at 22:45, Richard Henderson wrote: > We added support for x86_64 in 4d330cee37a2; this adds support > for 5 more hosts. Also, tweak the signal_pending test for x86_64. > > > r~ > > > Richard Henderson (6): > linux-user: fix x86_64 safe_syscall > linux-user:

[Qemu-devel] [PATCH 3/6] linux-user: Provide safe_syscall for arm

Signed-off-by: Richard Henderson --- linux-user/host/arm/hostdep.h | 34 ++ linux-user/host/arm/safe-syscall.inc.S | 86 ++ 2 files changed, 120 insertions(+) create mode 100644 linux-user/host/arm/hostdep.h create mode

[Qemu-devel] [PATCH 6/6] linux-user: Provide safe_syscall for ppc64

Signed-off-by: Richard Henderson --- linux-user/host/ppc64/hostdep.h | 34 + linux-user/host/ppc64/safe-syscall.inc.S | 87 2 files changed, 121 insertions(+) create mode 100644 linux-user/host/ppc64/hostdep.h create mode

[Qemu-devel] [Bug 1589272] Re: qemu-system-x86_64: There is no option group 'vnc'

any notice of this? -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1589272 Title: qemu-system-x86_64: There is no option group 'vnc' Status in QEMU: New Bug description: build qemu from git

[Qemu-devel] [PATCH 5/6] linux-user: Provide safe_syscall for s390x

Signed-off-by: Richard Henderson --- linux-user/host/s390x/hostdep.h | 34 + linux-user/host/s390x/safe-syscall.inc.S | 87 2 files changed, 121 insertions(+) create mode 100644 linux-user/host/s390x/hostdep.h create mode

[Qemu-devel] [PATCH 1/6] linux-user: fix x86_64 safe_syscall

Do what the comment says, test for signal_pending non-zero, rather than the current coe which tests for bit 0 non-zero. Signed-off-by: Richard Henderson --- linux-user/host/x86_64/safe-syscall.inc.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[Qemu-devel] [PATCH 4/6] linux-user: Provide safe_syscall for aarch64

Signed-off-by: Richard Henderson --- linux-user/host/aarch64/hostdep.h | 34 ++ linux-user/host/aarch64/safe-syscall.inc.S | 72 ++ 2 files changed, 106 insertions(+) create mode 100644 linux-user/host/aarch64/hostdep.h create

[Qemu-devel] [PATCH 0/6] linux-user: safe_syscall updates

We added support for x86_64 in 4d330cee37a2; this adds support for 5 more hosts. Also, tweak the signal_pending test for x86_64. r~ Richard Henderson (6): linux-user: fix x86_64 safe_syscall linux-user: Provide safe_syscall for i386 linux-user: Provide safe_syscall for arm linux-user:

Re: [Qemu-devel] [PATCH v4 04/11] nbd: Improve server handling of bogus commands

On 13 Jun 2016, at 13:25, Eric Blake wrote: > On 06/13/2016 06:10 AM, Paolo Bonzini wrote: >> >> >> On 12/05/2016 00:39, Eric Blake wrote: >>> - If we report an error to NBD_CMD_READ, we are not writing out >>> any data payload; but the protocol says that a client can

Re: [Qemu-devel] [RESEND PATCH v3 0/8] libqos: use standard virtio headers

On 05/09/2016 08:47 AM, Stefan Hajnoczi wrote: > v2: > * Fix missing s/X/(1u << X)/ conversion in Patch 3 [Marc] > > This patch series eliminates code duplication in libqos virtio. > include/standard-headers/ contains the Linux virtio header files so we don't > need to define our own version

Re: [Qemu-devel] [RFC v2 3/3] Remove unnecessary variables for function return value

On Mon, Jun 13, 2016 at 01:29:47PM +0200, Markus Armbruster wrote: > Eduardo Habkost writes: > > > Use Coccinelle script to replace 'ret = E; return ret' with > > 'return E'. The script will do the substitution only when the > > function return type and variable type are the

Re: [Qemu-devel] [PATCH] macio: Use blk_drain instead of blk_drain_all

On 06/12/2016 02:56 AM, Fam Zheng wrote: > We only care about the associated backend, so blk_drain is more > appropriate here. > > Signed-off-by: Fam Zheng > --- > hw/ide/macio.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/ide/macio.c

Re: [Qemu-devel] [PATCH v6 08/11] target-avr: adding instruction translation

On 06/13/2016 01:25 PM, Michael Rolnik wrote: what is the difference between tcg_gen_qemu_st16 and tcg_gen_qemu_st_tl st16 is a legacy interface; st_tl is newer and has an argument that is a mask of MO_* bits. MO_BEUW is a convenience name for MO_BE | MO_16. r~

[Qemu-devel] [PULL 31/32] docs: add NVDIMM ACPI documentation

From: Xiao Guangrong It describes the basic concepts of NVDIMM ACPI and the interfaces between QEMU and the ACPI BIOS Signed-off-by: Xiao Guangrong Reviewed-by: Stefan Hajnoczi Reviewed-by: Michael S. Tsirkin

[Qemu-devel] [PULL 29/32] nvdimm acpi: support Get Namespace Label Data function

From: Xiao Guangrong Function 5 is used to get Namespace Label Data Reviewed-by: Stefan Hajnoczi Signed-off-by: Xiao Guangrong Reviewed-by: Stefan Hajnoczi Reviewed-by: Michael S.

Re: [Qemu-devel] [PATCH v6 00/13] data-driven device registers

On Fri, Jun 10, 2016 at 4:53 AM, Peter Maydell wrote: > On 9 June 2016 at 01:30, Alistair Francis wrote: >> On Thu, May 12, 2016 at 3:45 PM, Alistair Francis >> wrote: >>> This patch series is based on Peter C's

Re: [Qemu-devel] [PATCH v6 02/13] register: Add Register API

On Thu, Jun 9, 2016 at 11:55 AM, Peter Maydell wrote: > On 12 May 2016 at 23:45, Alistair Francis wrote: >> This API provides some encapsulation of registers and factors our some > > "out" > >> common functionality to common code. Bits of

[Qemu-devel] [PULL 27/32] nvdimm acpi: check revision

From: Xiao Guangrong Currently only revision 1 is supported Signed-off-by: Xiao Guangrong Reviewed-by: Stefan Hajnoczi Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin

[Qemu-devel] [PULL 32/32] MAINTAINERS: add Marcel to PCI

Marcel is reviewing PCI patches anyway, things will be easier if people remember to Cc him. Cc: Marcel Apfelbaum Signed-off-by: Michael S. Tsirkin --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index

Re: [Qemu-devel] [PATCH v6 01/13] bitops: Add MAKE_64BIT_MASK macro

On Thu, Jun 9, 2016 at 11:46 AM, Peter Maydell wrote: > On 12 May 2016 at 23:45, Alistair Francis wrote: >> Add a macro that creates a 64bit value which has length number of ones >> shifted acrros by the value of shift. > > "across" > >> >>

[Qemu-devel] [PULL 20/32] nvdimm: support nvdimm label

From: Xiao Guangrong Introduce a parameter, 'label-size', which is the size of nvdimm label data area which is reserved at the end of backend memory. It is required at least 128k Two callbacks, read_label_data() and write_label_data(), are used to operate the

[Qemu-devel] [PULL 21/32] acpi: add aml_object_type

From: Xiao Guangrong Implement ObjectType which is used by NVDIMM _DSM method in later patch Signed-off-by: Xiao Guangrong Reviewed-by: Stefan Hajnoczi Reviewed-by: Michael S. Tsirkin

Re: [Qemu-devel] [PATCH v3 0/4] enable iommu with -device

On Mon, Jun 13, 2016 at 05:36:56PM +0300, Marcel Apfelbaum wrote: > Create the iommu device with '-device intel-iommu' instead of > '-machine,iommu=on'. > > The device is part of the machine properties because we wanted > to ensure is created before any other PCI device. > > The alternative is

[Qemu-devel] [PULL 30/32] nvdimm acpi: support Set Namespace Label Data function

From: Xiao Guangrong Function 6 is used to set Namespace Label Data Reviewed-by: Stefan Hajnoczi Signed-off-by: Xiao Guangrong Reviewed-by: Stefan Hajnoczi Reviewed-by: Michael S.

[Qemu-devel] [PULL 18/32] msi_init: change return value to 0 on success

From: Cao jin No caller use its return value as msi capability offset, also in order to make its return behaviour consistent with msix_init(). cc: Michael S. Tsirkin cc: Paolo Bonzini cc: Hannes Reinecke cc: Markus

Re: [Qemu-devel] [PATCH 03/10] tests/vhost-user-bridge: workaround stale vring base

On Thu, Jun 09, 2016 at 12:25:54PM +0200, Marc-André Lureau wrote: > Hi > > On Thu, Jun 9, 2016 at 12:07 PM, Victor Kaplansky wrote: > > What if set_vring_base is called after set_vring_addr? > > Maybe it is worth to add the fixup to the set_vring_base as well? > > It would

[Qemu-devel] [PULL 17/32] fix some coding style problems

From: Cao jin It has: 1. More newlines make the code block well separated. 2. Add more comments for msi_init. 3. Fix a indentation in vmxnet3.c. 4. ioh3420 & xio3130_downstream: put PCI Express capability init function together, make it more readable. cc: Michael S.

[Qemu-devel] [PULL 28/32] nvdimm acpi: support Get Namespace Label Size function

From: Xiao Guangrong Function 4 is used to get Namespace label size Reviewed-by: Stefan Hajnoczi Signed-off-by: Xiao Guangrong Reviewed-by: Stefan Hajnoczi Reviewed-by: Michael S.

[Qemu-devel] [PULL 15/32] bios: Add tests for the IPMI ACPI and SMBIOS entries

From: Corey Minyard Signed-off-by: Corey Minyard Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/bios-tables-test.c | 60 ---

[Qemu-devel] [PULL 24/32] nvdimm acpi: save arg3 of _DSM method

From: Xiao Guangrong Check if the input Arg3 is valid then store it into ARG3 if it is needed Signed-off-by: Xiao Guangrong Reviewed-by: Stefan Hajnoczi Reviewed-by: Michael S. Tsirkin

[Qemu-devel] [PULL 14/32] acpi: Add IPMI table entries

From: Corey Minyard Use the ACPI table construction tools to create an ACPI entry for IPMI. This adds a function called build_acpi_ipmi_devices to add an DSDT entry for IPMI if IPMI is compiled in and an IPMI device exists. It also adds a dummy function if IPMI is not

[Qemu-devel] [PULL 12/32] smbios: Move table build tools into an include file.

From: Corey Minyard This will let things in other files (like IPMI) build SMBIOS tables. Signed-off-by: Corey Minyard Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/smbios/smbios_build.h |

[Qemu-devel] [PULL 26/32] nvdimm acpi: abstract the operations for root & nvdimm devices

From: Xiao Guangrong It separates the operations between root device and nvdimm devices in order to introducing label functions support for nvdimm device Signed-off-by: Xiao Guangrong Reviewed-by: Stefan Hajnoczi

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