[Qemu-devel] [PATCH v6 5/5] target-ppc: add vector permute right indexed instruction

Add vpermr instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 23 +++ target-ppc/translate/vmx-impl.inc.c | 18 ++

[Qemu-devel] [PULL 30/66] ppc: Rework NIP updates vs. exception generation

From: Benjamin Herrenschmidt We make env->nip almost always point to the faulting instruction, thus avoiding a mess of "store_current" vs "store_next" in the exception handling. The syscall exception knows to move the PC by 4 and that's really about it. This actually

[Qemu-devel] [PULL 27/66] ppc: Don't update NIP in lswi/lswx/stswi/stswx

From: Benjamin Herrenschmidt Instead, pass GETPC() result to the corresponding helpers. This requires a bit of fiddling to get the PC (hopefully) right in the case where we generate a program check, though the hacks there are temporary, a subsequent patch will clean

[Qemu-devel] [PULL 62/66] ppc: Improve the exception helpers flags

From: Benjamin Herrenschmidt They generate exceptions, but they don't update the environment Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Richard Henderson Signed-off-by: David Gibson ---

[Qemu-devel] [PATCH v6 1/5] target-ppc: add vector insert instructions

The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h

[Qemu-devel] [PULL 44/66] ppc: load/store multiple and string insns don't do LE

From: Benjamin Herrenschmidt Just generate an alignment interrupt Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 29 + 1 file changed,

[Qemu-devel] [PULL 19/66] ppc: Move DFP ops out of translate.c

From: Benjamin Herrenschmidt Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 365

[Qemu-devel] virtio-net & dhcp & udp checksum

Hi! I am trying DHCP between 2 guests. So I am running first guest with: -netdev tap,id=TAP0,helper=/home/aik/qemu-bridge-helper \ -device "virtio-net-pci,id=vnet0,mac=C0:41:49:4b:ee:ee,netdev=TAP0" and second one with: -netdev tap,id=TAP0,vhost=on,helper=/home/aik/qemu-bridge-helper \ -device

[Qemu-devel] [PULL 52/66] target-ppc: add vsrv instruction

From: Vivek Andrew Sha Adds Vector Shift Right Variable instruction. Signed-off-by: Vivek Andrew Sha [ reverse the order of computation to avoid temporary array ] Signed-off-by: Nikunj A Dadhania Reviewed-by:

[Qemu-devel] [PULL 33/66] ppc: Don't update NIP in facility unavailable interrupts

From: Benjamin Herrenschmidt This is no longer necessary as the helpers will properly retrieve the return address when needed. Also remove gen_update_current_nip() which didn't seem to make much sense to me. Signed-off-by: Benjamin Herrenschmidt

[Qemu-devel] [PULL 32/66] ppc: Don't update NIP in DCR access routines

From: Benjamin Herrenschmidt This is no longer necessary as the helpers will properly retrieve the return address when needed Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 65/66] tests: Resort check-qtest entries in Makefile.include

From: Thomas Huth The rather random list of check-qtest-xxx entries caused some confusion in the past, where to use "=" and where to use "+=" (see commits 0ccac16f59462b8e2b9afbc1 and 1f5c1cfbaec0792cd2e5da for example). Sorting the check-qtest-xxx entries by architecure

[Qemu-devel] [PULL 16/66] ppc: Provide basic raise_exception_* functions

From: Benjamin Herrenschmidt Instead of using the same helpers called from translate.c, let's have a bunch of functions that take the various argument combinations, especially the retaddr which will be needed in subsequent patches, and leave the helpers to be just that,

[Qemu-devel] [PULL 26/66] ppc: FP exceptions are always precise

From: Benjamin Herrenschmidt We don't implement imprecise FP exceptions and using store_current which sets SRR1 to the *previous* instruction never makes sense for these. So let's be truthful and make them precise, which is allowed by the architecture. Signed-off-by:

[Qemu-devel] [PULL 48/66] target-ppc: add dtstsfi[q] instructions

From: Sandipan Das DFP Test Significance Immediate [Quad] Signed-off-by: Sandipan Das Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson Signed-off-by: David Gibson

[Qemu-devel] [PULL 11/66] target-ppc: add cmpeqb instruction

From: Nikunj A Dadhania Search a byte in the stream of 8bytes provided in the register Suggested-by: Richard Henderson Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by:

[Qemu-devel] [PULL 10/66] target-ppc: add cnttzw[.] instruction

From: Nikunj A Dadhania Add ISA3.0: Count trailing zeros word instruction. Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target-ppc/helper.h

[Qemu-devel] [PULL 49/66] target-ppc: add vabsdu[b, h, w] instructions

From: Sandipan Das Adds following instructions: vabsdub: Vector Absolute Difference Unsigned Byte vabsduh: Vector Absolute Difference Unsigned Halfword vabsduw: Vector Absolute Difference Unsigned Word Signed-off-by: Sandipan Das [ use

[Qemu-devel] [PULL 05/66] target-ppc: adding addpcis instruction

From: Nikunj A Dadhania ISA 3.0 instruction for adding immediate value shifted with next instruction address and return the result in the target register. Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson

[Qemu-devel] [PULL 60/66] ppc: Don't generate dead code on unconditional branches

From: Benjamin Herrenschmidt We are always generating the "else" case of the condition even when generating an unconditional branch that will never hit it. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Richard Henderson

[Qemu-devel] [PULL 00/66] ppc-for-2.8 queue 20160906

The following changes since commit e87d397e5ef66276ccc49b829527d605ca07d0ad: Open 2.8 development tree (2016-09-05 11:38:54 +0100) are available in the git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.8-20160906 for you to fetch changes up to

[Qemu-devel] [PULL 42/66] ppc: Don't set access_type on all load/stores on hash64

From: Benjamin Herrenschmidt We don't use it so let's not generate the updates. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 4 +++- 1 file changed, 3

[Qemu-devel] [PULL 14/66] target-ppc: add maddhd and maddhdu instruction

From: Nikunj A Dadhania maddhd: Multiply-Add High Doubleword maddhdu: Multiply-Add High Doubleword Unsigned Above two instruction are dual form and differ by 1 bit (31st bit) Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword)

[Qemu-devel] [PULL 07/66] target-ppc: add modulo word operations

From: Nikunj A Dadhania Adding following instructions: moduw: Modulo Unsigned Word modsw: Modulo Signed Word Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson

[Qemu-devel] [PULL 53/66] target-ppc: add extswsli[.] instruction

From: Nikunj A Dadhania extswsli : Extend Sign Word & Shift Left Immediate Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson Reviewed-by: Richard Henderson Signed-off-by: David

[Qemu-devel] [PULL 43/66] ppc: Use a helper to generate "LE unsupported" alignment interrupts

From: Benjamin Herrenschmidt Some operations aren't allowed in LE mode, use a helper rather than open coding the exception generation. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 02/66] hw/ppc: include fdt helper routine in a common file

From: Cédric Le Goater spapr_pci would also be a good candidate but the macro _FDT is slightly different. It returns and does not exit. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/spapr.c| 11

[Qemu-devel] [PULL 55/66] hw/ppc: use error_report instead of fprintf

From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/spapr.c | 12 ++-- hw/ppc/spapr_drc.c | 8 hw/ppc/spapr_iommu.c | 4 ++-- hw/ppc/spapr_rtas.c | 13 +++--

[Qemu-devel] [PULL 12/66] target-ppc: add setb instruction

From: Vivek Andrew Sha The CR number is provided in the opcode as - BFA (11:13) Returns: -1 if bit 0 of CR field is set 1 if bit 1 of CR field is set 0 otherwise. Signed-off-by: Vivek Andrew Sha [ reworded commit, used 32bit ops as

[Qemu-devel] [PULL 28/66] ppc: Don't update NIP in lmw/stmw/icbi

From: Benjamin Herrenschmidt Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/mem_helper.c | 11 ++-

[Qemu-devel] [PULL 09/66] target-ppc: add cnttzd[.] instruction

From: Sandipan Das Add ISA3.0 Count trailing zeros double word Signed-off-by: Sandipan Das [ added ISA300 flag ] Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by:

[Qemu-devel] [PULL 03/66] target-ppc: Introduce Power9 family

From: "Aneesh Kumar K.V" The patch adds CPU PVR definition for POWER9 and enables QEMU to launch guests/linux-user in TCG mode. Signed-off-by: Aneesh Kumar K.V [ Added POWER9 alias, POWER9 SPAPR core and dropped MMU defines ]

[Qemu-devel] [PULL 54/66] ppc: Rename #include'd .c files to .inc.c

From: Benjamin Herrenschmidt Also while at it, group the #include statements in translate.c Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c

[Qemu-devel] [PULL 31/66] ppc: Fix source NIP on SLB related interrupts

From: Benjamin Herrenschmidt We need to pass it to the raise helper since we don't update it before the calls. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/mmu-hash64.c | 16

[Qemu-devel] [PULL 04/66] target-ppc: Introduce POWER ISA 3.0 flag

From: Nikunj A Dadhania This flag will be used for POWER9 instructions. Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson Signed-off-by: David Gibson --- target-ppc/cpu.h

[Qemu-devel] [PULL 58/66] ppc: Fix catching some segfaults in user mode

From: Benjamin Herrenschmidt The usermode "translate" code generates an error code value that has the "is_write" bit set, which causes our switch/case to miss and display "Invalid segfault errno" and a spurrious second state dump. Fix it. Signed-off-by: Benjamin

[Qemu-devel] [PULL 01/66] xics_kvm: drop extra checking of kernel_xics_fd

From: Greg Kurz We abort a few lines above if kernel_xics_fd == -1. This is only code cleanup. Signed-off-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/xics_kvm.c | 20 1 file changed, 8 insertions(+),

[Qemu-devel] [PULL 29/66] ppc: Make tlb_fill() use new exception helper

From: Benjamin Herrenschmidt Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/mmu_helper.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git

[Qemu-devel] [PULL 35/66] ppc: Don't update NIP on conditional trap instructions

From: Benjamin Herrenschmidt This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 18/66] ppc: Move embedded spe ops out of translate.c

From: Benjamin Herrenschmidt Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 1328

[Qemu-devel] [PULL 06/66] target-ppc: add cmprb instruction

From: Nikunj A Dadhania ISA 3.0 Compare Ranged Byte instruction useful for isupper/islower/isaplha kind of operation. Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson

[Qemu-devel] [PULL 40/66] ppc: Speed up dcbz

From: Benjamin Herrenschmidt Use tlb_vaddr_to_host to do a fast path single translate for the whole cache line. Also make the reservation check match the entire range. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson

[Qemu-devel] [PULL 20/66] ppc: Move VMX ops out of translate.c

From: Benjamin Herrenschmidt Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 1068

[Qemu-devel] [PULL 23/66] ppc: Make float_invalid_op_excp() pass the return address

From: Benjamin Herrenschmidt Instead of relying on NIP having been updated already Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/fpu_helper.c | 6 -- 1 file changed, 4

[Qemu-devel] [PULL 57/66] ppc: Fix macio ESCC legacy mapping

From: Benjamin Herrenschmidt The current mapping, while correct for the base ports (which is all the driver uses these days), is wrong for the extended registers. I suspect the bugs come from incorrect tables in the CHRP IO Ref document, I have verified the new values

[Qemu-devel] [PULL 66/66] tests: Check serial output of firmware boot of some machines

From: Thomas Huth Some of the machines that we have got a firmware image for write some output to the serial console while booting up. We can use this output to make sure that the machine is basically working, so this adds a test that checks the output of these machines for

[Qemu-devel] [PULL 62/66] ppc: Improve the exception helpers flags

From: Benjamin Herrenschmidt They generate exceptions, but they don't update the environment Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Richard Henderson Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 21/66] ppc: Move VSX ops out of translate.c

From: Benjamin Herrenschmidt Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 994

[Qemu-devel] [PULL 39/66] ppc: Handle unconditional (always/never) traps at translation time

From: Benjamin Herrenschmidt We don't need to call a helper for trap always and trap never which are used by Linux under some circumstances. Signed-off-by: Benjamin Herrenschmidt -- v2. Don't generate the helper call when trapping always

[Qemu-devel] [PULL 50/66] target-ppc: add vcmpnez[b, h, w][.] instructions

From: Swapnil Bokade Adds following instructions: vcmpnezb[.]: Vector Compare Not Equal or Zero Byte vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword vcmpnezw[.]: Vector Compare Not Equal or Zero Word Signed-off-by: Swapnil Bokade [

[Qemu-devel] [PULL 64/66] spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call

From: Laurent Vivier Since kernel v4.0, linux uses H_CHANGE_LOGICAL_LAN_MAC to change lively the MAC address of an ibmveth interface. As QEMU doesn't implement this h_call, we can't change anymore the MAC address of an spapr-vlan interface. Signed-off-by: Laurent Vivier

[Qemu-devel] [PULL 25/66] ppc: Don't update the NIP in floating point generated code

From: Benjamin Herrenschmidt This is no longer necessary as the helpers will properly retrieve the return address. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 65/66] tests: Resort check-qtest entries in Makefile.include

From: Thomas Huth The rather random list of check-qtest-xxx entries caused some confusion in the past, where to use "=" and where to use "+=" (see commits 0ccac16f59462b8e2b9afbc1 and 1f5c1cfbaec0792cd2e5da for example). Sorting the check-qtest-xxx entries by architecure

[Qemu-devel] [PULL 56/66] hw/ppc: add a ppc_create_page_sizes_prop() helper routine

From: Cédric Le Goater The exact same routine will be used in PowerNV. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/Makefile.objs | 2 +- hw/ppc/fdt.c | 49

[Qemu-devel] [PULL 40/66] ppc: Speed up dcbz

From: Benjamin Herrenschmidt Use tlb_vaddr_to_host to do a fast path single translate for the whole cache line. Also make the reservation check match the entire range. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson

[Qemu-devel] [PULL 22/66] ppc: Rename fload_invalid_op_excp to float_invalid_op_excp

From: Benjamin Herrenschmidt No other change Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/fpu_helper.c | 122 1 file changed,

[Qemu-devel] [PULL 47/66] target-ppc: implement branch-less divd[o][.]

From: Nikunj A Dadhania Similar to divw, implement branch-less divd. Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target-ppc/translate.c |

[Qemu-devel] [PULL 63/66] ppc: Improve a few more helper flags

From: Benjamin Herrenschmidt Mostly turn "store" type of helpers into TCG_CALL_NO_WG because they can take exceptions. Also fixup_thrm doesn't read nor write the tracked environment. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Richard

[Qemu-devel] [PULL 59/66] ppc: Stop dumping state on all exceptions in linux-user

From: Benjamin Herrenschmidt Other archs don't do it, some programs catch signals just fine and those dumps just clutter the output. Keep the dumps for cases that aren't supposed to happen such as unknown codes. Signed-off-by: Benjamin Herrenschmidt

[Qemu-devel] [PULL 37/66] ppc: Don't update NIP in dcbz and lscbx

From: Benjamin Herrenschmidt Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/mem_helper.c | 9 +

[Qemu-devel] [PULL 61/66] ppc: Improve flags for helpers loading/writing the time facilities

From: Benjamin Herrenschmidt Those helpers never load from or store to the TCG tracked environment, not do they generate synchronous exceptions (they might generate an asynchronous interrupt but that's not an issue here). So we can make them all use TCG_CALL_NO_RWG

[Qemu-devel] [PULL 30/66] ppc: Rework NIP updates vs. exception generation

From: Benjamin Herrenschmidt We make env->nip almost always point to the faulting instruction, thus avoiding a mess of "store_current" vs "store_next" in the exception handling. The syscall exception knows to move the PC by 4 and that's really about it. This actually

[Qemu-devel] [PULL 54/66] ppc: Rename #include'd .c files to .inc.c

From: Benjamin Herrenschmidt Also while at it, group the #include statements in translate.c Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c

[Qemu-devel] [PULL 44/66] ppc: load/store multiple and string insns don't do LE

From: Benjamin Herrenschmidt Just generate an alignment interrupt Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 29 + 1 file changed,

[Qemu-devel] [PULL 13/66] target-ppc: add maddld instruction

From: Nikunj A Dadhania maddld: Multiply-Add Low Doubleword Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the lower dword in the target register(RT). Signed-off-by: Nikunj A Dadhania

[Qemu-devel] [PULL 53/66] target-ppc: add extswsli[.] instruction

From: Nikunj A Dadhania extswsli : Extend Sign Word & Shift Left Immediate Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson Reviewed-by: Richard Henderson Signed-off-by: David

[Qemu-devel] [PULL 51/66] target-ppc: add vslv instruction

From: Vivek Andrew Sha vslv: Vector Shift Left Variable Signed-off-by: Vivek Andrew Sha Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson Reviewed-by: Richard Henderson

[Qemu-devel] [PULL 08/66] target-ppc: add modulo dword operations

From: Nikunj A Dadhania Adding following instructions for ISA3.0 support modud: Modulo Unsigned Dword modsd: Modulo Signed Dword Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson

[Qemu-devel] [PULL 43/66] ppc: Use a helper to generate "LE unsupported" alignment interrupts

From: Benjamin Herrenschmidt Some operations aren't allowed in LE mode, use a helper rather than open coding the exception generation. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 39/66] ppc: Handle unconditional (always/never) traps at translation time

From: Benjamin Herrenschmidt We don't need to call a helper for trap always and trap never which are used by Linux under some circumstances. Signed-off-by: Benjamin Herrenschmidt -- v2. Don't generate the helper call when trapping always

[Qemu-devel] [PULL 46/66] target-ppc: implement branch-less divw[o][.]

From: Nikunj A Dadhania While implementing modulo instructions figured out that the implementation uses many branches. Change the logic to achieve the branch-less code. Undefined value is set to dividend in case of invalid input. Signed-off-by: Nikunj A Dadhania

[Qemu-devel] [PULL 15/66] target-ppc: introduce opc4 for Expanded Opcode

From: Nikunj A Dadhania ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level indirect opcode table and corresponding parsing routines. EO (11:12) Expanded opcode field Formats: XX1 EO (11:15) Expanded opcode field Formats: VX, X, XX2 Signed-off-by:

[Qemu-devel] [PULL 42/66] ppc: Don't set access_type on all load/stores on hash64

From: Benjamin Herrenschmidt We don't use it so let's not generate the updates. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 4 +++- 1 file changed, 3

[Qemu-devel] [PULL 22/66] ppc: Rename fload_invalid_op_excp to float_invalid_op_excp

From: Benjamin Herrenschmidt No other change Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/fpu_helper.c | 122 1 file changed,

[Qemu-devel] [PULL 52/66] target-ppc: add vsrv instruction

From: Vivek Andrew Sha Adds Vector Shift Right Variable instruction. Signed-off-by: Vivek Andrew Sha [ reverse the order of computation to avoid temporary array ] Signed-off-by: Nikunj A Dadhania Reviewed-by:

Re: [Qemu-devel] [RFC 00/13] Live memory snapshot based on userfaultfd

Hi Andrea， I tested it with the new live memory snapshot with --enable-kvm, it doesn't work. To make things simple, I simplified the codes, only left the codes that can tested the write-protect capability. You can find the codes from

[Qemu-devel] [PULL 29/66] ppc: Make tlb_fill() use new exception helper

From: Benjamin Herrenschmidt Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/mmu_helper.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git

[Qemu-devel] [PULL 37/66] ppc: Don't update NIP in dcbz and lscbx

From: Benjamin Herrenschmidt Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/mem_helper.c | 9 +

[Qemu-devel] [PULL 41/66] ppc: Fix CFAR updates

From: Benjamin Herrenschmidt We were one instruction off Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 8 1 file changed, 4 insertions(+), 4 deletions(-)

[Qemu-devel] [PULL 19/66] ppc: Move DFP ops out of translate.c

From: Benjamin Herrenschmidt Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 365

[Qemu-devel] [PULL 49/66] target-ppc: add vabsdu[b, h, w] instructions

From: Sandipan Das Adds following instructions: vabsdub: Vector Absolute Difference Unsigned Byte vabsduh: Vector Absolute Difference Unsigned Halfword vabsduw: Vector Absolute Difference Unsigned Word Signed-off-by: Sandipan Das [ use

[Qemu-devel] [PULL 38/66] ppc: Make alignment exceptions suck less

From: Benjamin Herrenschmidt The current alignment exception generation tries to load the opcode to put in DSISR from a context where a cpu_ldl_code() is really not a good idea. It might fault and longjmp out and that's not something we want happening here. Instead,

[Qemu-devel] [PULL 17/66] ppc: Move classic fp ops out of translate.c

From: Benjamin Herrenschmidt Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/translate.c | 1205

[Qemu-devel] [PULL 33/66] ppc: Don't update NIP in facility unavailable interrupts

From: Benjamin Herrenschmidt This is no longer necessary as the helpers will properly retrieve the return address when needed. Also remove gen_update_current_nip() which didn't seem to make much sense to me. Signed-off-by: Benjamin Herrenschmidt

[Qemu-devel] [PULL 45/66] ppc: Speed up load/store multiple

From: Benjamin Herrenschmidt Use a single translate when not crossing a page boundary and avoid going through layers of helpers. MacOS uses those instructions a lot, so does OpenBIOS. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David

[Qemu-devel] [PULL 28/66] ppc: Don't update NIP in lmw/stmw/icbi

From: Benjamin Herrenschmidt Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/mem_helper.c | 11 ++-

[Qemu-devel] [PULL 31/66] ppc: Fix source NIP on SLB related interrupts

From: Benjamin Herrenschmidt We need to pass it to the raise helper since we don't update it before the calls. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/mmu-hash64.c | 16

[Qemu-devel] [PULL 55/66] hw/ppc: use error_report instead of fprintf

From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/spapr.c | 12 ++-- hw/ppc/spapr_drc.c | 8 hw/ppc/spapr_iommu.c | 4 ++-- hw/ppc/spapr_rtas.c | 13 +++--

[Qemu-devel] [PULL 13/66] target-ppc: add maddld instruction

From: Nikunj A Dadhania maddld: Multiply-Add Low Doubleword Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the lower dword in the target register(RT). Signed-off-by: Nikunj A Dadhania

[Qemu-devel] [PULL 32/66] ppc: Don't update NIP in DCR access routines

From: Benjamin Herrenschmidt This is no longer necessary as the helpers will properly retrieve the return address when needed Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 60/66] ppc: Don't generate dead code on unconditional branches

From: Benjamin Herrenschmidt We are always generating the "else" case of the condition even when generating an unconditional branch that will never hit it. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Richard Henderson

[Qemu-devel] [PULL 36/66] ppc: Don't update NIP if not taking alignment exceptions

From: Benjamin Herrenschmidt Move the NIP update to after the conditional branch so that we don't do it if we aren't going to take the alignment exception Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson

[Qemu-devel] [PULL 23/66] ppc: Make float_invalid_op_excp() pass the return address

From: Benjamin Herrenschmidt Instead of relying on NIP having been updated already Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/fpu_helper.c | 6 -- 1 file changed, 4

[Qemu-devel] [PULL 26/66] ppc: FP exceptions are always precise

From: Benjamin Herrenschmidt We don't implement imprecise FP exceptions and using store_current which sets SRR1 to the *previous* instruction never makes sense for these. So let's be truthful and make them precise, which is allowed by the architecture. Signed-off-by:

[Qemu-devel] [PULL 24/66] ppc: Make float_check_status() pass the return address

From: Benjamin Herrenschmidt Instead of relying on NIP having been updated already. Signed-off-by: Benjamin Herrenschmidt [dwg: Fold in fix to mark function always_inline] Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 25/66] ppc: Don't update the NIP in floating point generated code

From: Benjamin Herrenschmidt This is no longer necessary as the helpers will properly retrieve the return address. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 57/66] ppc: Fix macio ESCC legacy mapping

From: Benjamin Herrenschmidt The current mapping, while correct for the base ports (which is all the driver uses these days), is wrong for the extended registers. I suspect the bugs come from incorrect tables in the CHRP IO Ref document, I have verified the new values

[Qemu-devel] [PULL 10/66] target-ppc: add cnttzw[.] instruction

From: Nikunj A Dadhania Add ISA3.0: Count trailing zeros word instruction. Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target-ppc/helper.h

[Qemu-devel] [PULL 34/66] ppc: Don't update NIP BookE 2.06 tlbwe

From: Benjamin Herrenschmidt This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 58/66] ppc: Fix catching some segfaults in user mode

From: Benjamin Herrenschmidt The usermode "translate" code generates an error code value that has the "is_write" bit set, which causes our switch/case to miss and display "Invalid segfault errno" and a spurrious second state dump. Fix it. Signed-off-by: Benjamin

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