Re: [Qemu-devel] [PATCH] block: nvme: correct the nvme queue id check

+-- On Sat, 22 Oct 2016, Peter Maydell wrote --+ | Secondly, it's almost the same as this cleanup | patch from Thomas Huth that's already in qemu-trivial: | http://patchwork.ozlabs.org/patch/681349/ | | except that your version is removing the ! | negations from the return value. | | Can you

Re: [Qemu-devel] [PATCH V5 2/7] nios2: Add architecture emulation support

On 10/22/2016 08:01 PM, Marek Vasut wrote: For signed division, you have to protect against 0x8000 / -1 as well, which raises an overflow exception on the x86 host. You mean similar to what mips does on OPC_DIV vs OPC_DIVU , right ? Yes. No CPU_LOG_TB_IN_ASM disassembly? I thought

Re: [Qemu-devel] [PATCH V5 2/7] nios2: Add architecture emulation support

On 10/20/2016 04:35 PM, Richard Henderson wrote: > On 10/20/2016 06:44 AM, Marek Vasut wrote: >> +typedef struct Nios2Instruction { >> +void (*handler)(DisasContext *dc, uint32_t code, TCGMemOp >> flags); >> +uint32_t flags; >> +} Nios2Instruction; > > I gave you some bad advice wrt

[Qemu-devel] [Bug 1626972] Fwd: [PATCH] vhost: secure vhost shared log files using argv paremeter

> Begin forwarded message: > > From: Rafael David Tinoco > Subject: Re: [Qemu-devel] [PATCH] vhost: secure vhost shared log files using > argv paremeter > Date: October 22, 2016 at 19:52:31 GMT-2 > To: Marc-André Lureau > Cc: Rafael

[Qemu-devel] [Bug 1626972] Fwd: [PATCH] vhost: secure vhost shared log files using argv paremeter

> Begin forwarded message: > > From: Marc-André Lureau > Subject: Re: [Qemu-devel] [PATCH] vhost: secure vhost shared log files using > argv paremeter > Date: October 22, 2016 at 05:18:02 GMT-2 > To: Rafael David Tinoco > Cc: QEMU

Re: [Qemu-devel] [PATCH] vhost: secure vhost shared log files using argv paremeter

Hello, > On Oct 22, 2016, at 05:18, Marc-André Lureau > wrote: > > Hi > > On Sat, Oct 22, 2016 at 10:01 AM Rafael David Tinoco > wrote: > Commit 31190ed7 added a migration blocker in vhost_dev_init() to > check if memfd would succeed.

[Qemu-devel] [PULL 34/35] target-alpha: Introduce MMU_PHYS_IDX

Rather than using helpers for physical accesses, use a mmu index. The primary cleanup is with store-conditional on physical addresses. Signed-off-by: Richard Henderson --- target-alpha/cpu.h| 18 +--- target-alpha/helper.c | 8 ++ target-alpha/helper.h

[Qemu-devel] [PATCH] vhost: secure vhost shared log files using argv paremeter

Commit 31190ed7 added a migration blocker in vhost_dev_init() to check if memfd would succeed. It is better if this blocker first checks if vhost backend requires shared log. This will avoid a situation where a blocker is added inappropriately (e.g. shared log allocation fails when vhost backend

Re: [Qemu-devel] [PATCH] tcg/tcg.h: Improve documentation of TCGv_i32 etc types

On 10/21/2016 09:38 AM, Peter Maydell wrote: The typedefs we use for the TCGv_i32, TCGv_i64 and TCGv_ptr types are somewhat confusing, because we define them as pointers to structs, but the structs themselves are never defined. Explain in the comments a bit more clearly why this is OK and what

[Qemu-devel] [PULL 33/35] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info}

From: "Emilio G. Cota" The exception is not emitted anymore; remove it and the associated TCG variables. Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson Message-Id:

[Qemu-devel] [PULL 29/35] target-arm: emulate SWP with atomic_xchg helper

From: "Emilio G. Cota" Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-25-git-send-email-c...@braap.org> Signed-off-by: Richard Henderson --- target-arm/translate.c | 26 ++ 1 file changed, 14 insertions(+),

[Qemu-devel] [PULL 35/35] target-alpha: Emulate LL/SC using cmpxchg helpers

Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. However, portable parallel code is written assuming only cmpxchg which means that in practice this is a viable alternative. Signed-off-by: Richard Henderson --- linux-user/main.c|

[Qemu-devel] [PULL 17/35] target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers

From: "Emilio G. Cota" The diff here is uglier than necessary. All this does is to turn FOO into: if (s->prefix & PREFIX_LOCK) { BAR } else { FOO } where FOO is the original implementation of an unlocked cmpxchg. [rth: Adjust unlocked cmpxchg to use movcond instead of

[Qemu-devel] [PULL 26/35] tests: add atomic_add-bench

From: "Emilio G. Cota" With this microbenchmark we can measure the overhead of emulating atomic instructions with a configurable degree of contention. The benchmark spawns $n threads, each performing $o atomic ops (additions) in a loop. Each atomic operation is performed on a

[Qemu-devel] [PULL 30/35] target-arm: emulate aarch64's LL/SC using cmpxchg helpers

From: "Emilio G. Cota" Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. Portable parallel code, however, is written assuming only cmpxchg--and not LL/SC--is available. This means that in practice emulating LL/SC with cmpxchg is a viable

[Qemu-devel] [PULL 24/35] target-i386: emulate XCHG using atomic helper

From: "Emilio G. Cota" Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-19-git-send-email-c...@braap.org> Signed-off-by: Richard Henderson --- target-i386/translate.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-)

[Qemu-devel] [PULL 31/35] linux-user: remove handling of ARM's EXCP_STREX

From: "Emilio G. Cota" The exception is not emitted anymore. Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson Message-Id: <1467054136-10430-29-git-send-email-c...@braap.org> ---

[Qemu-devel] [PULL 19/35] target-i386: emulate LOCK'ed INC using atomic helper

From: "Emilio G. Cota" [rth: Merge gen_inc_locked back into gen_inc to share cc update.] Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-14-git-send-email-c...@braap.org> Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 20/35] target-i386: emulate LOCK'ed NOT using atomic helper

From: "Emilio G. Cota" [rth: Avoid qemu_load that's redundant with the atomic op.] Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-15-git-send-email-c...@braap.org> Signed-off-by: Richard Henderson --- target-i386/translate.c | 26

[Qemu-devel] [PULL 28/35] target-arm: emulate LL/SC using cmpxchg helpers

From: "Emilio G. Cota" Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. Portable parallel code, however, is written assuming only cmpxchg--and not LL/SC--is available. This means that in practice emulating LL/SC with cmpxchg is a viable

[Qemu-devel] [PULL 32/35] linux-user: remove handling of aarch64's EXCP_STREX

From: "Emilio G. Cota" The exception is not emitted anymore. Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson Message-Id: <1467054136-10430-30-git-send-email-c...@braap.org> ---

[Qemu-devel] [PULL 18/35] target-i386: emulate LOCK'ed OP instructions using atomic helpers

From: "Emilio G. Cota" [rth: Eliminate some unnecessary temporaries.] Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-13-git-send-email-c...@braap.org> Signed-off-by: Richard Henderson --- target-i386/translate.c | 76

[Qemu-devel] [PULL 10/35] cputlb: Remove includes from softmmu_template.h

We already include exec/address-spaces.h and exec/memory.h in cputlb.c; the include of qemu/timer.h appears to be a fossil. Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- softmmu_template.h |

[Qemu-devel] [PULL 25/35] target-i386: remove helper_lock()

From: "Emilio G. Cota" It's been superseded by the atomic helpers. The use of the atomic helpers provides a significant performance and scalability improvement. Below is the result of running the atomic_add-test microbenchmark with: $ x86_64-linux-user/qemu-x86_64

[Qemu-devel] [PULL 27/35] target-arm: Rearrange aa32 load and store functions

Stop specializing on TARGET_LONG_BITS == 32; unconditionally allocate a temp and expand with tcg_gen_extu_i32_tl. Split out gen_aa32_addr, gen_aa32_frob64, gen_aa32_ld_i32 and gen_aa32_st_i32 as separate interfaces. Reviewed-by: Alex Bennée Signed-off-by: Richard

[Qemu-devel] [PULL 09/35] cputlb: Move probe_write out of softmmu_template.h

Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- cputlb.c | 21 + softmmu_template.h | 23 --- 2 files changed, 21 insertions(+), 23 deletions(-)

[Qemu-devel] [PULL 15/35] tcg: Add CONFIG_ATOMIC64

Allow qemu to build on 32-bit hosts without 64-bit atomic ops. Even if we only allow 32-bit hosts to multi-thread emulate 32-bit guests, we still need some way to handle the 32-bit guest using a 64-bit atomic operation. Do so by dropping back to single-step. Reviewed-by: Emilio G. Cota

[Qemu-devel] [PULL 11/35] cputlb: Move most of iotlb code out of line

Saves 2k code size off of a cold path. Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- cputlb.c | 37 + softmmu_template.h | 52

[Qemu-devel] [PULL 23/35] target-i386: emulate LOCK'ed BTX ops using atomic helpers

From: "Emilio G. Cota" [rth: Avoid redundant qemu_ld in locked case. Fix previously unnoticed incorrect zero-extension of address in register-offset case.] Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-18-git-send-email-c...@braap.org>

[Qemu-devel] [PULL 07/35] linux-user: enable parallel code generation on clone

From: Alex Bennée The variable parallel_cpus controls the generation of thread aware atomic code. We only need to set it once we clone our first thread. At this point any existing translations need to be thrown away. Reviewed-by: Emilio G. Cota

[Qemu-devel] [PULL 22/35] target-i386: emulate LOCK'ed XADD using atomic helper

From: "Emilio G. Cota" [rth: Move load of reg value to common location.] Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-17-git-send-email-c...@braap.org> Signed-off-by: Richard Henderson --- target-i386/translate.c | 15

[Qemu-devel] [PULL 13/35] tcg: Add atomic helpers

Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson

[Qemu-devel] [PULL 03/35] exec: Avoid direct references to Int128 parts

Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- exec.c| 4 ++-- include/qemu/int128.h | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/exec.c

[Qemu-devel] [PULL 08/35] cputlb: Replace SHIFT with DATA_SIZE

Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- cputlb.c | 16 softmmu_template.h | 7 ++- 2 files changed, 10 insertions(+), 13 deletions(-) diff --git

[Qemu-devel] [PULL 21/35] target-i386: emulate LOCK'ed NEG using cmpxchg helper

From: "Emilio G. Cota" [rth: Move redundant qemu_load out of cmpxchg loop.] Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-16-git-send-email-c...@braap.org> Signed-off-by: Richard Henderson --- target-i386/translate.c | 38

[Qemu-devel] [PULL 16/35] tcg: Emit barriers with parallel_cpus

Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 12 +--- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cdd61d6..bb2bfee

[Qemu-devel] [PULL 14/35] tcg: Add atomic128 helpers

Force the use of cmpxchg16b on x86_64. Wikipedia suggests that only very old AMD64 (circa 2004) did not have this instruction. Further, it's required by Windows 8 so no new cpus will ever omit it. If we truely care about these, then we could check this at startup time and then avoid executing

[Qemu-devel] [PULL 05/35] int128: Add int128_make128

Allows Int128 to be used more generally, rather than having to begin with 64-bit inputs and accumulate. Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/int128.h | 20

[Qemu-devel] [PULL 04/35] int128: Use __int128 if available

Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/int128.h | 135 +- tests/test-int128.c | 22 2 files changed, 145

[Qemu-devel] [PULL 00/35] cmpxchg atomic operations

in the git repository at: git://github.com/rth7680/qemu.git tags/pull-atomic-20161022 for you to fetch changes up to 278c5beb29ef8b6747a7c9bde403e9fe90cdad9c: target-alpha: Emulate LL/SC using cmpxchg helpers (2016-10-20 11:00:46 -0700

[Qemu-devel] [PULL 01/35] atomics: add atomic_xor

From: "Emilio G. Cota" This paves the way for upcoming work. Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson Message-Id: <1467054136-10430-8-git-send-email-c...@braap.org> ---

[Qemu-devel] [PULL 02/35] atomics: add atomic_op_fetch variants

From: "Emilio G. Cota" This paves the way for upcoming work. Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson Message-Id: <1467054136-10430-9-git-send-email-c...@braap.org> ---

[Qemu-devel] [PULL 12/35] cputlb: Tidy some macros

TGT_LE and TGT_BE are not size dependent and do not need to be redefined. The others are no longer used at all. Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- cputlb.c | 8

Re: [Qemu-devel] [RFC PATCH] memory: Don't use memcpy for ram marked as skip_dump

On Sat, 22 Oct 2016 11:10:59 +0200 Thorsten Kohfeldt wrote: > Hi *, > > this came to my mind when browsing the sources in the patch's vicinity. > > It is just a collection of thoughts, so please don't feel offended > about how I phrased certain statements. > > >

[Qemu-devel] [V7 1/1] fsdev: add IO throttle support to fsdev devices

Signed-off-by: Pradeep Jagadeesh --- fsdev/Makefile.objs | 1 + fsdev/file-op-9p.h | 3 + fsdev/qemu-fsdev-opts.c | 76 +++ fsdev/qemu-fsdev-throttle.c | 147

Re: [Qemu-devel] [PATCH] block: nvme: correct the nvme queue id check

On 22 October 2016 at 13:09, P J P wrote: > From: Prasad J Pandit > > NVME Express Controller has two queues, submission & completion > queue. When creating a new queue object, 'nvme_create_sq' and > 'nvme_create_cq' routines incorrectly check the

[Qemu-devel] [PATCH] block: nvme: correct the nvme queue id check

From: Prasad J Pandit NVME Express Controller has two queues, submission & completion queue. When creating a new queue object, 'nvme_create_sq' and 'nvme_create_cq' routines incorrectly check the queue id field. It could lead to an OOB access issue. Correct the queue id

[Qemu-devel] [PATCH 38/38] bt: use qemu_chr_alloc()

Use common allocator for CharDriverState. Signed-off-by: Marc-André Lureau --- hw/bt/hci-csr.c | 19 +-- 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/bt/hci-csr.c b/hw/bt/hci-csr.c index bf2deb0..e2c78b8 100644 ---

[Qemu-devel] [PATCH 31/38] char: use a const CharDriver

No need to allocate & copy fileds, let's use static const struct instead. Signed-off-by: Marc-André Lureau --- backends/baum.c | 7 ++-- backends/msmouse.c| 6 ++-- backends/testdev.c| 6 ++-- qemu-char.c | 89

[Qemu-devel] [PATCH 28/38] char: replace avail_connections

No need to count the users of a CharDriverState, it can rely on the fact of whether there is a CharBackend associated or if there is enough space in the muxer. Simplify and fold chr_mux_new_fe() in qemu_chr_fe_init() since there is a single user now. Also switch from fprintf to raising error

[Qemu-devel] [PATCH 37/38] char: allocate CharDriverState as a single object

Use a single allocation for CharDriverState, this avoids extra allocations & pointers, and is a step towards more object-oriented CharDriver. Signed-off-by: Marc-André Lureau --- backends/baum.c | 23 ++--- backends/msmouse.c| 16 +-- backends/testdev.c

[Qemu-devel] [PATCH 36/38] char: use a feature bit for replay

Use a feature flag rather than a structure field for "replay". Signed-off-by: Marc-André Lureau --- qemu-char.c | 33 - include/sysemu/char.h | 3 ++- 2 files changed, 22 insertions(+), 14 deletions(-) diff --git

[Qemu-devel] [PATCH 25/38] char: remove unused CHR_EVENT_FOCUS

Usage has long been removed, since commit f220174de8d9. Signed-off-by: Marc-André Lureau --- hw/usb/ccid-card-passthru.c | 2 -- hw/usb/dev-serial.c | 2 -- include/sysemu/char.h | 1 - 3 files changed, 5 deletions(-) diff --git

[Qemu-devel] [PATCH 20/38] tests: start chardev unit tests

Signed-off-by: Marc-André Lureau --- tests/test-char.c | 253 + tests/Makefile.include | 4 + 2 files changed, 257 insertions(+) create mode 100644 tests/test-char.c diff --git a/tests/test-char.c

[Qemu-devel] [PATCH 35/38] char: introduce generic qemu_chr_get_kind()

This allows to remove the "is_mux" field from CharDriverState. Signed-off-by: Marc-André Lureau --- monitor.c | 2 +- qemu-char.c | 19 +-- include/sysemu/char.h | 15 +-- 3 files changed, 23 insertions(+), 13

[Qemu-devel] [PATCH 30/38] char: remove explicit_be_open from CharDriverState

It's only used in qmp_chardev_add(), so use a create() argument instead. Also switched to typedef functions for CharDriverParse/CharDriverCreate. Signed-off-by: Marc-André Lureau --- backends/baum.c | 1 + backends/msmouse.c| 3 ++- backends/testdev.c

[Qemu-devel] [PATCH 18/38] char: replace qemu_chr_claim/release with qemu_chr_fe_init/deinit

Now that all front end use qemu_chr_fe_init(), we can move chardev claiming in init(), and add a function deinit() to release the chardev and cleanup handlers. The qemu_chr_fe_claim_no_fail() for property are gone, since the property will raise an error instead. In other cases, where there is

[Qemu-devel] [PATCH 13/38] char: rename some frontend functions

qemu_chr_accept_input() and qemu_chr_disconnect() are only used by frontend, so use qemu_chr_fe prefix. Signed-off-by: Marc-André Lureau --- hw/char/bcm2835_aux.c | 2 +- hw/char/cadence_uart.c| 4 ++-- hw/char/escc.c| 2 +- hw/char/imx_serial.c

[Qemu-devel] [PATCH 29/38] char: use common error path in qmp_chardev_add

Signed-off-by: Marc-André Lureau --- qemu-char.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/qemu-char.c b/qemu-char.c index f386dcd..2408e97 100644 --- a/qemu-char.c +++ b/qemu-char.c @@ -4751,8 +4751,7 @@ ChardevReturn

[Qemu-devel] [PATCH 11/38] char: replace PROP_CHR with CharBackend

Store the property in a CharBackend instead of CharDriverState*. This also replace systematically chr by chr.chr to access the CharDriverState*. The following patches will replace it with calls to qemu_chr_fe CharBackend functions. Signed-off-by: Marc-André Lureau

[Qemu-devel] [PATCH 23/38] char: remove explicit_fe_open, use a set_handlers argument

No need to keep explicit_fe_open around if it affects only a qemu_chr_fe_set_handlers(). Use an additional argument instead. Signed-off-by: Marc-André Lureau --- backends/rng-egd.c | 2 +- gdbstub.c | 2 +- hw/arm/pxa2xx.c |

[Qemu-devel] [PATCH 34/38] char: fold single-user functions in caller

This shorten a bit the code. Signed-off-by: Marc-André Lureau --- qemu-char.c | 100 +--- 1 file changed, 34 insertions(+), 66 deletions(-) diff --git a/qemu-char.c b/qemu-char.c index a52e0ba..735a518 100644

[Qemu-devel] [PATCH 09/38] char: introduce CharBackend

This new structure is meant to keep the details associated with a char driver usage. On initialization, it gets a tag from the mux backend. It can change its handlers thanks to qemu_chr_fe_set_handlers(). This structure is introduced so that all frontend will be moved to hold and use a

[Qemu-devel] [PATCH 26/38] char: use an enum for CHR_EVENT

This may help to catch unhandled cases, and avoid having to maintain numbering. Signed-off-by: Marc-André Lureau --- include/sysemu/char.h | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/include/sysemu/char.h b/include/sysemu/char.h

[Qemu-devel] [PATCH 15/38] char: use qemu_chr_fe* functions with CharBackend argument

This also switches from qemu_chr_add_handlers() to qemu_chr_fe_set_handlers(). Note that qemu_chr_fe_set_handlers() now takes the focus when fe_open (qemu_chr_add_handlers() did take the focus) Signed-off-by: Marc-André Lureau --- backends/rng-egd.c | 13

[Qemu-devel] [PATCH 33/38] char: move callbacks in CharDriver

This makes the code more declarative, and avoids to duplicate the information on all instances. Signed-off-by: Marc-André Lureau --- backends/baum.c | 13 +- backends/msmouse.c| 14 +- backends/testdev.c| 10 +- gdbstub.c | 7 +-

[Qemu-devel] [PATCH 07/38] xilinx: fix buffer overflow on realize

ASAN complains about buffer overflow when running: aarch64-softmmu/qemu-system-aarch64 -machine xilinx-zynq-a9 ==476==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60235e38 at pc 0x00f75253 bp 0x7ffc597e0ec0 sp 0x7ffc597e0eb0 READ of size 8 at 0x60235e38 thread T0 #0

[Qemu-devel] [PATCH 24/38] char: move fe_open in CharBackend

The fe_open state belongs to front end. Signed-off-by: Marc-André Lureau --- qemu-char.c | 7 --- include/sysemu/char.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/qemu-char.c b/qemu-char.c index e52c3af..81a593b 100644 ---

[Qemu-devel] [PATCH 17/38] vhost-user: only initialize queue 0 CharBackend

All the queues share the same chardev. Initialize only the first queue CharBackend, and pass it to other queues. This will allow to claim the chardev only once in a later change. Signed-off-by: Marc-André Lureau --- net/vhost-user.c | 29

[Qemu-devel] [PATCH 32/38] char: use a static array for backends

Number and kinds of backends is known at compile-time, use a fixed-sized static array to simplify iterations & lookups. Signed-off-by: Marc-André Lureau --- backends/baum.c | 2 +- backends/msmouse.c| 2 +- backends/testdev.c| 2 +- qemu-char.c

[Qemu-devel] [PATCH 05/38] malta: replace chr init by CHR_EVENT_OPENED handler

The CharDriverState.init() callback was introduced in commit ceecf1d158. It is only called from text_console_do_init(), but it is no longer set since commit a61ae7f88 (init assignment has been removed by accident). It seems correct to use an event callback instead and print the console text on

[Qemu-devel] [PATCH 19/38] char: make some qemu_chr_fe skip if no driver

In most cases, front ends do not care about the side effect of CharBackend, so we can simply skip the checks and call the qemu_chr_fe functions even without associated CharDriver. Signed-off-by: Marc-André Lureau --- hw/arm/pxa2xx.c | 8 +++-

[Qemu-devel] [PATCH 16/38] char: fold qemu_chr_set_handlers in qemu_chr_fe_set_handlers

qemu_chr_add_handlers*() have been removed in previous change, so the common qemu_chr_set_handlers() is no longer needed. Signed-off-by: Marc-André Lureau --- qemu-char.c | 78 ++- include/sysemu/char.h | 3

[Qemu-devel] [PATCH 27/38] char: remove unused qemu_chr_fe_event

I introduced this function in d61b0c9a2f7f, but it isn't used. Furthermore, it was incomplete, as it would need to translate QEMU chr events to Spice port events. (presumably it was used in the follow-up NBD-spice series that was not completed:

[Qemu-devel] [PATCH 04/38] sun4uv: fix serial initialization regression

Since commit b6607a1a204d, serial_hds_isa_init() was introduced to factor out serial_isa_init() loops. However, sun4uv shouldn't start from 0 when there is a mm serial on 0 already. Add a "from" argument to serial_hds_isa_init(). Signed-off-by: Marc-André Lureau ---

[Qemu-devel] [PATCH 10/38] char: start converting mux driver to use CharBackend

Start using qemu_chr_fe* CharBackend functions: initialize a CharBackend and use qemu_chr_fe_set_handlers(). Signed-off-by: Marc-André Lureau --- qemu-char.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/qemu-char.c

[Qemu-devel] [PATCH 08/38] mux: split mux_chr_update_read_handler()

Make qemu_chr_add_handlers_full() aware of mux handling. This allows introduction of a tag associated with the fe handlers and a qemu_chr_set_handlers() function to set the handler for a particular tag. That will allow to get rid of qemu_chr_add_handlers*() in later changes, in favor of

[Qemu-devel] [PATCH 03/38] ringbuf: fix chr_write return value

It should return the number of written bytes. Signed-off-by: Marc-André Lureau --- qemu-char.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu-char.c b/qemu-char.c index 9165051..650943d 100644 --- a/qemu-char.c +++ b/qemu-char.c @@ -3328,7

[Qemu-devel] [PATCH 22/38] char: rename chr_close/chr_free

The function is used to free the backend opaque pointer, let's name it accordingly. Signed-off-by: Marc-André Lureau --- backends/baum.c | 4 ++-- backends/msmouse.c| 4 ++-- backends/testdev.c| 4 ++-- qemu-char.c | 58

[Qemu-devel] [PATCH 01/38] rng: remove unused included header

DEFINE_PROP_CHR is not used (rng is not of TYPE_DEVICE) Signed-off-by: Marc-André Lureau --- backends/rng-egd.c | 1 - 1 file changed, 1 deletion(-) diff --git a/backends/rng-egd.c b/backends/rng-egd.c index ba17c07..0f6d0af 100644 --- a/backends/rng-egd.c +++

[Qemu-devel] [PATCH 02/38] char: remove use-after-free on win-stdio

Found by reviewing the code, win_stdio_close() is called by qemu_chr_free() which then call qemu_chr_free_common() taking care of freeing CharDriverState*. Signed-off-by: Marc-André Lureau --- qemu-char.c | 1 - 1 file changed, 1 deletion(-) diff --git

[Qemu-devel] [PATCH 06/38] char: remove init callback

The CharDriverState.init() callback is no longer set since commit a61ae7f88ce and thus unused. The only user, the malta FGPA display has been converted to use an event "opened" callback instead. Signed-off-by: Marc-André Lureau --- gdbstub.c | 2 +-

[Qemu-devel] [PATCH 21/38] char: move front end handlers in CharBackend

Since the hanlders are associated with a CharBackend, rather than the CharDriverState, it is more appropriate to store in CharBackend. This avoids the handler copy dance in qemu_chr_fe_set_handlers() then mux_chr_update_read_handler(), by storing the CharBackend pointer directly. Also a mux

[Qemu-devel] [PATCH v5 17/17] ppc/pnv: Add Naples chip support for LPC interrupts

From: Benjamin Herrenschmidt It adds the Naples chip which supports proper LPC interrupts via the LPC controller rather than via an external CPLD. Signed-off-by: Benjamin Herrenschmidt [clg: - updated for qemu-2.7 - ported on latest

[Qemu-devel] [PATCH 00/38] char: fixes and improvements (was "[PATCH 0/9] Fix mux regression")

Hi, This is a followup of the series "[PATCH 0/9] Fix mux regression (commit 949055a2)". Paolo suggested a new API for qemu_chr_fe_* taking a new CharBackend* structure as argument, and modifying properties to hold such structure. I followed his advise in the series, and it turns out to bring

[Qemu-devel] [PATCH v5 11/17] ppc/xics: Add "native" XICS subclass

This provides access to the MMIO based Interrupt Presentation Controllers (ICP) as found on a POWER8 system. A new XICSNative class is introduced to hold the MMIO region of the ICPs. Each thread of the system has a subregion, indexed by its PIR number, holding a XIVE (External Interrupt Vector

[Qemu-devel] [PATCH 14/38] colo: claim in find_and_check_chardev

This factors out claiming of chardev, and changes the call to non-fatal to return an error like the rest of the chardev checks. Signed-off-by: Marc-André Lureau --- net/colo-compare.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git

[Qemu-devel] [PATCH v5 16/17] ppc/pnv: Add OCC model stub with interrupt support

From: Benjamin Herrenschmidt The OCC is an on-chip microcontroller based on a ppc405 core used for various power management tasks. It comes with a pile of additional hardware sitting on the PIB (aka XSCOM bus). At this point we don't emulate it (nor plan to do so).

[Qemu-devel] [PATCH v5 15/17] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt

From: Benjamin Herrenschmidt The PSI (Processor Service Interface) is one of the engines of the "Bridge" unit which connects the different interfaces to the Power Processor. This adds just enough of the PSI bridge to handle various on-chip and the one external

[Qemu-devel] [PATCH v5 09/17] ppc/pnv: add a LPC controller

From: Benjamin Herrenschmidt The LPC (Low Pin Count) interface on a POWER8 is made accessible to the system through the ADU (XSCOM interface). This interface is part of set of units connected together via a local OPB (On-Chip Peripheral Bus) which act as a bridge

[Qemu-devel] [PATCH 12/38] char: remaining switch to CharBackend in frontend

Similar to previous change, for the remaining CharDriverState front ends users. Signed-off-by: Marc-André Lureau --- backends/rng-egd.c | 29 ++--- gdbstub.c | 22 +++ hw/arm/omap2.c | 11 +-

[Qemu-devel] [PATCH v5 14/17] ppc/xics: introduce a helper to insert a new ics

Interrupt Control Sources (ICS) are now maintained under a list. Signed-off-by: Cédric Le Goater --- hw/intc/xics.c| 6 ++ include/hw/ppc/xics.h | 1 + 2 files changed, 7 insertions(+) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 095c16a30082..f24787e95013

[Qemu-devel] [PATCH v5 12/17] ppc/pnv: add a XICS native to each PowerNV chip

It also links the XICS object to each core as it is needed to do the CPU setup and the ICP MMIO windows are memory mapped for each thread. Signed-off-by: Cédric Le Goater --- Changes since v4: - changed the calculation of the number of ICPs to use smp_threads - added the

[Qemu-devel] [PATCH v5 07/17] ppc/pnv: add XSCOM infrastructure

On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves as a backbone to connect different units of the system. The host firmware connects to the PIB through a bridge unit, the Alter-Display-Unit (ADU), which gives him access to all the chiplets on the PCB network (Pervasive Connect

[Qemu-devel] [PATCH v5 10/17] ppc/pnv: add a ISA bus

As Qemu only supports a single instance of the ISA bus, we use the LPC controller of chip 0 to create one and plug in a couple of useful devices, like an UART and RTC. An IPMI BT device, which is also an ISA device, can be defined on the command line to connect an external BMC. That is for later.

[Qemu-devel] [PATCH v5 13/17] ppc/xics: add a xics_get_cpu_index_by_pir helper

We will need this helper to translate the server number of the XIVE (which is a PIR) into an ICPState index number (which is a cpu index). Signed-off-by: Cédric Le Goater --- hw/intc/xics_native.c | 19 +++ include/hw/ppc/xics.h | 1 + 2 files changed, 20

[Qemu-devel] [PATCH v5 06/17] ppc/pnv: add a PnvCore object

This is largy inspired by sPAPRCPUCore with some simplification, no hotplug for instance. A set of PnvCore objects is added to the PnvChip and the device tree is populated looping on these cores. Real HW cpu ids are now generated depending on the chip cpu model, the chip id and a core mask. The

[Qemu-devel] [PATCH v5 05/17] ppc/pnv: add a PIR handler to PnvChip

The Processor Identification Register (PIR) is a register that holds a processor identifier which is used for bus transactions (XSCOM) and for processor differentiation in multiprocessor systems. It also used in the interrupt vector entries (IVE) to identify the thread serving the interrupts. P9

[Qemu-devel] [PATCH v5 03/17] ppc/pnv: add a PnvChip object

This is is an abstraction of a POWER8 chip which is a set of cores plus other 'units', like the pervasive unit, the interrupt controller, the memory controller, the on-chip microcontroller, etc. The whole can be seen as a socket. It depends on a cpu model and its characteristics: max cores and

[Qemu-devel] [PATCH v5 04/17] ppc/pnv: add a core mask to PnvChip

This will be used to build real HW ids for the cores and enforce some limits on the available cores per chip. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson --- Changes since v4 : - removed setting of 'cores-mask' property. -global can

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