Re: [Qemu-devel] [Qemu-trivial] [PATCH] cadence_uart: Check if receiver timeout counter is disabled

I CC: Xilinx Zynq Maintainers. Laurent On 07/12/2016 22:12, Andrew Gacek wrote: > When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to > 0, the receiver timeout counter should be disabled. See page 1801 of > "Zynq-7000 AP SoC Technical Reference Manual". This commit adds a > such

Re: [Qemu-devel] test-qga failures on Fedora 24

Hi - Original Message - > On 7 July 2016 at 00:02, Michael Roth wrote: > > Quoting John Snow (2016-07-06 17:41:32) > >> > >> > >> On 07/06/2016 06:20 PM, Michael Roth wrote: > >> > Quoting Marc-André Lureau (2016-07-06 16:40:52) > >> >>> Here's the meat of it:

[Qemu-devel] [Bug 1579306] Re: usb-uas does not work in Windows (10) guest

I am also facing this issue. On further probing, I found out that usb-uas in Qemu doesn't support "SET_SEL" control command due to which windows driver "uaspstor.sys" couldn't complete the enumeration. It is clearly mentioned in USB 3.1 specs that uasp devices should handle two new control

Re: [Qemu-devel] [PATCH 04/14] qemu-img: Set "share-rw" flag in read-only commands

On Fri, 12/02 01:52, Max Reitz wrote: > > diff --git a/qemu-img.c b/qemu-img.c > > index afcd51f..b2f4077 100644 > > --- a/qemu-img.c > > +++ b/qemu-img.c > > @@ -679,6 +679,10 @@ static int img_check(int argc, char **argv) > > break; > > } > > } > > + > > +if

Re: [Qemu-devel] [PATCH v3] doc: Add NBD_CMD_BLOCK_STATUS extension

08.12.2016 06:39, Alex Bligh wrote: [...] are vendor dependent extensions. The 'BASE' namespace represents metadata contexts defined within this document. Other namespaces may be registered by reference within this document. +The "BASE:allocation" Backticks: `BASE:allocation` An idea:

Re: [Qemu-devel] [PATCH 01/14] osdep: Add qemu_lock_fd and qemu_unlock_fd

On Fri, 12/02 01:30, Max Reitz wrote: > On 31.10.2016 16:38, Fam Zheng wrote: > > They are wrappers of POSIX fcntl "file private locking". > > > > Signed-off-by: Fam Zheng > > --- > > include/qemu/osdep.h | 2 ++ > > util/osdep.c | 29 + > >

Re: [Qemu-devel] [PATCH v7 0/5] IOMMU: intel_iommu support map and unmap notifications

On 2016年12月08日 10:39, Peter Xu wrote: > Btw, do you have time to help review my RFC series for "vt-d replay"? > :) I'd like to receive any further review comments besides the issues > mentioned above since IMHO they can be seperated from current series, > I have noted them down in my pending list.

Re: [Qemu-devel] [PATCH] migration: re-active images when migration fails to complete

Hi， On 2016/12/6 23:24, Dr. David Alan Gilbert wrote: * Kevin Wolf (kw...@redhat.com) wrote: Am 19.11.2016 um 12:43 hat zhanghailiang geschrieben: commit fe904ea8242cbae2d7e69c052c754b8f5f1ba1d6 fixed a case which migration aborted QEMU because it didn't regain the control of images while

[Qemu-devel] [PATCH v6 2/2] crypto: add virtio-crypto driver

This patch introduces virtio-crypto driver for Linux Kernel. The virtio crypto device is a virtual cryptography device as well as a kind of virtual hardware accelerator for virtual machines. The encryption anddecryption requests are placed in the data queue and are ultimately handled by

[Qemu-devel] [PATCH v6 0/2] virtio-crypto: add Linux driver

v6: - add patch 1/2 to make sparc architecture happy. [Sam] - close created sessions previousely when rekeying. - convert the priority of virtio crypto algs from 4001 to 501 which is enough. v5: - add comments for algs_lock and table_lock. [Stefan] - use kzfree instead of kfree for key

[Qemu-devel] [PATCH v6 1/2] sparc: fix a building error reported by kbuild

>> arch/sparc/include/asm/topology_64.h:44:44: error: implicit declaration of function 'cpu_data' [-Werror=implicit-function-declaration] #define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id) ^ Let's include cpudata.h in topology_64.h.

Re: [Qemu-devel] [PATCH v3] doc: Add NBD_CMD_BLOCK_STATUS extension

> On 2 Dec 2016, at 18:45, Alex Bligh wrote: > > Thanks. That makes sense - or enough sense for me to carry on commenting! I finally had some time to go through this extension in detail. Rather than comment on all the individual patches, I squashed them into a single commit,

Re: [Qemu-devel] [RFC PATCH 11/13] intel_iommu: provide its own replay() callback

On 2016年12月06日 18:36, Peter Xu wrote: > +/** > + * vtd_page_walk - walk specific IOVA range, and call the hook > + * > + * @ce: context entry to walk upon > + * @start: IOVA address to start the walk > + * @end: size of the IOVA range to walk over

[Qemu-devel] [PATCH for-2.9] cryptodev: add 3des-ede support

This patch add 3des-ede support for cryptodev. However this is effective only when backend using libgcrypt/nettle, because cipher-builtin doesn't support 3des-ede yet. Signed-off-by: Longpeng(Mike) --- Changes since v1: - split the original pathset. [Gonglei] ---

Re: [Qemu-devel] [PATCH for-2.9 v2] crypto: add 3des-ede support when using libgcrypt/nettle

> From: longpeng > Sent: Thursday, December 08, 2016 10:33 AM > To: berra...@redhat.com; ebl...@redhat.com; arm...@redhat.com > Cc: Wubin (H); Zhoujian (jay, Euler); Gonglei (Arei); qemu-devel@nongnu.org; > longpeng > Subject: [PATCH for-2.9 v2] crypto: add 3des-ede support when using >

Re: [Qemu-devel] [PATCH v7 0/5] IOMMU: intel_iommu support map and unmap notifications

On Wed, Dec 07, 2016 at 10:04:57PM +0800, Lan Tianyu wrote: [...] > >Even if the context entry is cleared and invalidated, IMHO it does not > >mean that we should be using GPA address space, nor do we need to put > >it into guest physical address space. Instead, it simply means this > >device

[Qemu-devel] [PATCH for-2.9 v2] crypto: add 3des-ede support when using libgcrypt/nettle

Libgcrypt and nettle support 3des-ede, so this patch add 3des-ede support when using libgcrypt or nettle. Signed-off-by: Longpeng(Mike) --- Changes since v1: - rename 3des-ede to 3des. [Daniel] - add (since 2.9) in comment. [Gonglei] - add ctr(3des) testcase.

Re: [Qemu-devel] [PATCH for-2.9 v2] virtio-crypto: zeroize the key material before free

> > From: Eric Blake [mailto:ebl...@redhat.com] > Sent: Wednesday, December 07, 2016 11:22 PM > To: Gonglei (Arei); qemu-devel@nongnu.org > Cc: m...@redhat.com; stefa...@redhat.com > Subject: Re: [PATCH for-2.9 v2] virtio-crypto: zeroize the key material before > free > > On 12/06/2016 08:29 PM,

Re: [Qemu-devel] [PATCH for-2.9 v2] virtio-crypto: zeroize the key material before free

Hi Max, > > On 07.12.2016 03:29, Gonglei wrote: > > Common practice with sensitive information (key material, passwords, > > etc). Prevents sensitive information from being exposed by accident later in > > coredumps, memory disclosure bugs when heap memory is reused, etc. > > > > Sensitive

Re: [Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE

On 2016年12月08日 10:16, Peter Xu wrote: On Thu, Dec 08, 2016 at 10:02:15AM +0800, Jason Wang wrote: On 2016年12月07日 13:52, Peter Xu wrote: Currently vt-d Context Entry (CE) only allows 39/48 bits address width. If guest software configured more than that, we complain and force shrink to the

Re: [Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE

On Thu, Dec 08, 2016 at 10:02:15AM +0800, Jason Wang wrote: > > > On 2016年12月07日 13:52, Peter Xu wrote: > >Currently vt-d Context Entry (CE) only allows 39/48 bits address width. > >If guest software configured more than that, we complain and force > >shrink to the maximum supported, which is

[Qemu-devel] [PATCH v3 5/6] target-ppc: Implement bcdtrunc. instruction

bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the number of bytes to truncate in vra, the return register will have vrb with such bits truncated. Signed-off-by: Jose Ricardo Ziviani --- target-ppc/helper.h | 1 +

[Qemu-devel] [PATCH v3 6/6] target-ppc: Implement bcdutrunc. instruction

bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with unsigned BCD numbers. Signed-off-by: Jose Ricardo Ziviani --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 54 +

[Qemu-devel] [PATCH v3 4/6] target-ppc: Implement bcdsr. instruction

bcdsr.: Decimal shift and round. This instruction works like bcds. however, when performing right shift, 1 will be added to the result if the last digit was >= 5. Signed-off-by: Jose Ricardo Ziviani --- target-ppc/helper.h | 1 +

[Qemu-devel] [PATCH v3 3/6] target-ppc: Implement bcdus. instruction

bcdus.: Decimal unsigned shift. This instruction works like bcds. but considers only unsigned BCDs (no sign in least meaning 4 bits). Signed-off-by: Jose Ricardo Ziviani --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 43

Re: [Qemu-devel] [PATCH v5 1/1] crypto: add virtio-crypto driver

Hi Sam, > > Subject: Re: [PATCH v5 1/1] crypto: add virtio-crypto driver > > On Mon, Dec 05, 2016 at 03:12:52AM +, Gonglei (Arei) wrote: > > I don't think the root cause of those warnings are introduced by > > virtio-crypto > driver. > > > > What's your opinion? Sam and David? > > Root

[Qemu-devel] [PATCH v3 2/6] target-ppc: Implement bcds. instruction

bcds.: Decimal shift. Given two registers vra and vrb, this instruction shift the vrb value by vra bits into the result register. Signed-off-by: Jose Ricardo Ziviani --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 38

[Qemu-devel] [PATCH v3 1/6] target-ppc: Implement unsigned quadword left/right shift and unit tests

This commit implements functions to right and left shifts and the unittest for them. Such functions is needed due to instructions that requires them. Today, there is already a right shift implementation in int128.h but it's designed for signed numbers. Signed-off-by: Jose Ricardo Ziviani

[Qemu-devel] [PATCH v3 0/6] POWER9 TCG enablements - BCD functions - final part

v3: - moves shift functions to host-utils.c and added config_int128 guard - changes Makefile to always compile host-utils.c - redesigns bcd[u]trunc to use bitwise operations - removes "target-ppc: Implement bcd_is_valid function" (merged) v2: - bcd[s,sr,us] uses 1 byte for shifting instead

Re: [Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE

On 2016年12月07日 13:52, Peter Xu wrote: Currently vt-d Context Entry (CE) only allows 39/48 bits address width. If guest software configured more than that, we complain and force shrink to the maximum supported, which is 48bits. Signed-off-by: Peter Xu ---

Re: [Qemu-devel] [PATCH v5 1/1] crypto: add virtio-crypto driver

> > Subject: Re: [PATCH v5 1/1] crypto: add virtio-crypto driver > > On Tue, Dec 06, 2016 at 09:01:49AM +, Gonglei (Arei) wrote: > > > > Would you please review and/or ack the virtio_crypto_algs.c? > > It is the realization of specified algs based on Linux Crypto Framework. > > I have no

Re: [Qemu-devel] [PATCH for-2.9 2/2] intel_iommu: extend supported guest aw to 48 bits

On 2016年12月07日 13:52, Peter Xu wrote: Previously vt-d codes only supports 39 bits iova address width. It won't be hard to extend it to 48 bits. After enabling this, we should be able to map larger iova addresses. To check whether 48 bits aw is enabled, we can grep in the guest dmesg with

Re: [Qemu-devel] qemu -netdev tun/tap support can't handle macvtap type devices

On 2016年12月07日 22:24, Daniel P. Berrange wrote: On Wed, Dec 07, 2016 at 02:21:24PM +, Peter Maydell wrote: On 7 December 2016 at 14:07, Daniel P. Berrange wrote: On Wed, Dec 07, 2016 at 12:30:31PM +, Peter Maydell wrote: On 7 December 2016 at 12:04, Daniel P.

Re: [Qemu-devel] qemu -netdev tun/tap support can't handle macvtap type devices

On 2016年12月07日 22:32, Peter Maydell wrote: On 7 December 2016 at 14:24, Daniel P. Berrange wrote: On Wed, Dec 07, 2016 at 02:21:24PM +, Peter Maydell wrote: On 7 December 2016 at 14:07, Daniel P. Berrange wrote: On Wed, Dec 07, 2016 at

Re: [Qemu-devel] [Qemu-trivial] [PATCH for-2.9] docs: Fix description of the sentence

On 12/07/2016 09:30 PM, Stefan Hajnoczi wrote: On Wed, Dec 07, 2016 at 10:01:49AM +0100, Laurent Vivier wrote: Le 07/12/2016 à 09:58, Zhang Chen a écrit : On 12/02/2016 03:57 PM, Laurent Vivier wrote: On 02/12/2016 03:59, Zhang Chen wrote: On 12/01/2016 10:57 PM, Eric Blake wrote: On

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 2/7] target-ppc: Implement unsigned quadword left/right shift and unit tests

On Wed, Dec 07, 2016 at 04:41:53PM +1100, David Gibson wrote: > On Tue, Dec 06, 2016 at 05:40:05PM -0200, Jose Ricardo Ziviani wrote: > > This commit implements functions to right and left shifts and the > > unittest for them. Such functions is needed due to instructions > > that requires them. >

[Qemu-devel] QEMU Advent Calendar

Dear Thomas, Dear Kashyap, dear QEMU developers, What a wonderful idea! Thank you. Considered http://aros.sourceforge.net/ or some of its distributions? Thanks, -- Martin

Re: [Qemu-devel] [PATCH 08/21] block: introduce auto-loading bitmaps

On 11/22/2016 12:26 PM, Vladimir Sementsov-Ogievskiy wrote: > Auto loading bitmaps are bitmaps store in the disk image, which should > be loaded when the image is opened and become BdrvDirtyBitmaps for the > corresponding drive. > > Signed-off-by: Vladimir Sementsov-Ogievskiy

Re: [Qemu-devel] [PATCH 3/3] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU

On Tue, Dec 06, 2016 at 05:46:19PM +, Peter Maydell wrote: > The GICv3 requires that we only signal Pending interrupts to > the CPU. This category does not include Pending+Active interrupts, > which means we need to check whether the interrupt is Active in > the gicr_int_pending() and

[Qemu-devel] [QEMU PATCH v15 4/4] migration: add error_report

Added error_report where version_ids do not match in vmstate_load_state. Signed-off-by: Jianjun Duan --- migration/vmstate.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/migration/vmstate.c b/migration/vmstate.c index 2f9d4ba..8ddd230 100644 ---

[Qemu-devel] [QEMU PATCH v15 2/4] migration: migrate QTAILQ

Currently we cannot directly transfer a QTAILQ instance because of the limitation in the migration code. Here we introduce an approach to transfer such structures. We created VMStateInfo vmstate_info_qtailq for QTAILQ. Similar VMStateInfo can be created for other data structures such as list.

[Qemu-devel] [QEMU PATCH v15 3/4] tests/migration: Add test for QTAILQ migration

Add a test for QTAILQ migration to tests/test-vmstate.c. Signed-off-by: Jianjun Duan --- tests/test-vmstate.c | 160 +++ 1 file changed, 160 insertions(+) diff --git a/tests/test-vmstate.c b/tests/test-vmstate.c index

[Qemu-devel] [QEMU PATCH v15 1/4] migration: extend VMStateInfo

Current migration code cannot handle some data structures such as QTAILQ in qemu/queue.h. Here we extend the signatures of put/get in VMStateInfo so that customized handling is supported. put now will return int type. Signed-off-by: Jianjun Duan ---

[Qemu-devel] [QEMU PATCH v15 0/4] migration: migrate QTAILQ

I addressed some review comments. Comments are welcome. v15: - Improved error messages. Previous versions are: v14: - Fixed a return statement. (link: http://lists.nongnu.org/archive/html/qemu-devel/2016-11/msg04467.html) v13: - Changed some QTAILQ related macro names to match

[Qemu-devel] [Bug 538808] Re: qemu-system-x86_64 0.12.2 crashes with -m 967 under Windows

I think that QEMU did not crash, but simply was not able to allocate the block of memory which was requested. This is an inherent problem of the fragmented memory of 32 bit applications on Windows. QEMU reports problems with memory allocation, but QEMU for Windows tries to send those messages to

[Qemu-devel] [PATCH] cadence_uart: Check if receiver timeout counter is disabled

When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to 0, the receiver timeout counter should be disabled. See page 1801 of "Zynq-7000 AP SoC Technical Reference Manual". This commit adds a such a check before setting the receive timeout interrupt. Signed-off-by: Andrew Gacek

Re: [Qemu-devel] [PATCH v5 1/1] crypto: add virtio-crypto driver

On Mon, Dec 05, 2016 at 03:12:52AM +, Gonglei (Arei) wrote: > I don't think the root cause of those warnings are introduced by > virtio-crypto driver. > > What's your opinion? Sam and David? Root cause here is that arch/sparc/include/asm/topology_64.h references cpu_data without including

Re: [Qemu-devel] [PATCH 1/3] target-arm: Log AArch64 exception returns

On Tue, Dec 06, 2016 at 05:46:17PM +, Peter Maydell wrote: > We already log exception entry; add logging of the AArch64 exception > return path as well. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- >

Re: [Qemu-devel] [PATCH 2/3] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset

On Tue, Dec 06, 2016 at 05:46:18PM +, Peter Maydell wrote: > In the ARMCPRegInfo definitions for the GICv3 CPU interface > registers, we were trying to use .fieldoffset to specify > the locations of data fields within the GICv3CPUState struct. > This is completely broken, because .fieldoffset

Re: [Qemu-devel] [QEMU PATCH v14 3/4] tests/migration: Add test for QTAILQ migration

On 12/07/2016 11:49 AM, Dr. David Alan Gilbert wrote: > * Jianjun Duan (du...@linux.vnet.ibm.com) wrote: >> Add a test for QTAILQ migration to tests/test-vmstate.c. > > Yes, but see comment below if you have to respin: > >> Signed-off-by: Jianjun Duan >> --- >>

Re: [Qemu-devel] [PATCH 11/21] block: introduce persistent dirty bitmaps

On 22.11.2016 18:26, Vladimir Sementsov-Ogievskiy wrote: > New field BdrvDirtyBitmap.persistent means, that bitmap should be saved > on bdrv_close, using format driver. Format driver should maintain bitmap > storing. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > ---

Re: [Qemu-devel] Slow qemu guest performance after host is resumed from suspended state

Following Stefan's suggestion I've investigated the possibility of potential problems with interrupts. Unfortunately, I can see no differences between both scenarios regarding the interrupt counter growth (c.f. https://evonide.com/images/qemu_proc_interrupts.png). After a short conversation with

Re: [Qemu-devel] [PATCH 09/21] qcow2: add .bdrv_load_autoloading_dirty_bitmaps

On 22.11.2016 18:26, Vladimir Sementsov-Ogievskiy wrote: > Auto loading bitmaps are bitmaps in Qcow2, with the AUTO flag set. They > are loaded when the image is opened and become BdrvDirtyBitmaps for the > corresponding drive. > > Extra data in bitmaps is not supported for now. > >

[Qemu-devel] [Bug 538808] Re: qemu-system-x86_64 0.12.2 crashes with -m 967 under Windows

Can you still reproduce this problem with the latest version of QEMU? ** Changed in: qemu Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/538808 Title:

[Qemu-devel] [Bug 584516] Re: opensuse 11.2 guest hangs after live migration with clocksource=kvm-clock

This bug ticket is quite old already ... can you still reproduce this issue with the latest version of QEMU? ** Changed in: qemu Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

Re: [Qemu-devel] [PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration

On Wed, Dec 07, 2016 at 11:54:34AM -0800, Dave Hansen wrote: > We're talking about a bunch of different stuff which is all being > conflated. There are 3 issues here that I can see. I'll attempt to > summarize what I think is going on: > > 1. Current patches do a hypercall for each order in the

[Qemu-devel] [Bug 498417] Re: cache=writeback on disk image doesn't do write-back

QEMU 0.11 / 0.12 is pretty much outdated nowadays ... can you still reproduce this issue with the latest version of QEMU? ** Changed in: qemu Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

[Qemu-devel] [Bug 584146] Re: Virtual fat breaks with -snapshot

Can you still reproduce this issue with the latest version of QEMU? If so, could you please provide a proper command line that triggers this problem? ** Changed in: qemu Status: Confirmed => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml,

Re: [Qemu-devel] [QEMU PATCH v14 0/4] migration: migrate QTAILQ

* Jianjun Duan (du...@linux.vnet.ibm.com) wrote: > ping Yes, hopefully this can go in right near the start of 2.9 Dave > > On 11/23/2016 09:53 AM, Jianjun Duan wrote: > > Hi all, > > > > I addressed some review comments. Comments are welcome. > > > > v14: - Fixed a return statement.

Re: [Qemu-devel] [PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration

We're talking about a bunch of different stuff which is all being conflated. There are 3 issues here that I can see. I'll attempt to summarize what I think is going on: 1. Current patches do a hypercall for each order in the allocator. This is inefficient, but independent from the underlying

Re: [Qemu-devel] [QEMU PATCH v14 4/4] migration: add error_report

* Jianjun Duan (du...@linux.vnet.ibm.com) wrote: > Added error_report where version_ids do not match in vmstate_load_state. > > Signed-off-by: Jianjun Duan Yes, but the error message would be better if it printed the two version numbers so you could see what went

Re: [Qemu-devel] [QEMU PATCH v14 3/4] tests/migration: Add test for QTAILQ migration

* Jianjun Duan (du...@linux.vnet.ibm.com) wrote: > Add a test for QTAILQ migration to tests/test-vmstate.c. > > Signed-off-by: Jianjun Duan oops, follow up to my previous mail, I meant to add: Reviewed-by: Dr. David Alan Gilbert > --- >

Re: [Qemu-devel] [QEMU PATCH v14 3/4] tests/migration: Add test for QTAILQ migration

* Jianjun Duan (du...@linux.vnet.ibm.com) wrote: > Add a test for QTAILQ migration to tests/test-vmstate.c. Yes, but see comment below if you have to respin: > Signed-off-by: Jianjun Duan > --- > tests/test-vmstate.c | 160 >

Re: [Qemu-devel] [PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration

On Wed, Dec 07, 2016 at 10:44:31AM -0800, Dave Hansen wrote: > On 12/07/2016 10:38 AM, Andrea Arcangeli wrote: > >> > and leaves room for the bitmap size to be encoded as well, if we decide > >> > we need a bitmap in the future. > > How would a bitmap ever be useful with very large page-order? >

Re: [Qemu-devel] Slow qemu guest performance after host is resumed from suspended state

On Sun, Dec 4, 2016 at 10:52 PM, Ruslan Habalov <3v0n...@gmail.com> wrote: > Hi everyone, > > I'm having the following qemu issue since about February on Xubuntu. > > Steps to reproduce: > 1) Boot host and boot qemu guest - everything works perfect > 2) Shutdown qemu guest > 3) Suspend host and

Re: [Qemu-devel] [PATCH 16/21] qmp: add persistent flag to block-dirty-bitmap-add

On 11/22/2016 11:26 AM, Vladimir Sementsov-Ogievskiy wrote: > Add optional 'persistent' flag to qmp command block-dirty-bitmap-add. > Default is false. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > Signed-off-by: Denis V. Lunev > --- > +++

Re: [Qemu-devel] [PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration

On 12/07/2016 10:38 AM, Andrea Arcangeli wrote: >> > and leaves room for the bitmap size to be encoded as well, if we decide >> > we need a bitmap in the future. > How would a bitmap ever be useful with very large page-order? Please, guys. Read the patches. *Please*. The current code doesn't

[Qemu-devel] [PATCH v1 9/9] target-ppc: Add xxperm and xxpermr instructions

From: Bharata B Rao xxperm: VSX Vector Permute xxpermr: VSX Vector Permute Right-indexed Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania --- target-ppc/fpu_helper.c | 23

[Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction

xscpsgnqp: VSX Scalar Copy Sign Quad-Precision Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson --- target-ppc/translate/vsx-impl.inc.c | 12 +++- target-ppc/translate/vsx-ops.inc.c | 1 + 2 files changed, 12 insertions(+),

Re: [Qemu-devel] [PATCH 08/21] block: introduce auto-loading bitmaps

On 22.11.2016 18:26, Vladimir Sementsov-Ogievskiy wrote: > Auto loading bitmaps are bitmaps store in the disk image, which should s/store/stored/ > be loaded when the image is opened and become BdrvDirtyBitmaps for the > corresponding drive. > > Signed-off-by: Vladimir Sementsov-Ogievskiy

Re: [Qemu-devel] [PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration

Hello, On Wed, Dec 07, 2016 at 08:57:01AM -0800, Dave Hansen wrote: > It is more space-efficient. We're fitting the order into 6 bits, which > would allows the full 2^64 address space to be represented in one entry, Very large order is the same as very large len, 6 bits of order or 8 bytes of

[Qemu-devel] [PATCH v1 6/9] target-ppc: implement xxinsertw instruction

xxinsertw: VSX Vector Insert Word Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 30 ++

[Qemu-devel] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction

xxextractuw: VSX Vector Extract Unsigned Word Signed-off-by: Nikunj A Dadhania --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 31 +++ target-ppc/translate/vsx-impl.inc.c | 27

[Qemu-devel] [PATCH v1 4/9] target-ppc: implement stxvll instructions

stxvll: Store VSX Vector Left-justified with Length Vector (8-bit elements) in LE/BE: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ Storing 14 bytes

Re: [Qemu-devel] [PATCH 07/21] qcow2: add bitmaps extension

On 22.11.2016 18:26, Vladimir Sementsov-Ogievskiy wrote: > Add bitmap extension as specified in docs/specs/qcow2.txt. > For now, just mirror extension header into Qcow2 state and check > constraints. > > For now, disable image resize if it has bitmaps. It will be fixed later. > > Signed-off-by:

[Qemu-devel] [PATCH v1 3/9] target-ppc: implement stxvl instruction

stxvl: Store VSX Vector with Length Vector (8-bit elements) in BE: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ Vector (8-bit elements) in LE:

[Qemu-devel] [PATCH v1 7/9] target-ppc: implement xsnegqp instruction

xsnegqp: VSX Scalar Negate Quad-Precision Signed-off-by: Nikunj A Dadhania --- target-ppc/translate/vsx-impl.inc.c | 4 target-ppc/translate/vsx-ops.inc.c | 1 + 2 files changed, 5 insertions(+) diff --git a/target-ppc/translate/vsx-impl.inc.c

[Qemu-devel] [PATCH v1 2/9] target-ppc: implement lxvll instruction

lxvll: Load VSX Vector Left-justified with Length Little/Big-endian Storage: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ Loading 14 bytes to vector

[Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9

This series contains 12 new instructions for POWER9 ISA3.0 Couple of consolidation patches VSX Vector Insert/Extract Word VSX Vector Permute VSX Load/Store with length VSX Scalar Quad-Precision Move Instructions Changelog: v0: * Fixed lxvl/lxvll and stxvl/stxvll as

[Qemu-devel] [PATCH v1 1/9] target-ppc: implement lxvl instruction

lxvl: Load VSX Vector with Length Little/Big-endian Storage: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ Loading 14 bytes results in: Vector (8-bit

Re: [Qemu-devel] [PATCH 1/2] tcg/aarch64: Fix addsub2 for 0+C

On 12/07/2016 10:10 AM, Peter Maydell wrote: > On 7 December 2016 at 18:07, Richard Henderson wrote: >> When al == xzr, we cannot use addi/subi because that encodes xsp. >> Force a zero into the temp register for that (rare) case. > > Incidentally I was slightly surprised that

[Qemu-devel] [PATCH] tcg/s390: Fix setcond expansion

We can't use LOAD AND TEST for unsigned data and then expect to extract the result with ADD LOGICAL WITH CARRY. Fall through to using COMPARE LOGICAL IMMEDIATE instead. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 50

Re: [Qemu-devel] [PATCH 1/2] tcg/aarch64: Fix addsub2 for 0+C

On 7 December 2016 at 18:07, Richard Henderson wrote: > When al == xzr, we cannot use addi/subi because that encodes xsp. > Force a zero into the temp register for that (rare) case. Incidentally I was slightly surprised that the optimisation pass didn't turn "add2 rlo, rhi, 0,

[Qemu-devel] [PATCH 2/2] tcg/aarch64: Fix tcg_out_movi

There were some patterns, like 0x___00ff, for which we would select to begin a multi-insn sequence with MOVN, but would fail to set the 0x lane back from 0x. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 57

[Qemu-devel] [PATCH 0/2] tcg/aarch64 fixes

Both of these were identified by Alex and his risu testsuite, and diagnosed by Peter. I believe that both bugs are my fault, originally. The risu testsuite, as posted, now passes with an aarch64 host. r~ Richard Henderson (2): tcg/aarch64: Fix addsub2 for 0+C tcg/aarch64: Fix

[Qemu-devel] [PATCH 1/2] tcg/aarch64: Fix addsub2 for 0+C

When al == xzr, we cannot use addi/subi because that encodes xsp. Force a zero into the temp register for that (rare) case. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 9 + 1 file changed, 9 insertions(+) diff --git

[Qemu-devel] [PATCH for 2.8 v4 1/1] cadence_uart: Check baud rate generator and divider values on migration

The Cadence UART device emulator calculates speed by dividing the baud rate by a 'baud rate generator' & 'baud rate divider' value. The device specification defines these register values to be non-zero and within certain limits. Checks were recently added when writing to these registers but not

Re: [Qemu-devel] [PATCH for 2.8 v3 1/1] cadence_uart: Check baud rate generator and divider values on migration

On Tue, Dec 6, 2016 at 1:31 AM, Peter Maydell wrote: > On 5 December 2016 at 18:35, Alistair Francis > wrote: >> The Cadence UART device emulator calculates speed by dividing the >> baud rate by a 'baud rate generator' & 'baud rate divider'

[Qemu-devel] [PATCH] Correct value of ARM Cortex-A8 MVFR1 register.

The value of the MVFR1 (Media and VFP Feature Register 1) register for the Cortex-A8 appears to be incorrect (according to the TRM, DDI0344K), with the "full denormal arithmetic" and "propagation of NaN" fields holding both 0 instead of both 1. I had a go tracing the history of the use of this

[Qemu-devel] [PATCH v5 3/3] utils: Add prefetch for Thunderx platform

From: Vijaya Kumar K Thunderx pass2 chip requires explicit prefetch instruction to give prefetch hint. To speed up live migration on Thunderx platform, prefetch instruction is added in zero buffer check function.The below results show live migration time improvement

[Qemu-devel] [PATCH v5 2/3] utils: Add helper to read arm MIDR_EL1 register

From: Vijaya Kumar K Add helper API to read MIDR_EL1 registers to fetch cpu identification information. This helps in adding errata's and architecture specific features. This is implemented only for arm architecture. Signed-off-by: Vijaya Kumar K

[Qemu-devel] [PATCH v5 0/3] Live migration optimization for Thunderx platform

From: Vijaya Kumar K The CPU MIDR_EL1 register is exposed to userspace for arm64 with the below patch. https://lkml.org/lkml/2016/7/8/467 Thunderx platform requires explicit prefetch instruction to provide prefetch hint. Using MIDR_EL1 information, provided by above

[Qemu-devel] [PATCH v5 1/3] cutils: Set __builtin_prefetch optional parameters

From: Vijaya Kumar K Optional parameters of __builtin_prefetch() which specifies rw and locality to 0's. For checking buffer is zero, set rw as read and temporal locality to 0. On arm64, __builtin_prefetch(addr) generates 'prfmpldl1keep' where

Re: [Qemu-devel] [kvm-unit-tests PATCH v14 0/5] ARM PMU tests

On Tue, Dec 06, 2016 at 12:05:23PM -0600, Wei Huang wrote: > Changes from v13: > * Rename cp15.h to sysreg.h for ARMv7 and add a new file sysreg.h for ARMv8 > * Add macros for read_sysreg() and write_sysreg(). CP15 registers can be > defined with __ACCESS_CP15() or __ACCESS_CP15_64(). sysreg.h

Re: [Qemu-devel] [PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration

Removing silly virtio-dev@ list because it's bouncing mail... On 12/07/2016 08:21 AM, David Hildenbrand wrote: >> Li's current patches do that. Well, maybe not pfn/length, but they do >> take a pfn and page-order, which fits perfectly with the kernel's >> concept of high-order pages. > > So we

Re: [Qemu-devel] [kvm-unit-tests PATCH v14 2/5] arm: Add support for read_sysreg() and write_sysreg()

On Tue, Dec 06, 2016 at 12:05:25PM -0600, Wei Huang wrote: > This patch adds two new macros to support read/write operations of ARMv7 > and ARMv8 system registers. As part of the change, xstr() is revised to > support variable arguments. With it, ARMv7 system register can be defined > with

Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH qemu] spapr_pci: Create PCI-express root bus by default

[Added Marcel to CC] On Wed, 2016-12-07 at 15:11 +1100, David Gibson wrote: > > Is the difference between q35 and pseries guests with > > respect to PCIe only relevant when it comes to assigned > > devices, or in general? I'm asking this because you seem to > > focus entirely on assigned devices.

Re: [Qemu-devel] [PATCH v3 5/5] tests: Add coverage for recent block geometry fixes

On 12/07/2016 10:16 AM, Kevin Wolf wrote: > Am 02.12.2016 um 20:22 hat Eric Blake geschrieben: >> Use blkdebug's new geometry constraints to emulate setups that >> have caused recent regression fixes: write zeroes asserting >> when running through a loopback block device with max-transfer >>

Re: [Qemu-devel] [Qemu-block] [PATCH] doc: Propose NBD_FLAG_INIT_ZEROES extension

Am 07.12.2016 um 16:50 hat Eric Blake geschrieben: > On 12/07/2016 04:44 AM, Kevin Wolf wrote: > >> Just because the NBD spec describes the bit does NOT require that > >> servers HAVE to set the bit on all images that are all zeroes. It is > >> perfectly compliant if the server never advertises

Re: [Qemu-devel] [PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration

I did something similar. Filled the balloon with 15GB for a 16GB idle guest, by using bitmap, the madvise count was reduced to 605. when using the PFNs, the madvise count was 3932160. It means there are quite a lot consecutive bits in the bitmap. I didn't test for a guest with heavy memory

  1   2   >