Re: [Qemu-devel] [PATCH] disas/cris.c: Fix Coverity warning about unchecked NULL

On 9 January 2017 at 19:10, wrote: > Checking PATCH 1/1: disas/cris.c: Fix Coverity warning about unchecked NULL... > ERROR: code indent should never use tabs > #24: FILE: disas/cris.c:2493: > +^Iif (sregp == NULL || sregp->name == NULL)$ > > ERROR: suspect code indent for

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

Hum, ... I think I have a problem. With the default register value (that I get a reset) the CS line is deselected when the CS is high. So at reset I would need to set my 4 CS lines to high in order to be able to drive them low later. So during the "reset" I need to set my 4 CS line to 1

Re: [Qemu-devel] [PATCH] error: error_setg_errno(): errno gets preserved

On 01/09/2017 12:27 PM, Halil Pasic wrote: >>> I still do >>> not understand why were you wrong there. In fact, I could argue that you >>> were right, but I'm afraid the argument would be somewhat lengthy and >>> confusing, and I'm already feeling bad about taking so much of your time >>> with

Re: [Qemu-devel] [PATCH v4 4/4] migration: Fail migration blocker for --only-migratble

On 01/09/2017 11:02 AM, Ashijeet Acharya wrote: s/migratble/migratable/ in the subject > migrate_add_blocker should rightly fail if the '--only-migratable' > option was specified and the device in use should not be able to > perform the action which results in an unmigratable VM. > > Make

[Qemu-devel] [PATCH] display: cirrus: ignore source pitch value as needed in blit_is_unsafe

Commit 4299b90 added a check which is too broad, given that the source pitch value is not required to be initialized for solid fill operations. This patch refines the blit_is_unsafe() check to ignore source pitch in that case. After applying the above commit as a security patch, we noticed the

Re: [Qemu-devel] [PATCH 3/3] fix qmp/hmp query-memdev not repporting IDs of memory backends

On 01/09/2017 08:17 AM, Igor Mammedov wrote: >> Wait. Isn't this going to inject an 'id' dict member to every use of >> user_creatable_add_type()? But not all QAPI structs contain an id >> member. Which means that you are now explicitly relying on the visitor >> to silently ignore garbage in

[Qemu-devel] [PATCH 2/3] migration: Check for ID length

From: "Dr. David Alan Gilbert" The qdev id of a device can be huge if it's on the end of a chain of bridges; in reality such chains shouldn't occur but they can be made to by chaining PCIe bridges together. The migration format has a number of 256 character long format

[Qemu-devel] [PATCH 3/3] vmstate registration: check return values

From: "Dr. David Alan Gilbert" Check qdev's call to vmstate_register_with_alias_id; that gets most of the common uses; there's hundreds of calls via vmstate_register which could get fixed over time. Signed-off-by: Dr. David Alan Gilbert ---

Re: [Qemu-devel] [PATCH] disas/cris.c: Fix Coverity warning about unchecked NULL

On Mon, Jan 09, 2017 at 07:05:59PM +, Peter Maydell wrote: > Coverity (CID 1005689) warns that we don't check that > spec_reg_info() returned non-NULL before dereferencing. > Add the check, though as the comment notes this is > a can't-really-happen case because the earlier constraint >

[Qemu-devel] [PATCH 0/3] Protect against long IDs

From: "Dr. David Alan Gilbert" QEMU currently asserts if you try and create a PCI device on the end of a very long chain, because the ID string exceeds the maximum length, and ends up aliasing. Fail with a clean error in this common case; there's lots of other places that

[Qemu-devel] [PATCH 1/3] vmstate_register_with_alias_id: Take an Error **

From: "Dr. David Alan Gilbert" I'll be adding an error to it in a subsequent patch. Signed-off-by: Dr. David Alan Gilbert --- hw/core/qdev.c | 3 ++- hw/intc/apic_common.c | 2 +- include/migration/vmstate.h | 5 +++--

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

Le 09/01/2017 à 20:06, Peter Maydell a écrit : On 9 January 2017 at 19:04, mar.krzeminski wrote: W dniu 09.01.2017 o 11:46, Peter Maydell pisze: Calling qemu_set_irq() in a device reset function is a bit tricky, because in a full system reset the device at the other

Re: [Qemu-devel] [PATCH] Update FreeBSD syscall numbers

On 01/09/17 07:00, Peter Maydell wrote: > On 5 January 2017 at 16:41, Sean Bruno wrote: >> Signed-off-by: Sean Bruno >> Signed-off-by: Stacy Son >> --- >> bsd-user/freebsd/syscall_nr.h | 929 >>

Re: [Qemu-devel] [PULL 21/25] scsi-disk: fix VERIFY for scsi-block

On 22 December 2016 at 15:22, Paolo Bonzini wrote: > When a scsi-disk object receives VERIFY command with BYTCHK bit being zero, > scsi_block_is_passthrough returns false and finally makes req being proceeded > by scsi_block_dma_command. Because scsi_block_dma_command has

Re: [Qemu-devel] [PATCH] disas/cris.c: Fix Coverity warning about unchecked NULL

Hi, Your series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PATCH] disas/cris.c: Fix Coverity warning about unchecked NULL Type: series Message-id: 1483988759-14606-1-git-send-email-peter.mayd...@linaro.org === TEST SCRIPT BEGIN ===

Re: [Qemu-devel] [PULL v2 00/11] tcg host mips64 support

On 9 January 2017 at 19:02, Richard Henderson wrote: > [Bah. This time with actual request-pull info.] > > This is v6 of Jin Guojie's patch set, as tested by Aurelien Jarno, > James Hogan, and Yun Qiang Su. Plus one more patch from me to fix > a trival Werror in mips specific

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

On 9 January 2017 at 19:04, mar.krzeminski wrote: > > > W dniu 09.01.2017 o 11:46, Peter Maydell pisze: >> Calling qemu_set_irq() in a device reset function is a bit >> tricky, because in a full system reset the device at the other >> end might have already reset or

[Qemu-devel] [PATCH] disas/cris.c: Fix Coverity warning about unchecked NULL

Coverity (CID 1005689) warns that we don't check that spec_reg_info() returned non-NULL before dereferencing. Add the check, though as the comment notes this is a can't-really-happen case because the earlier constraint matching should have ruled out the "unknown reg" case. Signed-off-by: Peter

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

W dniu 09.01.2017 o 11:46, Peter Maydell pisze: On 4 January 2017 at 22:06, Jean-Christophe Dubois wrote: The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI

[Qemu-devel] [PULL v2 00/11] tcg host mips64 support

[Bah. This time with actual request-pull info.] This is v6 of Jin Guojie's patch set, as tested by Aurelien Jarno, James Hogan, and Yun Qiang Su. Plus one more patch from me to fix a trival Werror in mips specific code with gcc 5.3. r~ The following changes since commit

[Qemu-devel] [PATCH] hw/net/dp8393x: Avoid unintentional sign extensions on addresses

The dp8393x has several 32-bit values which are formed by concatenating two 16 bit device register values. Attempting to do these inline with ((s->reg[HI] << 16) | s->reg[LO]) can result in an unintended sign extension because "x << 16" is of type 'int' even though s->reg is unsigned, and so if

Re: [Qemu-devel] [PATCH] error: error_setg_errno(): errno gets preserved

On 01/09/2017 03:50 PM, Eric Blake wrote: > On 07/29/2016 08:38 AM, Halil Pasic wrote: >> >> >> On 07/28/2016 11:03 PM, Eric Blake wrote: >>> On 07/28/2016 09:29 AM, Halil Pasic wrote: >>> > You mean va_start, not start_va. And actually, C11 is clear that errno > is unspecified after

Re: [Qemu-devel] [PATCH v4 3/6] hypertrace: [*-user] Add QEMU-side proxy to "guest_hypertrace" event

Stefan Hajnoczi writes: > On Mon, Dec 26, 2016 at 09:34:54PM +0100, Lluís Vilanova wrote: >> +static void segv_handler(int signum, siginfo_t *siginfo, void *sigctxt) >> +{ >> +CPUState *vcpu = current_cpu; >> +void *control_0 = vcpu->hypertrace_control; >> +void *control_1 =

Re: [Qemu-devel] [PATCH 20/20] chardev: qom-ify

On 01/05/2017 10:53 AM, Marc-André Lureau wrote: > Turn Chardev into Object. > > qemu_chr_alloc() is replaced by the qemu_chardev_new() constructor. It > will call qemu_char_open() to open/intialize the chardev with the > ChardevCommon *backend settings. > > The CharDriver::create() callback is

Re: [Qemu-devel] CMSIS SVD based peripheral definitions

> On 9 Jan 2017, at 19:31, Peter Maydell wrote: > > FSF's view is that Apache 2.0 is not compatible with GPLv2: I can't dispute this, but does't the GPLv2 requirements apply to the qemu executable only? my JSON files are not compiled into the binary, but are data

Re: [Qemu-devel] [PATCH] hw/i386/kvmvapic: Remove dead code in patch_hypercalls()

On 2017-01-09 18:05, Peter Maydell wrote: > The patch_hypercalls() function sets up a 'patches' > variable and checks it at the end of the function, but > never modifies it in the middle. Remove this dead code, > which seems to have been present since the function was > added in commit

Re: [Qemu-devel] CMSIS SVD based peripheral definitions

On 9 January 2017 at 16:51, Liviu Ionescu wrote: >> On 9 Jan 2017, at 18:16, Peter Maydell wrote: >> The obvious issue that comes to mind >> is licensing, though -- what licenses are the SVD files under, >> and would those be compatible with QEMU's

Re: [Qemu-devel] [PATCH 15/17] iotests: add default node-name

On 11/22/2016 08:54 PM, Vladimir Sementsov-Ogievskiy wrote: > When testing migration, auto-generated by qemu node-names differs in > source and destination qemu and migration fails. After this patch, > auto-generated by iotest nodenames will be the same. > > Signed-off-by: Vladimir

Re: [Qemu-devel] [PULL for-2.9 0/9] virtio, vhost, pc: fixes

On 9 January 2017 at 16:48, Michael S. Tsirkin wrote: > The strange thing here is that this actually seems to apply patches > from list instead of getting the tag from the tree. That's because it's really supposed to be working on patches sent to the list -- it only checks pull

Re: [Qemu-devel] [PATCH v4 0/4] Introduce a new --only-migratable option

Hi, Your series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PATCH v4 0/4] Introduce a new --only-migratable option Message-id: 1483981368-9965-1-git-send-email-ashijeetacha...@gmail.com === TEST SCRIPT BEGIN ===

Re: [Qemu-devel] QEMU online/offline cpu

On Tue, 3 Jan 2017 12:37:36 +0100 Igor Mammedov wrote: [...] > Wiki page http://wiki.qemu.org/Features/CPUHotplug is rather outdated, > I'll update it to reflect currently implemented hotplug interfaces/targets. David, I've updated above CPUHotplug wiki page to match

[Qemu-devel] [PATCH v4 2/4] migration: Allow "device add" options to only add migratable devices

Introduce checks for the unmigratable flag in the VMStateDescription structs of respective devices when user attempts to add them. If the "--only-migratable" was specified, all unmigratable devices will rightly fail to add. This feature is made compatible for both "-device" and "-usbdevice"

Re: [Qemu-devel] [PATCH v6] qqq: module for synchronizing with a simulation

On 09/01/2017 18:04, Nutaro, James J. wrote: > Thanks again Paolo. When I change the command line switches, is it best to > submit a whole new version of the patch? Or is there another method for > managing patch revisions? Yes, submit a new version, then put v6->v7: did this and that

[Qemu-devel] [PATCH] hw/i386/kvmvapic: Remove dead code in patch_hypercalls()

The patch_hypercalls() function sets up a 'patches' variable and checks it at the end of the function, but never modifies it in the middle. Remove this dead code, which seems to have been present since the function was added in commit e5ad936b0fd7 in 2012. (Spotted by Coverity: CID 1005581.)

[Qemu-devel] [PATCH v4 3/4] migration: disallow migrate_add_blocker during migration

If a migration is already in progress and somebody attempts to add a migration blocker, this should rightly fail. Add an errp parameter and a retcode return value to migrate_add_blocker. Signed-off-by: John Snow Signed-off-by: Ashijeet Acharya ---

Re: [Qemu-devel] [PATCH v6] qqq: module for synchronizing with a simulation

Thanks again Paolo. When I change the command line switches, is it best to submit a whole new version of the patch? Or is there another method for managing patch revisions? Thanks, Jim -Original Message- From: Paolo Bonzini [mailto:pbonz...@redhat.com] Sent: Thursday, January 05,

Re: [Qemu-devel] [PATCH v5 3/4] Plumb the HAXM-based hardware acceleration support

On Mon, Jan 9, 2017 at 2:03 PM, Paolo Bonzini wrote: > > > On 06/01/2017 15:08, Vincent Palatin wrote: >> Apart from the above change, can you check if there are some less >> heavyeight methods to force an exit? I can think of QueueUserAPC with >> an empty pfnAPC

[Qemu-devel] [PATCH v4 4/4] migration: Fail migration blocker for --only-migratble

migrate_add_blocker should rightly fail if the '--only-migratable' option was specified and the device in use should not be able to perform the action which results in an unmigratable VM. Make migrate_add_blocker return -EACCES in this case. Signed-off-by: Ashijeet Acharya

[Qemu-devel] [PATCH v4 0/4] Introduce a new --only-migratable option

Previously posted series patches: http://lists.nongnu.org/archive/html/qemu-devel/2017-01/msg00320.html http://lists.nongnu.org/archive/html/qemu-devel/2016-12/msg02391.html http://lists.nongnu.org/archive/html/qemu-devel/2016-12/msg02062.html This series adds a new command line option

[Qemu-devel] [PATCH v4 1/4] migration: Add a new option to enable only-migratable

Add a new option "--only-migratable" in qemu which will allow to add only those devices which will not fail qemu after migration. Devices set with the flag 'unmigratable' cannot be added when this option will be used. Signed-off-by: Ashijeet Acharya ---

[Qemu-devel] [PATCH v2 08/11] aspeed/smc: reset flash after each test

Let's make sure when each test is run that the flash object is in an initial state and did not keep configuration from the previous tests. Signed-off-by: Cédric Le Goater --- tests/m25p80-test.c | 31 +++ 1 file changed, 31 insertions(+) diff --git

[Qemu-devel] [PATCH v2 06/11] aspeed/smc: adjust the size of the register region

The SPI controller of the AST2400 SoC has less registers. So we can adjust the size of the memory region holding the registers depending on the controller type. We can also remove the guest_error logging which is useless as the range of the region is strict enough. Signed-off-by: Cédric Le Goater

Re: [Qemu-devel] CMSIS SVD based peripheral definitions

> On 9 Jan 2017, at 18:16, Peter Maydell wrote: > > On 28 December 2016 at 18:49, Liviu Ionescu wrote: >> The latest release of GNU ARM Eclipse QEMU (2.8.0-20161227) introduced >> a new technology for implementing peripherals, based on standard >>

Re: [Qemu-devel] [PULL for-2.9 0/9] virtio, vhost, pc: fixes

On Fri, Dec 16, 2016 at 01:32:04PM -0800, no-re...@patchew.org wrote: > Hi, > > Your series seems to have some coding style problems. See output below for > more information: > > Type: series > Subject: [Qemu-devel] [PULL for-2.9 0/9] virtio, vhost, pc: fixes > Message-id:

[Qemu-devel] [PATCH v2 03/11] aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines

Change the routines prototype to use a 'AspeedSMCFlash *' instead of 'AspeedSMCState *'. The result will help in making future changes clearer. Also change aspeed_smc_update_cs() which uselessly loops on all slave devices to update their status. Signed-off-by: Cédric Le Goater

[Qemu-devel] [PATCH] hw/display/framebuffer.c: Avoid overflow for framebuffers > 4GB

Coverity points out that calculating src_len by multiplying src_width by rows could overflow. This can only happen in the implausible case of a framebuffer larger than 4GB, but we may as well fix it, placating Coverity. (CID1005515) Signed-off-by: Peter Maydell ---

Re: [Qemu-devel] [PATCH v4 3/6] hypertrace: [*-user] Add QEMU-side proxy to "guest_hypertrace" event

On Mon, Dec 26, 2016 at 09:34:54PM +0100, Lluís Vilanova wrote: > +static void segv_handler(int signum, siginfo_t *siginfo, void *sigctxt) > +{ > +CPUState *vcpu = current_cpu; > +void *control_0 = vcpu->hypertrace_control; > +void *control_1 = vcpu->hypertrace_control +

[Qemu-devel] [PATCH v2 02/11] aspeed/smc: remove call to aspeed_smc_update_cs() in reset function

Instead, we can simply set the irq level when unselecting the slave devices. This change prepares ground for a subsequent cleanup of the aspeed_smc_update_cs() routine which uselessly loops on all slaves to update their status. Signed-off-by: Cédric Le Goater ---

Re: [Qemu-devel] [Bug 1654137] Re: Ctrl-A b not working in 2.8.0

Hi On Mon, Jan 9, 2017 at 4:39 PM Marc-André Lureau wrote: > Hi > > On Fri, Jan 6, 2017 at 2:46 PM Andreas Gustafsson wrote: > > I am also seeing this problem. In case it was not clear from Paul's > original report, it affects guests using a serial

[Qemu-devel] [PATCH v2 01/11] aspeed/smc: remove call to reset in realize function

This is useless as reset will be called later on. Signed-off-by: Cédric Le Goater --- hw/ssi/aspeed_smc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 78f5aed53247..8a7217d4df6c 100644 --- a/hw/ssi/aspeed_smc.c +++

Re: [Qemu-devel] [PATCH v4 6/6] hypertrace: Add guest-side Linux module

On Mon, Dec 26, 2016 at 09:35:10PM +0100, Lluís Vilanova wrote: > Provides guest Linux kernel module "qemu-hypertrace.ko" to abstract > access to the hypertrace channel. > > Signed-off-by: Lluís Vilanova > --- > Makefile |4 - >

[Qemu-devel] [PATCH v2 11/11] aspeed/smc: handle dummy bytes when doing fast reads in command mode

When doing fast read, a certain amount of dummy bytes should be sent before the read. This number is configurable in the controler CE0 Control Register and needs to be modeled using fake transfers the flash module. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery

Re: [Qemu-devel] Question about add AF_ALG backend for virtio-crypto

On Mon, Jan 09, 2017 at 01:43:10PM +, Stefan Hajnoczi wrote: > On Mon, Jan 09, 2017 at 03:04:55PM +0800, Longpeng (Mike) wrote: > > I'm one of Gonglei's virtio-crypto project members, and we plan to add a > > AF_ALG > > backend for virtio-crypto(there's only builtin-backend currently). > > >

Re: [Qemu-devel] [PULL for-2.9 0/9] virtio, vhost, pc: fixes

On 6 January 2017 at 21:20, Michael S. Tsirkin wrote: > So the email might be malformed, but git commits are ok I think. > Peter, could you pls merge? I'll investigate my email settings later. Applied to master, thanks. -- PMM

Re: [Qemu-devel] [PATCH v4 0/6] hypertrace: Lightweight guest-to-QEMU trace channel

On Mon, Dec 26, 2016 at 09:34:38PM +0100, Lluís Vilanova wrote: > The hypertrace channel allows guest code to emit events in QEMU (the host) > using > its tracing infrastructure (see "docs/trace.txt"). This works in both 'system' > and 'user' modes, is architecture-agnostic and introduces minimal

[Qemu-devel] [PATCH v2 07/11] aspeed/smc: handle SPI flash Command mode

The Aspeed SMC controllers have a mode (Command mode) in which accesses to the flash content are no different than doing MMIOs. The controller generates all the necessary commands to load (or store) data in memory. However, accesses are restricted to the segment window assigned the the flash

[Qemu-devel] [PATCH v2 10/11] aspeed: use first FMC flash as a boot ROM

Create a ROM region, using the default size of the mapping window for the CE0 FMC flash module, and fill it with the flash content. This is a little hacky but until we can boot from a MMIO region, it seems difficult to do anything else. Signed-off-by: Cédric Le Goater

[Qemu-devel] [PATCH v2 00/11] Aspeed SMC controller fixes and improvements

Hello, I have reduced the patchset size to focus on some improvements of the SMC (Flash) controller model only and will address the watchdog and network models in other patchset. The main benefit of this series is to enable booting directly from a flash image containing U-Boot. It adds : -

[Qemu-devel] [PATCH v2 04/11] aspeed/smc: autostrap CE0/1 configuration

On the AST2500 SoC, the FMC controller flash type is fixed to SPI for CE0 and CE1 and 4BYTE mode is autodetected for CE0. On the AST2400 SoC, the FMC controller flash type and 4BYTE mode are strapped with register SCU70. We use the default settings from the palmetto-bmc machine for now.

[Qemu-devel] [PATCH v2 10/18] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers

Implement the the ICV_ registers HPPIR, DIR and RPR. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 235 +- hw/intc/trace-events | 3 + 2 files changed, 235 insertions(+), 3 deletions(-) diff --git

Re: [Qemu-devel] [PATCH] vnc: track LED state separately

On 04/01/17 09:57, Gerd Hoffmann wrote: /me wonders how you've tested the patch ... That would be not at all. Or rather, just a compile. :) Tried, but checkpatch found some more issues: Fixed. New patch incoming. Regards -- Pierre Ossman Software Development Cendio AB

[Qemu-devel] [PATCH v2 09/11] aspeed/smc: extend tests for Command mode

The Aspeed SMC controllers have a mode (Command mode) in which accesses to the flash content are no different than doing MMIOs. The controller generates all the necessary commands to load (or store) data in memory. So add a couple of tests doing direct reads and writes on the AHB bus.

[Qemu-devel] [PATCH v2 02/18] hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ

Augment the GIC's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. We never use these, but it's helpful to keep the v2-and-earlier GIC's external interface in line with that of the GICv3 to avoid board code having to add extra code conditional

Re: [Qemu-devel] CMSIS SVD based peripheral definitions

On 28 December 2016 at 18:49, Liviu Ionescu wrote: > The latest release of GNU ARM Eclipse QEMU (2.8.0-20161227) introduced > a new technology for implementing peripherals, based on standard > CMSIS SVD definitions > (http://www.keil.com/pack/doc/CMSIS/SVD/html/index.html). > >

[Qemu-devel] [PATCH v2 16/18] target/arm/psci.c: If EL2 implemented, start CPUs in EL2

The PSCI spec states that a CPU_ON call should cause the new CPU to be started in the highest implemented Non-secure exception level. We were incorrectly starting it at the exception level of the caller, which happens to be correct if EL2 is not implemented. Implement the correct logic as

[Qemu-devel] [PATCH v2 05/11] aspeed/smc: unfold the AspeedSMCController array

This is getting difficult to read. Also add a 'has_dma' field for each controller type. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery --- hw/ssi/aspeed_smc.c | 91

[Qemu-devel] [PATCH v2 12/18] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()

Implement the function which signals virtual interrupts to the CPU as appropriate following CPU interface state changes. Signed-off-by: Peter Maydell --- include/hw/intc/arm_gicv3_common.h | 1 + hw/intc/arm_gicv3_cpuif.c | 49

[Qemu-devel] [PATCH] vnc: track LED state separately

Piggy-backing on the modifier state array made it difficult to send out updates at the proper times. Signed-off-by: Pierre Ossman --- ui/vnc.c | 59 --- ui/vnc.h | 3 ++- 2 files changed, 18 insertions(+), 44

[Qemu-devel] [PATCH v2 08/18] hw/intc/arm_gicv3: Add accessors for ICH_ system registers

The GICv3 virtualization interface includes system registers accessible only to the hypervisor which form the control interface for interrupt virtualization. Implement these registers. The function gicv3_cpuif_virt_update() which determines whether it needs to signal vIRQ, vFIQ or a maintenance

Re: [Qemu-devel] [PATCH v4 4/6] hypertrace: [softmmu] Add QEMU-side proxy to "guest_hypertrace" event

On Mon, Dec 26, 2016 at 09:34:59PM +0100, Lluís Vilanova wrote: > +#define PAGE_SIZE TARGET_PAGE_SIZE Unused. Please remove. signature.asc Description: PGP signature

[Qemu-devel] [PATCH v2 06/18] hw/intc/gicv3: Add defines for ICH system register fields

Add defines to gicv3_internal.h for fields in the ICH_* system registers which form the GIC virtualization control interface. Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 79 1 file changed, 79

[Qemu-devel] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs

This patchset adds support for the Virtualization extensions to QEMU's GICv3 emulation. This was the last missing piece that was stopping us from turning on the EL2 support in the CPU model, so the patchset also adds support for enabling it all on the virt board via the '-machine

[Qemu-devel] [PATCH v2 13/18] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs

Implement the architecturally required traps from NS EL1 to EL2 for the CPU interface registers. These fall into several different groups: * group-0-only registers all trap if ICH_HRC_EL2.TALL0 is set (exactly the registers covered by gicv3_fiq_access()) * group-1-only registers all trap if

[Qemu-devel] [PATCH v2 03/18] target-arm: Expose output GPIO line for VCPU maintenance interrupt

The GICv3 support for virtualization includes an outbound maintenance interrupt signal which is asserted when the CPU interface wants to signal to the hypervisor that it needs attention. Expose this as an outbound GPIO line from the CPU object which can be wired up as a physical interrupt line by

[Qemu-devel] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU

Wire the new VIRQ, VFIQ and maintenance interrupt lines from the GIC to each CPU. Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 2 ++ hw/arm/virt.c | 14 +++--- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git

[Qemu-devel] [PATCH v2 07/18] hw/intc/gicv3: Add data fields for virtualization support

As the first step in adding support for the virtualization extensions to the GICv3 emulation: * add the necessary data fields to the state structures * add the fields to the migration state, as a subsection which is only present if virtualization is enabled The use of a subsection means we

[Qemu-devel] [PATCH v2 18/18] hw/arm/virt: Add board property to enable EL2

Add a board level property to the virt board which will enable EL2 on the CPU if the user asks for it. The default is not to provide EL2. If EL2 is enabled then we will use SMC as our PSCI conduit, and report the virtualization support in the GICv3 device tree node and the ACPI tables.

[Qemu-devel] [PATCH v2 17/18] target-arm: Enable EL2 feature bit on A53 and A57

Enable the ARM_FEATURE_EL2 bit on Cortex-A52 and Cortex-A57, since this is all now sufficiently implemented to work with the GICv3. We provide the usual CPU property to disable it for backwards compatibility with the older virt boards. In this commit, we disable the EL2 feature on the virt and

[Qemu-devel] [PATCH v2 01/18] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ

Augment the GICv3's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. Signed-off-by: Peter Maydell --- include/hw/intc/arm_gicv3_common.h | 2 ++ hw/intc/arm_gicv3_common.c | 6 ++ 2 files changed, 8

[Qemu-devel] [PATCH v2 11/18] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR

Implement the two remaining ICV_ registers: EOIR and IAR. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 220 ++ hw/intc/trace-events | 2 + 2 files changed, 222 insertions(+) diff --git

[Qemu-devel] [PATCH v2 05/18] target-arm: Add ARMCPU fields for GIC CPU i/f config

Add fields to the ARMCPU structure to allow CPU classes to specify the configurable aspects of their GIC CPU interface. In particular, the virtualization support allows different values for number of list registers, priority bits and preemption bits. Signed-off-by: Peter Maydell

[Qemu-devel] [PATCH v2 15/18] hw/arm/virt-acpi-build: use SMC if booting in EL2

From: Andrew Jones Signed-off-by: Andrew Jones [PMM: look at vms->psci_conduit rather than vms->virt to decide whether to use HVC or SMC, and report no PSCI support at all for the 'PSCI disabled' case] Signed-off-by: Peter Maydell

[Qemu-devel] [PATCH v2 09/18] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors

If the HCR_EL2.IMO or FMO bits are set, accesses to ICC_ system registers are redirected to be accesses to ICV_ registers (the guest-visible interface to the virtual interrupt controller). Implement this behaviour for the ICV_ registers which are simple accessors to the underlying register state.

[Qemu-devel] [PATCH v2 14/18] hw/arm/virt: Support using SMC for PSCI

If we are giving the guest a CPU with EL2, it is likely to want to use the HVC instruction itself, for instance for providing PSCI to inner guest VMs. This makes using HVC as the PSCI conduit for the outer QEMU a bad idea. We will want to use SMC instead is this case: this makes sense because

Re: [Qemu-devel] [PATCH 15/17] iotests: add default node-name

09.01.2017 18:57, Denis V. Lunev wrote: On 11/22/2016 08:54 PM, Vladimir Sementsov-Ogievskiy wrote: When testing migration, auto-generated by qemu node-names differs in source and destination qemu and migration fails. After this patch, auto-generated by iotest nodenames will be the same.

Re: [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs

On 19 December 2016 at 22:20, Alistair Francis wrote: > If I manually enable EL2 and EL3 for the Xilinx EP108 board I can > replicate a full hardware flow from ATF -> u-boot -> Linux. > > Unfortunately Linux doesn't get too far as I get the error below. This > is further

Re: [Qemu-devel] [PATCH v4 3/6] hypertrace: [*-user] Add QEMU-side proxy to "guest_hypertrace" event

On Mon, Dec 26, 2016 at 09:34:54PM +0100, Lluís Vilanova wrote: > @@ -847,6 +855,10 @@ int main(int argc, char **argv) > } else if (!strcmp(r, "trace")) { > g_free(trace_file); > trace_file = trace_opt_parse(optarg); > +} else if (!strcmp(r,

Re: [Qemu-devel] Question about add AF_ALG backend for virtio-crypto

On Mon, Jan 09, 2017 at 03:04:55PM +0800, Longpeng (Mike) wrote: > I'm one of Gonglei's virtio-crypto project members, and we plan to add a > AF_ALG > backend for virtio-crypto(there's only builtin-backend currently). > > I found that Catalin, Paolo and Stefan had discussed about this in 2015 >

[Qemu-devel] [PATCH v2 8/8] io: introduce a DNS resolver API

Currently DNS resolution is done automatically as part of the creation of a QIOChannelSocket object instance. This works ok for network clients where you just end up a single network socket, but for servers, the results of DNS resolution may require creation of multiple sockets. Introducing a DNS

Re: [Qemu-devel] implementing architectural timers using QEMU timers

> On 9 Jan 2017, at 15:18, Max Filippov wrote: > > Hello, > > I'm trying to reimplement xtensa CCOUNT (cycle counter) and > CCOMPARE (CCOUNT-based timer interrupts) using QEMU > timers. That is CCOUNT value is derived from the > QEMU_CLOCK_VIRTUAL clock and CCOMPARE

[Qemu-devel] [PATCH v2 6/8] io: change the QIOTask callback signature

Currently the QIOTaskFunc signature takes an Object * for the source, and an Error * for any error. We also need to be able to provide a result pointer. Rather than continue to add parameters to QIOTaskFunc, remove the existing ones and simply pass the QIOTask object instead. This has methods to

[Qemu-devel] [PATCH v2 4/8] io: add ability to associate an opaque "result" with with a task

Currently there is no data associated with a successful task completion. This adds an opaque pointer to the task to store an arbitrary result. Reviewed-by: Eric Blake Signed-off-by: Daniel P. Berrange --- include/io/task.h | 27

[Qemu-devel] [PATCH v2 5/8] io: add ability to associate an error with a task

Currently when a task fails, the error is never explicitly associated with the task object, it is just passed along through the completion callback. This adds the ability to explicitly associate an error with the task. Signed-off-by: Daniel P. Berrange --- include/io/task.h

Re: [Qemu-devel] [Bug 1654137] Re: Ctrl-A b not working in 2.8.0

Hi On Fri, Jan 6, 2017 at 2:46 PM Andreas Gustafsson wrote: > I am also seeing this problem. In case it was not clear from Paul's > original report, it affects guests using a serial console. > > Also, it is not specific to NetBSD. I can reproduce it using a Linux > guest on a

[Qemu-devel] [PATCH v2 2/8] io: stop incrementing reference in qio_task_get_source

Incrementing the reference in qio_task_get_source is not necessary, since we're not running concurrently with any other code touching the QIOTask. This minimizes chances of further memory leaks. Reviewed-by: Eric Blake Signed-off-by: Daniel P. Berrange

[Qemu-devel] [PATCH v2 7/8] io: remove Error parameter from QIOTask thread worker

Now that task objects have a directly associated error, there's no need for an an Error **errp parameter to the QIOTask thread worker function. It already has a QIOTask object, so can directly set the error on it. Reviewed-by: Eric Blake Signed-off-by: Daniel P. Berrange

[Qemu-devel] [PATCH v2 3/8] io: fix typo in docs for QIOTask

The GDestroyNotify parameter is already a pointer, so does not need a '*' suffix on the type. Reviewed-by: Eric Blake Signed-off-by: Daniel P. Berrange --- include/io/task.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[Qemu-devel] [PATCH v2 0/8] io: enable DNS resolving separately of socket create

This is a followup of: v1: https://lists.gnu.org/archive/html/qemu-devel/2017-01/msg00574.html Currently DNS resolution of SocketAddress structs is done as part of the socket connect/listen process. This is very inflexible as it assumes that a single SocketAddress struct will only ever require

[Qemu-devel] [PATCH v2 1/8] sockets: add ability to disable DNS resolution for InetSocketAddress

Add a 'numeric' flag to the InetSocketAddress struct to allow the caller to indicate that DNS should be skipped for the host/port fields. This is useful if the caller knows the address is already numeric and wants to guarantee no (potentially blocking) DNS lookups are attempted. Signed-off-by:

Re: [Qemu-devel] [PULL 00/14] Block layer patches

On 9 January 2017 at 13:44, Kevin Wolf wrote: > The following changes since commit ffe22bf51065dd33022cf91f77a821d1f11c250d: > > Merge remote-tracking branch 'remotes/gonglei/tags/cryptodev-next-20161224' > into staging (2017-01-06 15:18:09 +) > > are available in the git

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