Re: [Qemu-devel] [RFC]virtio-blk: add disk-name device property

On 2017/1/12 10:22, Fam Zheng wrote: On Thu, 01/12 09:22, Yang Zhang wrote: On 2017/1/4 22:44, Stefan Hajnoczi wrote: On Tue, Jan 03, 2017 at 10:53:06AM -0600, Eric Blake wrote: On 12/29/2016 08:41 PM, Junkang Fu wrote: >From 74e913fc41ea98d1dde692175f1e3fb6729342aa Mon Sep 17 00:00:00 2001

[Qemu-devel] [PATCH RFC v2 09/12] vfio/ccw: get irqs info and set the eventfd fd

From: Xiao Feng Ren vfio-ccw resorts to the eventfd mechanism to communicate with userspace. We fetch the irqs info via the ioctl VFIO_DEVICE_GET_IRQ_INFO, register a event notifier to get the eventfd fd which is sent to kernel via the ioctl VFIO_DEVICE_SET_IRQS,

[Qemu-devel] [PATCH RFC v2 12/12] vfio/ccw: update sense data if a unit check is pending

Concurrent-sense data is currently not delivered. This patch stores the concurrent-sense data to the subchannel if a unit check is pending and the concurrent-sense bit is enabled. Then a TSCH can retreive the right IRB data back to the guest. Signed-off-by: Dong Jia Shi

[Qemu-devel] [PATCH RFC v2 08/12] vfio/ccw: get io region info

vfio-ccw provides an MMIO region for I/O operations. We fetch its information via ioctls here, then we can use it performing I/O instructions and retrieving I/O results later on. Signed-off-by: Xiao Feng Ren --- hw/vfio/ccw.c | 52

[Qemu-devel] [PATCH RFC v2 06/12] s390x/css: device support for s390-ccw passthrough

From: Xiao Feng Ren In order to support subchannels pass-through, we introduce a s390 subchannel device called "s390-ccw" to hold the real subchannel info. The s390-ccw devices inherit from the abstract CcwDevice which connect to the existing virtual-css-bus.

[Qemu-devel] [PATCH RFC v2 11/12] s390x/css: ccws translation infrastructure

From: Xiao Feng Ren Implement a basic infrastructure of handling channel I/O instruction interception for passed through subchannels: 1. Branch the code path of instruction interception handling by SubChannel type. 2. For a passed-through subchannel, issue the ORB

[Qemu-devel] [PATCH] doc/usb2: fix typo

Signed-off-by: Cao jin --- docs/usb2.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/usb2.txt b/docs/usb2.txt index c7a445afcd55..b9e75480737c 100644 --- a/docs/usb2.txt +++ b/docs/usb2.txt @@ -19,7 +19,7 @@ the controller so the USB 2.0 bus

[Qemu-devel] [PATCH RFC v2 03/12] s390x/css: add s390-map-css machine option

From: Xiao Feng Ren We want to support real (i.e. not virtual) channel devices even for guests that do not support MCSS-E (where guests may see devices from any channel subsystem image at once). As all virtio-ccw devices are in css 0xfe (and show up in the default

[Qemu-devel] [PATCH RFC v2 05/12] s390x/css: realize css_create_sch

The S390 virtual css support already has a mechanism to create a virtual subchannel and provide it to the guest. However, to pass-through subchannels to a guest, we need to introduce a new mechanism to create the subchannel according to the real device information. Thus we realize a new

[Qemu-devel] [PATCH RFC v2 10/12] s390x/css: introduce and realize ccw-request callback

From: Xiao Feng Ren Introduce a new callback on subchannel to handle ccw-request. Realize the callback in vfio-ccw device. Besides, resort to the event notifier handler to handling the ccw-request results. 1. Pread the I/O results via MMIO region. 2. Update the scsw

[Qemu-devel] [PATCH RFC v2 00/12] basic channel IO passthrough infrastructure based on vfio

The patch series introduce a basic channel I/O passthrough infrastructure based on vfio. - Focus on supporting dasd-eckd(cu_type/dev_type = 0x3990/0x3390) as the target device. - Support new qemu parameters in the style of: "-machine s390-ccw-virtio(,s390-map-css=on|off) ... -device

[Qemu-devel] [PATCH RFC v2 02/12] vfio: linux-headers update for vfio-ccw

From: Xiao Feng Ren This is a placeholder for a linux-headers update. Signed-off-by: Xiao Feng Ren --- include/standard-headers/asm-s390/vfio_ccw.h | 28 linux-headers/linux/vfio.h | 17

[Qemu-devel] [PATCH RFC v2 04/12] s390x/css: realize css_sch_build_schib

From: Xiao Feng Ren The S390 virtual css support already has a mechanism to build virtual Sub-Channel Information Block and provide virtual subchannels to the guest. However, to pass-through subchannels to a guest, we need to introduce a new mechanism to build its

[Qemu-devel] [PATCH RFC v2 07/12] vfio/ccw: vfio based subchannel passthrough driver

From: Xiao Feng Ren We use the IOMMU_TYPE1 of VFIO to realize the subchannels passthrough, implement a vfio based subchannels passthrough driver called "vfio-ccw". Support qemu parameters in the style of: "-device vfio-ccw,id=xx,hostid=xx(,guestid=xx),mdevid=xx"

[Qemu-devel] [PATCH RFC v2 15/15] vfio: ccw: introduce support for ccw0

Although Linux does not use format-0 channel command words (CCW0) these are a non-optional part of the platform spec, and for the sake of platform compliance, and possibly some non-Linux guests, we have to support CCW0. Making the kernel execute a format 0 channel program is too much hassle

[Qemu-devel] [PATCH RFC v2 14/15] docs: add documentation for vfio-ccw

Add file Documentation/s390/vfio-ccw.txt that includes details of vfio-ccw. Signed-off-by: Dong Jia Shi Acked-by: Pierre Morel --- Documentation/s390/00-INDEX | 2 + Documentation/s390/vfio-ccw.txt | 303

[Qemu-devel] [PATCH RFC v2 07/15] vfio: ccw: introduce ccw_io_region

To provide user-space a set of interfaces to: 1. pass in a ccw program to perform an I/O operation. 2. read back I/O results of the completed I/O operations. We introduce an MMIO region for the vfio-ccw device here. This region is defined to content: 1. areas to store arguments that an ssch

[Qemu-devel] [PATCH RFC v2 13/15] vfio: ccw: introduce a finite state machine

The current implementation doesn't check if the subchannel is in a proper device state when handling an event. Let's introduce a finite state machine to manage the state/event change. Signed-off-by: Dong Jia Shi --- drivers/s390/cio/Makefile | 2 +-

[Qemu-devel] [PATCH RFC v2 01/12] update-linux-headers: add asm-s390/vfio_ccw.h

Add asm-s390/vfio_ccw.h as a new standard header. Signed-off-by: Dong Jia Shi --- scripts/update-linux-headers.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh index 08c4c4a..67320be 100755 ---

[Qemu-devel] [PATCH RFC v2 12/15] vfio: ccw: return I/O results asynchronously

Introduce a singlethreaded workqueue to handle the I/O interrupts. With the work added to this queue, we store the I/O results to the io_region of the subchannel, then signal the userspace program to handle the results. Signed-off-by: Dong Jia Shi ---

[Qemu-devel] [PATCH RFC v2 11/15] vfio: ccw: introduce ioctls to get/set VFIO_CCW_IO_IRQ

Realize VFIO_DEVICE_GET_IRQ_INFO ioctl to retrieve VFIO_CCW_IO_IRQ information. Realize VFIO_DEVICE_SET_IRQS ioctl to set an eventfd fd for VFIO_CCW_IO_IRQ. Once a write operation to the ccw_io_region was performed, trigger a signal on this fd. Signed-off-by: Dong Jia Shi

[Qemu-devel] [PATCH RFC v2 05/15] vfio: ccw: introduce ccwprogram interfaces

Introduce ccwchain structure and helper functions that can be used to handle a ccw programs issued from a virtual machine. The following limitations apply: 1. Supports only prefetch enabled mode. 2. Supports idal(c64) ccw chaining. 3. Supports 4k idaw. 4. Supports ccw1. 5. Supports direct ccw

[Qemu-devel] [PATCH RFC v2 08/15] vfio: ccw: handle ccw command request

We implement the basic ccw command handling infrastructure here: 1. Translate the ccw commands. 2. Issue the translated ccw commands to the device. 3. Once we get the execution result, update the guest SCSW with it. Signed-off-by: Dong Jia Shi Acked-by: Pierre

[Qemu-devel] [PATCH RFC v2 09/15] vfio: ccw: realize VFIO_DEVICE_GET_REGION_INFO

Introduce device information about vfio-ccw: VFIO_DEVICE_FLAGS_CCW. Realize VFIO_DEVICE_GET_REGION_INFO ioctl for vfio-ccw. Signed-off-by: Dong Jia Shi Reviewed-by: Pierre Morel --- drivers/s390/cio/vfio_ccw_ops.c | 81

[Qemu-devel] [PATCH RFC v2 06/15] vfio: ccw: register vfio_ccw to the mediated device framework

To make vfio support subchannel devices, we need to leverage the mediated device framework to create a mediated device for the subchannel device. This registers the subchannel device to the mediated device framework during probe to enable mediated device creation. Signed-off-by: Dong Jia Shi

[Qemu-devel] [PATCH RFC v2 10/15] vfio: ccw: realize VFIO_DEVICE_RESET ioctl

Introduce VFIO_DEVICE_RESET ioctl for vfio-ccw to make it possible to hot-reset the device. We try to achieve a reset by first disabling the subchannel and then enabling it again: this should clear all state at the subchannel. Signed-off-by: Dong Jia Shi ---

[Qemu-devel] [PATCH RFC v2 02/15] s390: cio: export more interfaces

Export the common I/O interfaces those are needed by an I/O subchannel driver to actually talk to the subchannel. Signed-off-by: Dong Jia Shi Reviewed-by: Pierre Morel --- drivers/s390/cio/cio.c | 10 ++ 1 file changed, 10

[Qemu-devel] [PATCH RFC v2 03/15] vfio: ccw: define device_api strings

Define vfio-ccw device API strings. CCW vendor driver using mediated device framework should use this string for device_api attribute. Signed-off-by: Dong Jia Shi Reviewed-by: Pierre Morel --- include/uapi/linux/vfio.h | 1 + 1 file

[Qemu-devel] [PATCH RFC v2 04/15] vfio: ccw: basic implementation for vfio_ccw driver

To make vfio support subchannel devices, we need a css driver for the vfio subchannels. This patch adds a basic vfio-ccw subchannel driver for this purpose. To enable VFIO for vfio-ccw, enable S390_CCW_IOMMU config option and configure VFIO as required. Signed-off-by: Dong Jia Shi

[Qemu-devel] [PATCH RFC v2 00/15] basic vfio-ccw infrastructure

vfio-ccw: the basic infrastructure == Introduction Here we describe the vfio support for I/O subchannel devices for Linux/s390. Motivation for vfio-ccw is to passthrough subchannels to a virtual machine, while vfio is the means. Different than other

[Qemu-devel] [PATCH RFC v2 01/15] s390: cio: introduce cio_cancel_halt_clear

For future code reuse purpose, this decouples the cio code with the ccw device specific parts from ccw_device_cancel_halt_clear, and makes a new common I/O interface named cio_cancel_halt_clear. Signed-off-by: Dong Jia Shi Reviewed-by: Pierre Morel

Re: [Qemu-devel] [PATCH] Further tidy-up on block status

11.01.2017 22:00, Alex Bligh wrote: On 11 Jan 2017, at 15:31, Vladimir Sementsov-Ogievskiy wrote: If an error occurs, the server SHOULD set the appropriate error code in the error field of an error chunk. However, if the error does not involve invalid usage (such

[Qemu-devel] [PATCH V1 1/4] target-arm: Add support for PMU register PMSELR_EL0

This patch adds support for AArch64 register PMSELR_EL0. The existing PMSELR definition is revised accordingly. Signed-off-by: Wei Huang --- target/arm/cpu.h| 1 + target/arm/helper.c | 24 +++- 2 files changed, 20 insertions(+), 5 deletions(-) diff

[Qemu-devel] [PATCH V1 0/4] Add vPMU vPMU support under TCG mode

QEMU has implemented cycle count support for guest VM under TCG mode. But this feature is not complete. In fact using perf inside a 64-bit Linux guest VM (under TCG) can cause the following kernel panic because some PMU registers are not implemented. [ 329.445970] []

[Qemu-devel] [PATCH V1 2/4] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0

In order to support Linux perf, which uses PMXEVTYPER register, this patch adds access support for PMXEVTYPER_EL0. Signed-off-by: Wei Huang --- target/arm/helper.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c

[Qemu-devel] [PATCH V1 4/4] target-arm: Hook up TCG vPMU with CPU pmu option

Remove the checking of kvm_enabled(). With this, .pmu option can also control vPMU under TCG mode. Signed-off-by: Wei Huang --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f5cb30a..2f87a4b 100644

[Qemu-devel] [PATCH V1 3/4] target-arm: Add support for PMU register PMINTENSET_EL1

This patch adds access support for PMINTENSET_EL1. Signed-off-by: Wei Huang --- target/arm/helper.c | 8 1 file changed, 8 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9044a33..22c66e3 100644 --- a/target/arm/helper.c +++

Re: [Qemu-devel] vhost-user: fix crash when chardev-remove

Hi I tested on qemu-2.7.1 release version. test case: 1. host run ovs-dpdk. start vhost-user mode vm 2. chardev-add socket,id=char-client-002-2,path=/usr/local/var/run/openvswitch/client-002-2,server=on netdev_add vhost-user,id=client-002-2, ,chardev=char-client-002-2,vhostforce=on

Re: [Qemu-devel] [PATCH v2 2/2] memory: hmp: dump flat view for 'info mtree'

On Wed, Jan 11, 2017 at 06:13:11PM +0100, Paolo Bonzini wrote: > > > On 21/12/2016 08:58, Peter Xu wrote: > > Dumping flat view will be useful to debug the memory rendering logic, > > also it'll be much easier with it to know what memory region is handling > > what address range. > > > >

Re: [Qemu-devel] [PATCH v2 1/2] memory: provide common macros for mtree_print_mr()

On Wed, Jan 11, 2017 at 06:21:46PM +0100, Paolo Bonzini wrote: > > > On 21/12/2016 08:58, Peter Xu wrote: > > - mr->romd_mode ? 'R' : '-', > > - !mr->readonly && !(mr->rom_device && mr->romd_mode) ? > > 'W' > > -

Re: [Qemu-devel] [PATCH 00/11] POWER9 TCG enablements - part11

On Tue, Jan 10, 2017 at 02:20:32PM +0530, Nikunj A Dadhania wrote: > This series contains 10 new instructions for POWER9 ISA3.0 > VSX Scalar Insert Exponent > VSX Vector Insert Exponent > VSX Vector Extract Exponent/Significand > VSX Scalar Truncate & Convert Quad-Precision >

Re: [Qemu-devel] [PATCH qemu 2/2] spapr_pci: Advertise 16M IOMMU pages when available

On Mon, Jan 09, 2017 at 01:06:03PM +1100, Alexey Kardashevskiy wrote: > On 03/01/17 10:41, David Gibson wrote: > > On Thu, Dec 22, 2016 at 04:22:12PM +1100, Alexey Kardashevskiy wrote: > >> On sPAPR, IOMMU page size varies and if QEMU is running with RAM > >> backed with hugepages, we can

Re: [Qemu-devel] [PATCH 03/11] target-ppc: Add xsiexpdp instruction

On Thu, Jan 12, 2017 at 10:23:22AM +0530, Nikunj A Dadhania wrote: > David Gibson writes: > > > [ Unknown signature status ] > > On Tue, Jan 10, 2017 at 02:20:35PM +0530, Nikunj A Dadhania wrote: > >> xsiexpdp: VSX Scalar Insert Exponent Double Precision > >> > >>

Re: [Qemu-devel] [PATCH 03/11] target-ppc: Add xsiexpdp instruction

David Gibson writes: > [ Unknown signature status ] > On Tue, Jan 10, 2017 at 02:20:35PM +0530, Nikunj A Dadhania wrote: >> xsiexpdp: VSX Scalar Insert Exponent Double Precision >> >> Signed-off-by: Nikunj A Dadhania >> --- >>

Re: [Qemu-devel] [PATCH] linux-user: Use *at functions instead of caching interp_prefix contents

Hi, Your series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20170112040534.15179-1-...@twiddle.net Subject: [Qemu-devel] [PATCH] linux-user: Use *at functions instead of caching interp_prefix contents === TEST SCRIPT BEGIN ===

Re: [Qemu-devel] [PULL 00/30] target-sparc sun4v support

Hi, Your series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PULL 00/30] target-sparc sun4v support Message-id: 20170112025606.27332-1-...@twiddle.net === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log

Re: [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112

Hi, Your series seems to have some coding style problems. See output below for more information: Message-id: 20170112020327.24882-1-da...@gibson.dropbear.id.au Subject: [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 Type: series === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1

[Qemu-devel] [kvm-unit-tests PATCH v6 3/3] run_tests: allow run tests in parallel

run_task.sh is getting slow. This patch is trying to make it faster by running the tests concurrently. We provide a new parameter "-j" for the run_tests.sh, which can be used to specify how many run queues we want for the tests. Default queue length is 1, which is the old behavior. Quick test on

Re: [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part

On Tue, Jan 10, 2017 at 12:10:07AM -0200, Jose Ricardo Ziviani wrote: > v5: > - removes 'unlikely' gcc branch pred. hints from not unlikely places > - adds comments in host-utils functions > - adds more test cases for shift functions > - handles "shift backwards" with signed shifts > -

[Qemu-devel] Question about io mode & cache mode

Hello. I sent mail for question about io mode and cache mode. When I set VM to I/O mode = native and cache mode = none, Vm cannot boot and vm is turn off automatically. Why cannot VM boot?

[Qemu-devel] [kvm-unit-tests PATCH v6 2/3] run_tests: put logs into per-test file

We were using test.log before to keep all the test logs. This patch creates one log file per test case under logs/ directory with name "TESTNAME.log". Meanwhile, we will keep the last time log into logs.old/. Renaming scripts/functions.bash into scripts/common.bash to store some more global

Re: [Qemu-devel] [PATCH 03/11] target-ppc: Add xsiexpdp instruction

On Tue, Jan 10, 2017 at 02:20:35PM +0530, Nikunj A Dadhania wrote: > xsiexpdp: VSX Scalar Insert Exponent Double Precision > > Signed-off-by: Nikunj A Dadhania > --- > target/ppc/translate/vsx-impl.inc.c | 20 > target/ppc/translate/vsx-ops.inc.c

[Qemu-devel] [kvm-unit-tests PATCH v6 1/3] run_tests: fix errno for param parsing

Signed-off-by: Peter Xu --- run_tests.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/run_tests.sh b/run_tests.sh index 254129d..2cfa365 100755 --- a/run_tests.sh +++ b/run_tests.sh @@ -41,7 +41,7 @@ while getopts "g:hv" opt; do

[Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <660569980c8449b732c19338412af241f216a563.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

[Qemu-devel] [kvm-unit-tests PATCH v6 0/3] run_tests: support concurrent test execution

v6: - some tunes on how to rm/mv logs/logs.old [Drew] - fix errno to 2 when param parse fail [Drew] - add one more patch to fix *) case errno [Drew] (please either take/squash/... this one) - comment fix again [Drew] v5: - add "/" at start/end of line where proper [Drew] - remove useless

[Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine

From: Artyom Tarasenko Remove the Niagara stub implementation from sun4u.c and add a machine, compatible with Legion simulator from the OpenSPARC T1 project. The machine uses the firmware supplied with the OpenSPARC T1 project,

[Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs

From: Artyom Tarasenko In OpenSPARC T1+ TWINX ASIs in store instructions are aliased with Block Initializing Store ASIs. "UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them in the chapter "5.9 Block Initializing Store ASIs" Integer stores of all sizes are

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 2/2] run_tests: allow run tests in parallel

On Wed, Jan 11, 2017 at 02:09:34PM +0100, Andrew Jones wrote: > On Wed, Jan 11, 2017 at 12:00:23PM +0100, Andrew Jones wrote: > > On Wed, Jan 11, 2017 at 01:29:35PM +0800, Peter Xu wrote: > > > run_task.sh is getting slow. This patch is trying to make it faster by > > > running the tests

Re: [Qemu-devel] [PATCH v5 2/7] host-utils: Implement unsigned quadword left/right shift and unit tests

On Tue, Jan 10, 2017 at 08:34:29AM -0600, Eric Blake wrote: > On 01/09/2017 08:10 PM, Jose Ricardo Ziviani wrote: > > Implements 128-bit left shift and right shift as well as their > > testcases. By design, shift silently mods by 128, so the caller is > > responsible to assert the shift range if

[Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21)

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <6f546cf963e03ed253e16701ba6e30dcc5d00073.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 31

Re: [Qemu-devel] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction

On Tue, Jan 10, 2017 at 12:10:13AM -0200, Jose Ricardo Ziviani wrote: > bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the > number of bytes to truncate in vra, the return register will have vrb > with such bits truncated. > > Signed-off-by: Jose Ricardo Ziviani

Re: [Qemu-devel] [PATCH 00/11] POWER9 TCG enablements - part11

On Tue, Jan 10, 2017 at 02:20:32PM +0530, Nikunj A Dadhania wrote: > This series contains 10 new instructions for POWER9 ISA3.0 > VSX Scalar Insert Exponent > VSX Vector Insert Exponent > VSX Vector Extract Exponent/Significand > VSX Scalar Truncate & Convert Quad-Precision >

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 1/2] run_tests: put logs into per-test file

On Wed, Jan 11, 2017 at 11:46:38AM +0100, Andrew Jones wrote: [...] > > So, how about this: > > > > rm -rf $unittest_log_dir.old || err "Failed remove old logs" > > if [[ -d $unittest_log_dir ]]; then > > Only [ ... ] for tests like these I thought [[ ... ]] would be superior to [ ...

[Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <288f09c6282bf46af7ad8343fe63f7438a9f44a2.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH] linux-user: Use *at functions instead of caching interp_prefix contents

If the interp_prefix is a complete chroot, it may have a *lot* of files. Setting up the cache for this is quite expensive. Instead, use the *at versions of various syscalls to attempt the operation in the prefix. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 12

[Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <146ff5800a7da7599439d69c4bd907a0b51747aa.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- linux-user/main.c | 2 +-

[Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: Signed-off-by: Richard Henderson --- MAINTAINERS | 6 +++

[Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <2bf424bff7e4dee34fcbcada4fd490205f392823.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 22

[Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <70562e4ef094e2beb2c56380fdd0db7b15cc0294.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <6139718b8d11c9c893d6deb02431c615ef422d65.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/translate.c | 2 +- 1 file changed, 1

[Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <0293a0b12e38e253a3590cebeee517ee16cf24d8.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 51

[Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode

From: Artyom Tarasenko Accordinf to UA2005, 9.3.3 "Address Space Identifiers", "In hyperprivileged mode, all instruction fetches and loads and stores with implicit ASIs use a physical address, regardless of the value of TL". Signed-off-by: Artyom Tarasenko

[Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <5e6434c91c40b0acc4a8da12da2edc7a43b1dd7f.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 13 ++---

[Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left

From: Artyom Tarasenko Implement the behavior described in the chapter 13.9.11 of UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005: "If a TLB Data-In replacement is attempted with all TLB entries locked and valid, the last TLB entry (entry 63) is replaced."

Re: [Qemu-devel] [PATCH] nvdimm acpi: fix g_array_free() with NULL pointer

On 01/11/2017 05:36 PM, Stefan Hajnoczi wrote: Unlike g_free(), g_array_free() does not accept a NULL pointer argument. The following error is logged when an nvdimm device is realized: GLib-CRITICAL **: g_array_free: assertion 'array' failed Cc: Xiao Guangrong

[Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode

From: Artyom Tarasenko As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005, outstanding disrupting exceptions that are destined for privileged mode can only cause a trap when the virtual processor is in nonprivileged or privileged mode and PSTATE.ie = 1. At

[Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <7edada4d1c26562843de80c9eb2339ca591f883b.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 +

[Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <343d22b67790a08cd37bd66bfddeb1cad351ef43.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 30

[Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <036aeab15d1b655352ec81abdd8696d5d3579938.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 17 + 1 file

Re: [Qemu-devel] [PATCH] qemu-io: Return non-zero exit code on failure

On Wed, 01/11 15:51, Eric Blake wrote: > On 01/11/2017 12:24 PM, Nir Soffer wrote: > > From: Nir Soffer > > > > The result of openfile was not checked, leading to failure deep in the > > actual command with confusing error message, and exiting with exit code 0. > > > > Here

[Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode

From: Artyom Tarasenko Please note that QEMU doesn't impelement Real->Physical address translation. The "Real Address" is always the "Physical Address". Suggested-by: Richard Henderson Signed-off-by: Artyom Tarasenko Message-Id:

[Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers

From: Artyom Tarasenko Use explicit register pointers while accessing D/I-MMU registers. Call cpu_unassigned_access on access to missing registers. Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id:

[Qemu-devel] [PULL 26/30] target-sparc: store the UA2005 entries in sun4u format

From: Artyom Tarasenko According to chapter 13.3 of the UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005, only the sun4u format is available for data-access loads. Store UA2005 entries in the sun4u format to simplify processing. Signed-off-by: Artyom Tarasenko

[Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <0fcf7eca7c2d3e6bef7846027857da3bd681645d.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 64/67] target-ppc: Add xscvdpqp instruction

From: Bharata B Rao xscvdpqp: VSX Scalar Convert Double-Precision format to Quad-Precision format Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson

[Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <18b3a791b00745313e47347b5221ae7d534a7d36.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/mmu_helper.c | 18 +-

Re: [Qemu-devel] [PATCH v5 wave 1 0/4] fw-cfg: support writeable blobs and more files

On Wed, Jan 11, 2017 at 06:34:53PM +0100, Laszlo Ersek wrote: > This is the first (fw_cfg) half of the v5 iteration of the series posted > here: > . > > In this version, the fw_cfg patches have been separated into a >

[Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 4 1 file changed, 4

[Qemu-devel] [PULL 57/67] target-ppc: Add xsxexpqp instruction

From: Nikunj A Dadhania xsxexpqp: VSX Scalar Extract Exponent Quad Precision Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 15 +++

[Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <83b315e3527bef56741c84e6d4f98de9bea2c560.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 2 +

Re: [Qemu-devel] [RFC]virtio-blk: add disk-name device property

On Thu, 01/12 09:22, Yang Zhang wrote: > On 2017/1/4 22:44, Stefan Hajnoczi wrote: > > On Tue, Jan 03, 2017 at 10:53:06AM -0600, Eric Blake wrote: > > > On 12/29/2016 08:41 PM, Junkang Fu wrote: > > > > >From 74e913fc41ea98d1dde692175f1e3fb6729342aa Mon Sep 17 00:00:00 2001 > > > > From:

[Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode

From: Artyom Tarasenko while IMMU/DMMU is disabled - ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor - signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise Signed-off-by: Artyom Tarasenko Message-Id:

[Qemu-devel] [PULL 46/67] target-ppc: Add xxextractuw instruction

From: Nikunj A Dadhania xxextractuw: VSX Vector Extract Unsigned Word Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/helper.h | 1 + target/ppc/int_helper.c

[Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <3a6aaddd6f65e26b06e5616d9eeaddc7a62a2910.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/asi.h | 1 +

[Qemu-devel] [PULL 47/67] target-ppc: Add xxinsertw instruction

From: Nikunj A Dadhania xxinsertw: VSX Vector Insert Word Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/helper.h | 1 + target/ppc/int_helper.c | 25

[Qemu-devel] [PULL 61/67] pseries: Rewrite CAS PVR compatibility logic

During boot, PAPR guests negotiate CPU model support with the ibm,client-architecture-support mechanism. The logic to implement this in qemu is very convoluted. This cleans it up to be cleaner, using the new ppc_check_compat() call. The new logic for choosing a compatibility mode is: 1.

[Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <65e7ea6ea1cd0ebf291b1ed76d5cb1cccff2d49e.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 53/67] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64

From: Bharata B Rao Since helper_compute_fprf() works on float64 argument, rename it to helper_compute_fprf_float64(). Also use a macro to generate helper_compute_fprf_float64() so that float128 version of the same helper can be introduced easily later.

[Qemu-devel] [PULL 37/67] qtest: add netfilter tests for ppc64

From: Laurent Vivier Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Reviewed-by: Greg Kurz Tested-by: Greg Kurz Signed-off-by: David Gibson ---

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