Re: [Qemu-devel] [PATCH 06/18] nbd/client: refactor drop_sync

07.02.2017 02:19, Eric Blake wrote: On 02/03/2017 09:47 AM, Vladimir Sementsov-Ogievskiy wrote: Return 0 on success to simplify success checking. Signed-off-by: Vladimir Sementsov-Ogievskiy --- nbd/client.c | 35 +++ 1 file changed,

Re: [Qemu-devel] [PATCH] misc: edu: free dma timer in device unit

2017-02-08 14:53 GMT+08:00 Jiri Slaby : > On 02/08/2017, 04:40 AM, Li Qiang wrote: > > From: Li Qiang > > > > This can avoid a memory leak when hotplug and unplug. > > > > Signed-off-by: Li Qiang > > --- > > hw/misc/edu.c | 1 + > > 1 file

Re: [Qemu-devel] [PATCH] misc: edu: free dma timer in device unit

On 02/08/2017, 04:40 AM, Li Qiang wrote: > From: Li Qiang > > This can avoid a memory leak when hotplug and unplug. > > Signed-off-by: Li Qiang > --- > hw/misc/edu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/misc/edu.c b/hw/misc/edu.c >

[Qemu-devel] [PATCH v2 3/3] sd: sdhci: Remove block count enable check in single block transfers

From: Prasad J Pandit In the SDHCI protocol the 'Block count enable' bit of the Transfer Mode register is relevant only in multi block transfers. We need not check it in single block transfers. Signed-off-by: Prasad J Pandit --- hw/sd/sdhci.c |

[Qemu-devel] [PATCH v2 2/3] sd: sdhci: conditionally invoke multi block transfer

From: Prasad J Pandit In sdhci_write invoke multi block transfer if it is enabled in the transfer mode register 's->trnmod'. Signed-off-by: Prasad J Pandit --- hw/sd/sdhci.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH v2 0/3] sd: sdhci: correct transfer mode register usage

From: Prasad J Pandit Hello, In SDHCI protocol, the 'Block Count Enable' bit of the Transfer Mode register is used to control 's->blkcnt' value. One, this bit is not relevant in single block transfers. Second, Transfer Mode register value could be set such that

[Qemu-devel] [PATCH v2 1/3] sd: sdhci: check transfer mode register in multi block transfer

From: Prasad J Pandit In SDHCI device emulation the transfer mode register value is used during multi block transfer to check if block count register is enabled and should be updated. Transfer mode register could be set such that, block count register would not be

Re: [Qemu-devel] [virtio-dev] [PATCH v16 1/2] virtio-crypto: Add virtio crypto device specification

Hi Halil, Thanks for your comments firstly. > > On 01/18/2017 09:22 AM, Gonglei wrote: > > The virtio crypto device is a virtual crypto device (ie. hardware > > crypto accelerator card). Currently, the virtio crypto device provides > > the following crypto services: CIPHER, MAC, HASH, and AEAD.

[Qemu-devel] [RFC] virtio-pci: Allow PCIe virtio devices on root bus

Marcel, Your original patch adding PCIe support to virtio-pci.c has the limitation noted below that PCIe won't be enabled if the device is on the root bus (rather than under a root or downstream port). As reasoned below, I think removing the check is correct, even for x86 (though it would rarely

Re: [Qemu-devel] [PATCH v12 14/16] file-posix: Implement image locking

On Wed, 02/08 04:05, Max Reitz wrote: > > +static int raw_lt_write_to_write_share(RawLockTransOp op, > > + int old_lock_fd, int new_lock_fd, > > + BDRVRawLockMode old_lock, > > +

[Qemu-devel] [PATCH V7 1/2] Add a new qmp command to start/stop replication

We can call this qmp command to start/stop replication outside of qemu. Like Xen colo need this function. Signed-off-by: Zhang Chen Signed-off-by: Wen Congyang Reviewed-by: Eric Blake Reviewed-by: Stefano Stabellini

[Qemu-devel] [PATCH V7 0/2] Add new qmp commands to suppurt Xen COLO

Xen COLO depend on qemu COLO replication function. So, We need new qmp commands for Xen to use qemu replication. Corresponding libxl patches already in xen.git. Commit ID: ed37ef1f91c20f0ab162ce60f8c38400b917fa64 COLO: introduce new API to prepare/start/do/get_error/stop replication

[Qemu-devel] [PATCH V7 2/2] Add a new qmp command to do checkpoint, query xen replication status

We can call this qmp command to do checkpoint outside of qemu. Xen colo will need this function. Signed-off-by: Zhang Chen Signed-off-by: Wen Congyang --- migration/colo.c | 17 qapi-schema.json | 60

Re: [Qemu-devel] [PATCH 1/2] sd: sdhci: check transfer mode register in multi block transfer

Hello Alistair, +-- On Tue, 7 Feb 2017, Alistair Francis wrote --+ | As it doesn't look like we have ever supported an infinite transfer | and we don't want infinite loops occurring I think we should add an | unsupported print statement here saying that we don't support infinite | transfers and

Re: [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage

+-- On Tue, 7 Feb 2017, Alistair Francis wrote --+ | > === | > diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | > index d921423..7f3d547 100644 | > --- a/hw/sd/sdhci.c | > +++ b/hw/sd/sdhci.c | > @@ -1019,7 +1019,11 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, | > unsigned size) | >

[Qemu-devel] [PATCH v7 1/2] block/vxhs.c: Add support for a new block device type called "vxhs"

From: Ashish Mittal Source code for the qnio library that this code loads can be downloaded from: https://github.com/VeritasHyperScale/libqnio.git Sample command line using JSON syntax: ./x86_64-softmmu/qemu-system-x86_64 -name instance-0008 -S -vnc 0.0.0.0:0 -k

[Qemu-devel] [PATCH v7 2/2] block/vxhs.c: Add qemu-iotests for new block device type "vxhs"

From: Ashish Mittal These changes use a vxhs test server that is a part of the following repository: https://github.com/VeritasHyperScale/libqnio.git Signed-off-by: Ashish Mittal --- v7 changelog: (1) No changes. v6 changelog: (1) Added

[Qemu-devel] Question about QEMU's threading model and stacking multiple block drivers

We’ve implemented a block driver that exposes storage to QEMU VMs. Our block driver (O) is interposing on writes to some other type of storage (B). O performs low latency replication and then asynchronously issues the write to the backing block driver, B, using bdrv_aio_writev(). Our problem is

Re: [Qemu-devel] [virtio-dev] [PATCH v16 1/2] virtio-crypto: Add virtio crypto device specification

Hi Cornelia, > > On Tue, 7 Feb 2017 12:39:44 +0100 > Halil Pasic wrote: > > > On 01/18/2017 09:22 AM, Gonglei wrote: > > > > +\section{Crypto Device}\label{sec:Device Types / Crypto Device} > > > + > > > +The virtio crypto device is a virtual cryptography device as

[Qemu-devel] [PATCH] misc: edu: free dma timer in device unit

From: Li Qiang This can avoid a memory leak when hotplug and unplug. Signed-off-by: Li Qiang --- hw/misc/edu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/edu.c b/hw/misc/edu.c index 401039c..7565552 100644 --- a/hw/misc/edu.c +++

Re: [Qemu-devel] [PATCH v12 14/16] file-posix: Implement image locking

On 23.01.2017 13:30, Fam Zheng wrote: > This implements open flag sensible image locking for local file > and host device protocol. > > virtlockd in libvirt locks the first byte, so we start looking at the > file bytes from 1. > > Quoting what was proposed by Kevin Wolf , there

Re: [Qemu-devel] [PATCH v7 08/17] intel_iommu: convert dbg macros to trace for trans

On 2017年02月07日 16:28, Peter Xu wrote: Another patch to convert the DPRINTF() stuffs. This patch focuses on the address translation path and caching. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 69 ++-

Re: [Qemu-devel] [PATCH v7 07/17] intel_iommu: convert dbg macros to traces for inv

On 2017年02月07日 16:28, Peter Xu wrote: VT-d codes are still using static DEBUG_INTEL_IOMMU macro. That's not good, and we should end the day when we need to recompile the code before getting useful debugging information for vt-d. Time to switch to the trace system. This is the first patch to do

[Qemu-devel] [PATCH] usb: ehci: fix memory leak in ehci

From: Li Qiang In usb_ehci_init function, it initializes 's->ipacket', but there is no corresponding function to free this. As the ehci can be hotplug and unplug, this will leak host memory leak. In order to make the hierarchy clean, we should add a ehci pci finalize function,

Re: [Qemu-devel] [PATCH V6 2/2] Add a new qmp command to do checkpoint, query xen replication status

On 02/07/2017 11:50 PM, Eric Blake wrote: On 01/05/2017 12:08 AM, Zhang Chen wrote: We can call this qmp command to do checkpoint outside of qemu. Xen colo will need this function. Signed-off-by: Zhang Chen Signed-off-by: Wen Congyang

Re: [Qemu-devel] [PATCH v3] softfloat: Add round-to-odd rounding mode

On 02/05/2017 09:55 PM, Bharata B Rao wrote: Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-odd rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If

[Qemu-devel] [Bug 1662050] Re: qemu-img convert a overlay qcow2 image into a entire image

@Thomas Huth, when we use qemu-img to convert a image "A" and will get a new image "B" which is equivalent to "A" . But "B" may be a lot different from "A",such as file size. The file size of "B" is usually less than "A" and this is very valuable to me. So I can't simply do a "cp delta.qcow2

Re: [Qemu-devel] [Bug 1662468] Re: [feature request] qemu-img convert should respond to control-T like dd

On 02/08/17 00:22, Max Reitz wrote: > That should be simple enough to implement considering we have this > behavior already on SIGUSR1. Unfortunately, I wouldn't be able to test > it because Linux apparently doesn't implement SIGINFO... > > Max > > > PS: By the way, thanks for the information.

Re: [Qemu-devel] [PATCH v12 13/16] tests: Disable image lock in test-replication

On 23.01.2017 13:30, Fam Zheng wrote: > The COLO block replication architecture requires one disk to be shared > between primary and secondary, in the test both processes use posix file > protocol (instead of over NBD) so it is affected by image locking. > Disable the lock. > > Signed-off-by: Fam

Re: [Qemu-devel] [PATCH v2] scripts: add "git.orderfile" for ordering diff hunks by pathname patterns

On 02/07/17 20:20, Eric Blake wrote: > On 12/02/2016 03:01 PM, Laszlo Ersek wrote: >> When passed to git-diff (and to every other git command producing diffs >> and/or diffstats) with "-O" or "diff.orderFile", this list of patterns >> will place the more declarative / abstract hunks first, while

Re: [Qemu-devel] [PATCH RFC] acpi: add reset register to fadt

On 02/07/17 22:02, Phil Dennis-Jordan wrote: > On 7 February 2017 at 20:54, Laszlo Ersek wrote: >> I filed . > > That looks nice and thorough. > >>> Your EDK2 patch >> >> For the record: >> [1]

Re: [Qemu-devel] [PATCH v5 05/10] ACPI: Add Virtual Machine Generation ID support

On 02/05/17 10:12, b...@skyportsystems.com wrote: > From: Ben Warren > > This implements the VM Generation ID feature by passing a 128-bit > GUID to the guest via a fw_cfg blob. > Any time the GUID changes, an ACPI notify event is sent to the guest > > The user

Re: [Qemu-devel] [RFC PATCH v1 2/2] softfloat: Add float128_to_uint32_round_to_zero()

On Tue, Feb 07, 2017 at 02:10:04PM -0800, Richard Henderson wrote: > On 02/07/2017 12:04 AM, Bharata B Rao wrote: > > +int64_t v; > > +uint32_t res; > > +int old_exc_flags = get_float_exception_flags(status); > > + > > +v = float128_to_uint64_round_to_zero(a, status); > > +if

Re: [Qemu-devel] [PATCH v12 12/16] tests: Use null-co:// instead of /dev/null as the dummy image

On 23.01.2017 13:30, Fam Zheng wrote: > Signed-off-by: Fam Zheng > --- > tests/drive_del-test.c| 2 +- > tests/nvme-test.c | 2 +- > tests/usb-hcd-uhci-test.c | 2 +- > tests/usb-hcd-xhci-test.c | 2 +- > tests/virtio-blk-test.c | 2 +- > tests/virtio-scsi-test.c

Re: [Qemu-devel] [PATCH] link to .xz files to save some bandwidth

Quoting Paolo Bonzini (2017-02-07 09:59:56) > I have converted all .gz and .bz2 files to .xz on download.qemu.org > and this patch would change the links in the website. This would save > about 5 GB of bandwidth every day (about 20% savings). > > xz should be available for all platforms.

Re: [Qemu-devel] [PATCH v12 11/16] iotests: 172: Use separate images for multiple devices

On 23.01.2017 13:30, Fam Zheng wrote: > To avoid image lock failures. > > Signed-off-by: Fam Zheng > --- > tests/qemu-iotests/172 | 53 > -- > tests/qemu-iotests/172.out | 50 ++- > 2 files

Re: [Qemu-devel] [PATCH v12 10/16] iotests: 091: Quit QEMU before checking image

On 23.01.2017 13:30, Fam Zheng wrote: > Signed-off-by: Fam Zheng > --- > tests/qemu-iotests/091 | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/tests/qemu-iotests/091 b/tests/qemu-iotests/091 > index 32bbd56..10ac4a8 100755 > --- a/tests/qemu-iotests/091 > +++

Re: [Qemu-devel] [PATCH v12 09/16] iotests: 085: Avoid image locking conflict

On 23.01.2017 13:30, Fam Zheng wrote: > In the case where we test the expected error when a blockdev-snapshot > target already has a backing image, backing chain is opened multiple *the backing chain > times. This will be a problem when we use image locking, so use a > different backing file

Re: [Qemu-devel] [PATCH v12 08/16] iotests: 087: Don't attach test image twice

On 23.01.2017 13:30, Fam Zheng wrote: > The test scenario doesn't require the same image, instead it focuses on > the duplicated node-name, so use null-co to avoid locking conflict. > > Signed-off-by: Fam Zheng > --- > tests/qemu-iotests/087 | 6 ++ > 1 file changed, 2

Re: [Qemu-devel] [PATCH v12 07/16] iotests: 030: Read-only open image for getting map

On 23.01.2017 13:30, Fam Zheng wrote: > Signed-off-by: Fam Zheng > --- > tests/qemu-iotests/030 | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Max Reitz (As always, took a couple of retries to let test 030 pass for me...)

Re: [Qemu-devel] [PATCH v12 06/16] iotests: 055: Don't attach the drive to vm for drive-backup

On 23.01.2017 13:30, Fam Zheng wrote: > Signed-off-by: Fam Zheng > --- > tests/qemu-iotests/055 | 32 ++-- > 1 file changed, 18 insertions(+), 14 deletions(-) Reviewed-by: Max Reitz signature.asc Description: OpenPGP digital

[Qemu-devel] [PATCH] progress: Show current progress on SIGINFO

Currently we only print progress information on retrieval of SIGUSR1. Some systems have a dedicated SIGINFO for this, however, so it should be handled appropriately if it is available. Buglink: https://bugs.launchpad.net/qemu/+bug/1662468 Signed-off-by: Max Reitz --- Can

Re: [Qemu-devel] [PATCH] Makefile: Make "install" depend on "trace-events-all"

On 02/07/2017 07:14 AM, Stefan Hajnoczi wrote: > On Sat, Feb 04, 2017 at 10:32:45PM +0800, Fam Zheng wrote: >> We install this file to data dir but since 0ab8ed18 it's no longer >> required by any objects during "make". List it explicitly as a depended >> target of install and fix the broken "make

Re: [Qemu-devel] [qcow2] how to avoid qemu doing lseek(SEEK_DATA/SEEK_HOLE)?

Hi, I've been thinking about the issue but I'm not sure I've come to a resolution you'll like much. I'm not really in favor of optimizing code for ZFS, especially if that means worse code for every other case. I think it very much makes sense to assume that lseek(SEEK_{DATA,HOLE}) is faster than

[Qemu-devel] [Bug 1662468] Re: [feature request] qemu-img convert should respond to control-T like dd

That should be simple enough to implement considering we have this behavior already on SIGUSR1. Unfortunately, I wouldn't be able to test it because Linux apparently doesn't implement SIGINFO... Max PS: By the way, thanks for the information. I didn't know about SIGINFO at all. Well, now I

Re: [Qemu-devel] [PATCH v3 RFC] block/vxhs: Initial commit to add Veritas HyperScale VxHS block device support

Hi Stefan, Patch V7, which I plan to submit soon, will have fixes to all the issues you pointed out in reply to - [PATCH v6 1/2] block/vxhs.c: Add support for a new block device type called "vxhs" It will also have the QEMUBH patch you provided. Thanks, Ashish On Tue, Nov 15, 2016 at 12:51

Re: [Qemu-devel] [PATCH 2/2] sd: sdhci: block count enable not relevant in single block transfer

On Tue, Jan 31, 2017 at 4:24 AM, P J P wrote: > From: Prasad J Pandit > > In SDHCI device emulation the 'Block count enable' bit Can you say 'In the SDHCI protocol' instead of 'SDHCI device emulation'? I feel like saying device emulation makes it

Re: [Qemu-devel] [PATCH 1/2] sd: sdhci: check transfer mode register in multi block transfer

On Tue, Jan 31, 2017 at 4:24 AM, P J P wrote: > From: Prasad J Pandit > > In SDHCI device emulation the transfer mode register value > is used during multi block transfer to check if block count > register is enabled and should be updated. Transfer

Re: [Qemu-devel] [PATCH v6 2/2] block/vxhs.c: Add qemu-iotests for new block device type "vxhs"

I plan to submit v7 soon, therefore going over any unanswered emails at this time. On Tue, Nov 8, 2016 at 12:44 PM, Jeff Cody wrote: > On Mon, Nov 07, 2016 at 04:59:45PM -0800, Ashish Mittal wrote: >> These changes use a vxhs test server that is a part of the following >>

Re: [Qemu-devel] [PATCH 08/18] hbitmap: add next_zero function

On 02/03/2017 09:47 AM, Vladimir Sementsov-Ogievskiy wrote: > The function searches for next zero bit. > Also add interface for BdrvDirtyBitmap. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- > block/dirty-bitmap.c | 5 + >

Re: [Qemu-devel] [RFC PATCH 1/9] spapr: fix off-by-one error in spapr_ovec_populate_dt()

On Tue, Feb 07, 2017 at 04:12:47PM -0600, Michael Roth wrote: > Quoting Sam Bobroff (2017-02-06 20:56:44) > > The last byte of the option vector was missing due to an off-by-one > > error. Without this fix, client architecture support negotiation will > > fail because the last byte of option

Re: [Qemu-devel] [PATCH v2 1/1] target-ppc, tcg: fix usermode segfault with pthread_create()

Quoting Sam Bobroff (2017-02-06 21:21:39) > Programs run under qemu-ppc64 on an x86_64 host currently segfault > if they use pthread_create() due to the adjustment made to the NIP in > commit bd6fefe71cec5a0c7d2be4ac96307f25db56abf9. > > This patch changes cpu_loop() to set the NIP back to the >

Re: [Qemu-devel] [PATCH v1 3/6] qemu-img: add support for -n arg to dd command

First, because this is perhaps the most important thing: I think I remembered what the original proposal to solve all this mess, or at least move it to a later point: We wanted to just disallow overwriting existing files without conv=notrunc. I think. The thing is that it's pretty much

Re: [Qemu-devel] [RFC PATCH 1/9] spapr: fix off-by-one error in spapr_ovec_populate_dt()

Quoting Sam Bobroff (2017-02-06 20:56:44) > The last byte of the option vector was missing due to an off-by-one > error. Without this fix, client architecture support negotiation will > fail because the last byte of option vector 5, which contains the MMU > support, will be missed. > >

Re: [Qemu-devel] [RFC PATCH v1 2/2] softfloat: Add float128_to_uint32_round_to_zero()

On 02/07/2017 12:04 AM, Bharata B Rao wrote: +int64_t v; +uint32_t res; +int old_exc_flags = get_float_exception_flags(status); + +v = float128_to_uint64_round_to_zero(a, status); +if (v > 0x) { v should be uint64_t. r~

Re: [Qemu-devel] [PATCH v5 04/10] ACPI: Add vmgenid storage entries to the build tables

On 02/05/17 10:11, b...@skyportsystems.com wrote: > From: Ben Warren > > This allows them to be centrally initialized and destroyed > > Signed-off-by: Ben Warren > --- > hw/acpi/aml-build.c | 2 ++ > include/hw/acpi/aml-build.h | 1 + >

Re: [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage

On Tue, Feb 7, 2017 at 11:12 AM, P J P wrote: > +-- On Tue, 7 Feb 2017, Peter Maydell wrote --+ > | On 31 January 2017 at 12:24, P J P wrote: > | > In SDHCI emulation, the 'Block Count Enable' bit of the Transfer Mode > | > register is used to control

[Qemu-devel] [PATCH V3 4/4] target-arm: Enable vPMU support under TCG mode

This patch contains several fixes to enable vPMU under TCG mode. It first removes the checking of kvm_enabled() while unsetting ARM_FEATURE_PMU. With it, the .pmu option can be used to turn on/off vPMU under TCG mode. Secondly the PMU node of DT table is now created under TCG. The last fix is to

[Qemu-devel] [PATCH V3 2/4] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0

In order to support Linux perf, which uses PMXEVTYPER register, this patch adds read/write access support for PMXEVTYPER. The access is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally this patch adds support for PMXEVTYPER_EL0. Signed-off-by: Wei Huang ---

[Qemu-devel] [PATCH V3 1/4] target-arm: Add support for PMU register PMSELR_EL0

This patch adds support for AArch64 register PMSELR_EL0. The existing PMSELR definition is revised accordingly. Signed-off-by: Wei Huang Reviewed-by: Peter Maydell --- target/arm/cpu.h| 1 + target/arm/helper.c | 25 - 2

[Qemu-devel] [PATCH V3 0/4] Add vPMU vPMU support under TCG mode

QEMU has implemented cycle count support for guest VM under TCG mode. But this feature is not complete. In fact using perf inside a 64-bit Linux guest VM (under TCG) can cause the following kernel panic because some PMU registers are not implemented. [ 329.445970] []

[Qemu-devel] [PATCH V3 3/4] target-arm: Add support for PMU register PMINTENSET_EL1

This patch adds access support for PMINTENSET_EL1. Signed-off-by: Wei Huang Reviewed-by: Peter Maydell --- target/arm/cpu.h| 2 +- target/arm/helper.c | 10 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git

Re: [Qemu-devel] How to find backing file for qemu-nbd?

Yes, it is what i'm doing now: ps -C qemu-nbd -o cmd='. Thanks! -- Nikolay Ivanets Mobile: +380979184774 Skype: n_ivanets 2017-02-07 17:36 GMT+02:00 Eric Blake : > On 02/07/2017 08:25 AM, Nikolay Ivanets wrote: > > Is there any way to find source file supplied

Re: [Qemu-devel] [PATCH RFC] acpi: add reset register to fadt

On 7 February 2017 at 20:54, Laszlo Ersek wrote: > On 02/06/17 17:30, Phil Dennis-Jordan wrote: >> Thanks for the in-depth reply - apologies for abandoning the thread >> for a few days. Looks like a bunch of things have already been hashed >> out, but I have a few more

Re: [Qemu-devel] [PATCH v5 03/10] docs: VM Generation ID device description

On 02/05/17 10:11, b...@skyportsystems.com wrote: > From: Ben Warren > > This patch is based off an earlier version by > Gal Hammer (gham...@redhat.com) > > Requirements section, ASCII diagrams and overall help > provided by Laszlo Ersek (ler...@redhat.com) > >

Re: [Qemu-devel] [PATCH v5 02/10] linker-loader: Add new 'write pointer' command

On 02/07/17 13:11, Igor Mammedov wrote: > On Mon, 6 Feb 2017 19:31:24 +0200 > "Michael S. Tsirkin" wrote: > >> On Mon, Feb 06, 2017 at 09:16:25AM -0800, Ben Warren wrote: > @@ -257,8 +263,11 @@ void bios_linker_loader_add_pointer(BIOSLinker > *linker, > const

Re: [Qemu-devel] [PATCH 07/18] nbd: Minimal structured read for client

On 02/03/2017 09:47 AM, Vladimir Sementsov-Ogievskiy wrote: > Minimal implementation: always send DF flag, to not deal with fragmented > replies. This works well with your minimal server implementation, but I worry that it will cause us to fall over when talking to a fully-compliant server that

Re: [Qemu-devel] [PATCH v5 01/10] ACPI: Add a function for building named qword entries

On 02/07/17 14:51, Igor Mammedov wrote: > On Sun, 5 Feb 2017 01:11:56 -0800 > b...@skyportsystems.com wrote: > >> From: Ben Warren >> >> This is initially used to patch a 64-bit address into >> the VM Generation ID SSDT >> >> Signed-off-by: Ben Warren

Re: [Qemu-devel] [PATCH 06/22] char: add a /chardevs container

Hi - Original Message - > > > On 02/02/2017 15:51, Marc-André Lureau wrote: > > +if (QTAILQ_IN_USE(chr, next)) { > > +QTAILQ_REMOVE(, chr, next); > > +} > > +if (OBJECT(chr)->parent) { > > +object_unparent(OBJECT(chr)); > > +} else { > > +

Re: [Qemu-devel] [PATCH 05/22] main: free root container

Hi - Original Message - > > > On 02/02/2017 15:51, Marc-André Lureau wrote: > > This should eventually free all objects that are only referenced by > > their parents. > > > > Signed-off-by: Marc-André Lureau > > --- > > vl.c | 1 + > > 1 file changed, 1

Re: [Qemu-devel] [PATCH RFC] acpi: add reset register to fadt

On 02/06/17 17:30, Phil Dennis-Jordan wrote: > Thanks for the in-depth reply - apologies for abandoning the thread > for a few days. Looks like a bunch of things have already been hashed > out, but I have a few more comments: Vice versa... Sorry about responding a bit late. Yesterday I severely

[Qemu-devel] [PULL v2 00/13] target-arm queue

' into staging (2017-02-07 15:29:26 +) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207-1 for you to fetch changes up to aecfbbc97a2e52bbee34a53c32f961a182046a95: stellaris: Use the 'unimplemented' device for parts we don't

Re: [Qemu-devel] [PATCH v2] scripts: add "git.orderfile" for ordering diff hunks by pathname patterns

On 12/02/2016 03:01 PM, Laszlo Ersek wrote: > When passed to git-diff (and to every other git command producing diffs > and/or diffstats) with "-O" or "diff.orderFile", this list of patterns > will place the more declarative / abstract hunks first, while changes to > imperative code / details will

Re: [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage

+-- On Tue, 7 Feb 2017, Peter Maydell wrote --+ | On 31 January 2017 at 12:24, P J P wrote: | > In SDHCI emulation, the 'Block Count Enable' bit of the Transfer Mode | > register is used to control 's->blkcnt' value. One, this bit is not | > relevant in single block transfers.

Re: [Qemu-devel] [PULL 00/13] target-arm queue

Hi, Your series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PULL 00/13] target-arm queue Message-id: 1486492645-27803-1-git-send-email-peter.mayd...@linaro.org === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1

Re: [Qemu-devel] [PULL 00/13] target-arm queue

branch 'remotes/juanquintela/tags/migration/20170206' > into staging (2017-02-07 15:29:26 +) > > are available in the git repository at: > > git://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20170207 > > for you to fetch changes up to 7727b

[Qemu-devel] [PULL 02/13] wdt: Add Aspeed watchdog device model

From: Cédric Le Goater The Aspeed SoC includes a set of watchdog timers using 32-bit decrement counters, which can be based either on the APB clock or a 1 MHz clock. The watchdog timer is designed to prevent system deadlock and, in general, it should be restarted before timeout.

[Qemu-devel] [PULL 01/13] integratorcp: adding vmstate for save/restore

From: Pavel Dovgalyuk VMState added by this patch preserves correct loading of the integratorcp device state. Signed-off-by: Pavel Dovgalyuk Message-id: 20170131114310.6768.79416.stgit@PASHA-ISP [PMM: removed unnecessary

[Qemu-devel] [PULL 06/13] target/arm: Add cfgend parameter for ARM CPU selection.

From: Julian Brown Add a new "cfgend" property which selects whether the CPU resets into big-endian mode or not. This setting affects whether we reset with SCTLR_B (ARMv6 and earlier) or SCTLR_EE (ARMv7 and later) set. Signed-off-by: Julian Brown

[Qemu-devel] [PULL 08/13] arm: Correctly handle watchpoints for BE32 CPUs

From: Julian Brown In BE32 mode, sub-word size watchpoints can fail to trigger because the address of the access is adjusted in the opcode helpers before being compared with the watchpoint registers. This patch reverses the address adjustment before performing the

[Qemu-devel] [PULL 03/13] aspeed: add a watchdog controller

From: Cédric Le Goater This enables reboot of a guest from U-Boot and Linux. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 1485452251-1593-3-git-send-email-...@kaod.org Signed-off-by: Peter Maydell

[Qemu-devel] [PULL 05/13] hw/arm/integratorcp: Support specifying features via -cpu

From: Julian Brown Since the integratorcp board creates the CPU object directly rather than via cpu_arm_init(), we have to call the CPU class parse_features() method ourselves if we want to support the user passing features via the -cpu command line argument as well as

[Qemu-devel] [PULL 04/13] sd: sdhci: check data length during dma_memory_read

From: Prasad J Pandit While doing multi block SDMA transfer in routine 'sdhci_sdma_transfer_multi_blocks', the 's->fifo_buffer' starting index 'begin' and data length 's->data_count' could end up to be same. This could lead to an OOB access issue. Correct transfer data

[Qemu-devel] [PATCH 5/5] m68k: manage memory block

Add a new risu op to restore modified address register (OP_NORMALIZE) and allow to manage several registers in the memory block Signed-off-by: Laurent Vivier --- m68k.risu | 98 + risu.h | 1 +

[Qemu-devel] [PULL 11/13] stellaris: Document memory map and which SoC devices are unimplemented

Add a comment documenting the memory map of the SoC devices and which are not implemented. Signed-off-by: Peter Maydell Message-id: 1484247815-15279-2-git-send-email-peter.mayd...@linaro.org --- hw/arm/stellaris.c | 34 ++ 1 file

[Qemu-devel] [PULL 10/13] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts

Add support for generating the ISS (Instruction Specific Syndrome) for Data Abort exceptions taken from AArch32. These syndromes are used by hypervisors for example to trap and emulate memory accesses. This is the equivalent for AArch32 guests of the work done for AArch64 guests in commit

[Qemu-devel] [PULL 07/13] Fix Thumb-1 BE32 execution and disassembly.

From: Julian Brown Thumb-1 code has some issues in BE32 mode (as currently implemented). In short, since bytes are swapped within words at load time for BE32 executables, this also swaps pairs of adjacent Thumb-1 instructions. This patch un-swaps those pairs of

[Qemu-devel] [PATCH 2/5] m68k: implement server and client side

This also adds the basic test file and the configuration update. This implementation can only test instructions with values in register and no memory access. Signed-off-by: Laurent Vivier --- configure | 6 ++- risu_m68k.c | 153

[Qemu-devel] [PULL 09/13] target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode

In the ARM ldr/str decode path, rather than directly testing "insn & (1 << 21)" and "insn & (1 << 24)", abstract these bits out into wbit and pbit local flags. (We will want to do more tests against them to determine whether we need to provide syndrome information.) Signed-off-by: Peter Maydell

[Qemu-devel] [PATCH 4/5] m68k: add instruction needing an extended word

Some instructions are encoded on more than 32 bits. To be able to add this word, we introduce a new keyword: "post". This keyword adds a block to be executed after the instruction generation. Signed-off-by: Laurent Vivier --- m68k.risu | 42

[Qemu-devel] [PULL 12/13] hw/misc: New "unimplemented" sysbus device

Create a new "unimplemented" sysbus device, which simply accepts all read and write accesses, and implements them as read-as-zero, write-ignored, with logging of the access as LOG_UNIMP. This is useful for stubbing out bits of an SoC or board model which haven't been written yet. Signed-off-by:

[Qemu-devel] [PULL 13/13] stellaris: Use the 'unimplemented' device for parts we don't implement

Use the 'unimplemented' dummy device to cover regions of the SoC device memory map which we don't have proper device implementations for yet. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id:

[Qemu-devel] [PULL 00/13] target-arm queue

repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207 for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd: stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:30:00 +

[Qemu-devel] [PATCH 1/5] m68k: implement risugen module

--- risugen_m68k.pm | 295 1 file changed, 295 insertions(+) create mode 100644 risugen_m68k.pm diff --git a/risugen_m68k.pm b/risugen_m68k.pm new file mode 100644 index 000..a9a4341 --- /dev/null +++ b/risugen_m68k.pm @@ -0,0 +1,295

[Qemu-devel] [PATCH 3/5] m68k: add risufile with m68k instructions.

Add a set of instructions working only on registers. Signed-off-by: Laurent Vivier --- m68k.risu | 241 ++ 1 file changed, 241 insertions(+) create mode 100644 m68k.risu diff --git a/m68k.risu b/m68k.risu new file

[Qemu-devel] [PATCH 0/5] risu: add m68k target support

This series add the files needed to test the m68k target. For the moment, it doesn't support FPU instructions. Laurent Vivier (5): m68k: implement risugen module m68k: implement server and client side m68k: add risufile with m68k instructions. m68k: add instruction needing an extended

Re: [Qemu-devel] [PULL 0/6] Migration pull

On 7 February 2017 at 07:50, Juan Quintela wrote: > Peter Maydell wrote: >> On 6 February 2017 at 16:51, Juan Quintela wrote: > > >> I get a test failure on aarch64 host on one of the ppc guest tests: >> >> TEST:

Re: [Qemu-devel] [PATCH 03/18] nbd: Minimal structured read for server

On 07/02/2017 00:01, Eric Blake wrote: > On 02/03/2017 09:47 AM, Vladimir Sementsov-Ogievskiy wrote: >> Minimal implementation of structured read: one data chunk + finishing >> none chunk. No segmentation. >> Minimal structured error implementation: no text message. >> Support DF flag, but just

Re: [Qemu-devel] [PATCH 1/3] stellaris: Document memory map and which SoC devices are unimplemented

On 27 January 2017 at 14:17, Peter Maydell wrote: > On 27 January 2017 at 14:11, Alex Bennée wrote: >> >> Peter Maydell writes: >> Can we at least have the title of the document these came from for >> future reference?

[Qemu-devel] [Bug 1662600] Re: error while building from source on Ubuntu 16.04

Since libibverbs was optional, I uninstalled it. After doing so, my build seems to have progressed past this error. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1662600 Title: error while

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