Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH 2/9] Update headers using update-linux-headers.sh

On 09.02.2017 05:53, Sam Bobroff wrote: > On Tue, Feb 07, 2017 at 01:59:52PM +0100, Thomas Huth wrote: >> On 07.02.2017 03:56, Sam Bobroff wrote: >>> This provides some new definitions needed by ISA 3.00 guests. >>> >>> It is a large change because this is the first import since >>> some kernel

Re: [Qemu-devel] [PATCH v3] hw/core/register: Mark the device with cannot_instantiate_with_device_add_yet

Thomas Huth writes: > The "qemu,register" device needs to be wired up in source code, there > is no way the user can make any real use of this device with the > "-device" parameter or the "device_add" monitor command yet. > > Signed-off-by: Thomas Huth

Re: [Qemu-devel] [PATCH v3] hw/core/or-irq: Mark the device with cannot_instantiate_with_device_add_yet

Thomas Huth writes: > The "or-irq" device needs to be wired up in source code, there is no > way the user can make any real use of this device with the "-device" > parameter or the "device_add" monitor command yet. > > Signed-off-by: Thomas Huth Reviewed-by:

Re: [Qemu-devel] [PATCH 1/2] numa: Turn simple union NumaOptions into a flat union

Eric Blake writes: > On 02/08/2017 10:04 AM, Markus Armbruster wrote: >> Simple unions are simpler than flat unions in the schema, but more >> complicated in C and on the QMP wire: there's extra indirection in C >> and extra nesting on the wire, both pointless. They're best

[Qemu-devel] [PATCH 1/2] ide: core: add cleanup function

As the pci ahci can be hotplug and unplug, in the ahci unrealize function it should free all the resource once allocated in the realized function. This patch adds two cleanup function. Signed-off-by: Li Qiang --- hw/ide/core.c | 21 +

[Qemu-devel] [PATCH 2/2] ide: ahci: call cleanup function in ahci unit

This can avoid memory leak when hotunplug the ahci device. Signed-off-by: Li Qiang --- hw/ide/ahci.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 3c19bda..56f68a8 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1485,6

[Qemu-devel] [PATCH 0/2] ide: ahci: fix memory leak in device unit

As the pci ahci can be hotplug and unplug, in the ahci unrealize function it should free all the resource once allocated in the realized function. This patchset first add cleanup function in core layer and then call it in the ahci unit. Li Qiang (2): ide: core: add cleanup function ide:

Re: [Qemu-devel] virtio-scsi-pci iothread spins at 100%

On Thu, 02/09 13:39, Fam Zheng wrote: > On Wed, 02/08 19:44, Ed Swierk wrote: > > On Wed, Feb 8, 2017 at 6:52 PM, Fam Zheng wrote: > > > This means virtio-scsi event vq handler is returning true but actually no > > > progress is made. Can you try the following patch to see if

Re: [Qemu-devel] [PATCH v8 1/2] block/vxhs.c: Add support for a new block device type called "vxhs"

On Wed, Feb 08, 2017 at 09:23:33PM -0800, Ashish Mittal wrote: > From: Ashish Mittal > > Source code for the qnio library that this code loads can be downloaded from: > https://github.com/VeritasHyperScale/libqnio.git > > Sample command line using JSON syntax: >

Re: [Qemu-devel] [PATCH 04/18] nbd/client: refactor nbd_receive_starttls

07.02.2017 19:32, Eric Blake wrote: On 02/03/2017 09:47 AM, Vladimir Sementsov-Ogievskiy wrote: Split out nbd_receive_simple_option to be reused for structured reply option. Signed-off-by: Vladimir Sementsov-Ogievskiy --- nbd/client.c | 54

[Qemu-devel] [Help] Windows2012 as Guest 64+cores on KVM Halts

Dear all: I try to boot windows2012R2 (more than 64 cores)on kvm platform with hyper-v on**. the guest halts on the starting time. Also tested in these cases: - boot sucess - boot sucess - boot sucess - boot failed - boot sucess(in Guest we can found 64) - boot failed Environment:

[Qemu-devel] [PATCH 0/3] Risu PPC improvements

The series contains some fixes/cleanup for ppc64le Nikunj A Dadhania (3): risu_ppc64le: set r23 as the comment says risu_ppc64le: zero the xer register risu_ppc64le: remove aarch64 related comments risugen_ppc64.pm | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.7.4

[Qemu-devel] [PATCH 2/3] risu_ppc64le: zero the xer register

Observed failures running with P9 mambo model, and figured out that the xer wasn't initialized. Signed-off-by: Nikunj A Dadhania --- risugen_ppc64.pm | 3 +++ 1 file changed, 3 insertions(+) diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 0532e3a..03f9317

[Qemu-devel] [PATCH 3/3] risu_ppc64le: remove aarch64 related comments

Signed-off-by: Nikunj A Dadhania --- risugen_ppc64.pm | 2 -- 1 file changed, 2 deletions(-) diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 03f9317..f208a54 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -84,8 +84,6 @@ sub write_sxt32($$) sub

[Qemu-devel] [PATCH 1/3] risu_ppc64le: set r23 as the comment says

Signed-off-by: Nikunj A Dadhania --- risugen_ppc64.pm | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 8e323a2..0532e3a 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -167,9 +167,9 @@ sub

Re: [Qemu-devel] [PATCH qemu 1/2] exec, kvm, target-ppc: Move getrampagesize() to common code

On 03/01/17 10:34, David Gibson wrote: > On Thu, Dec 22, 2016 at 04:22:11PM +1100, Alexey Kardashevskiy wrote: >> getrampagesize() returns the largest supported page size and mainly >> used to know if huge pages are enabled. >> >> However is implemented in target-ppc/kvm.c and not available >> in

Re: [Qemu-devel] virtio-scsi-pci iothread spins at 100%

On Wed, 02/08 19:44, Ed Swierk wrote: > On Wed, Feb 8, 2017 at 6:52 PM, Fam Zheng wrote: > > This means virtio-scsi event vq handler is returning true but actually no > > progress is made. Can you try the following patch to see if it's because a > > stalled cache of VQ index? > >

[Qemu-devel] [PATCH v1 2/2] target-ppc: implement store atomic instruction

From: Balamuruhan S stwat: Store Word Atomic stdat: Store Doubleword Atomic The instruction includes as function code (5 bits) which gives a detail on the operation to be performed. The patch implements five such functions. Signed-off-by: Balamuruhan S

[Qemu-devel] [PATCH v1 1/2] target-ppc: implement load atomic instruction

From: Balamuruhan S lwat: Load Word Atomic ldat: Load Doubleword Atomic The instruction includes as function code (5 bits) which gives a detail on the operation to be performed. The patch implements five such functions. Signed-off-by: Balamuruhan S

[Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14

This series contains 4 new instructions for POWER9 ISA3.0 Load/Store Atomic instructions Changelog: v0: Raise invalid execption for function codes that are not implemented, and data storage execption for invalid function codes. Balamuruhan S (2): target-ppc: implement load atomic

[Qemu-devel] [PATCH v8 2/2] block/vxhs.c: Add qemu-iotests for new block device type "vxhs"

From: Ashish Mittal These changes use a vxhs test server that is a part of the following repository: https://github.com/VeritasHyperScale/libqnio.git Signed-off-by: Ashish Mittal --- v8/v7 changelog: (1) No changes. v6 changelog: (1) Added

Re: [Qemu-devel] [PATCH 20/22] target/openrisc: Optimize l.jal to next

On 02/09/2017 01:51 AM, Richard Henderson wrote: This allows the tcg optimizer to see, and fold, all of the constants involved in a GOT base register load sequence. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé ---

Re: [Qemu-devel] [PATCH 14/22] target/openrisc: Set flags on helpers

On 02/09/2017 01:51 AM, Richard Henderson wrote: Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/openrisc/helper.h | 24 1 file

Re: [Qemu-devel] [PATCH 15/22] target/openrisc: Enable trap, csync, msync, psync for user mode

On 02/09/2017 01:51 AM, Richard Henderson wrote: Not documented as disabled for user mode. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé ---

[Qemu-devel] [PATCH v8 1/2] block/vxhs.c: Add support for a new block device type called "vxhs"

From: Ashish Mittal Source code for the qnio library that this code loads can be downloaded from: https://github.com/VeritasHyperScale/libqnio.git Sample command line using JSON syntax: ./x86_64-softmmu/qemu-system-x86_64 -name instance-0008 -S -vnc 0.0.0.0:0 -k

[Qemu-devel] [PATCH 22/22] target/openrisc: Tidy handling of delayed branches

Signed-off-by: Richard Henderson --- target/openrisc/cpu.h| 12 +--- target/openrisc/gdbstub.c| 2 +- target/openrisc/interrupt.c | 4 ++-- target/openrisc/sys_helper.c | 2 +- target/openrisc/translate.c | 40 5

Re: [Qemu-devel] [RFC PATCH 3/9] spapr: Add ibm, processor-radix-AP-encodings to the device tree

On Thu, Feb 09, 2017 at 01:14:08PM +1100, David Gibson wrote: > On Tue, Feb 07, 2017 at 01:56:46PM +1100, Sam Bobroff wrote: > > Use the new ioctl, KVM_PPC_GET_RMMU_INFO, to fetch radix MMU > > information from KVM and present the page encodings in the device tree > > under

[Qemu-devel] [PATCH 13/22] target/openrisc: Use movcond where appropriate

Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/openrisc/translate.c

Re: [Qemu-devel] [PATCH 06/22] target/openrisc: Tidy insn dumping

On 02/09/2017 01:51 AM, Richard Henderson wrote: Avoids warnings from unused variables etc. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé ---

Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH 2/9] Update headers using update-linux-headers.sh

On Tue, Feb 07, 2017 at 01:59:52PM +0100, Thomas Huth wrote: > On 07.02.2017 03:56, Sam Bobroff wrote: > > This provides some new definitions needed by ISA 3.00 guests. > > > > It is a large change because this is the first import since > > some kernel header files have become autogenerated. > >

[Qemu-devel] [PATCH 11/22] target/openrisc: Keep SR_F in a separate variable

This avoids having to keep merging and extracting the flag from SR. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 15 +- target/openrisc/gdbstub.c | 4 +-

Re: [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction

David Gibson writes: > [ Unknown signature status ] > On Mon, Feb 06, 2017 at 03:59:57PM +0530, Nikunj A Dadhania wrote: >> From: Balamuruhan S >> >> lwat: Load Word Atomic >> ldat: Load Doubleword Atomic >> >> The instruction includes

[Qemu-devel] [PATCH 20/22] target/openrisc: Optimize l.jal to next

This allows the tcg optimizer to see, and fold, all of the constants involved in a GOT base register load sequence. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH 08/22] target/openrisc: Streamline arithmetic and OVE

Fix incorrect overflow calculation. Move overflow exception check to a helper function, to eliminate inline branches. Remove some incorrect special casing of R0. Implement multiply inline. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson

Re: [Qemu-devel] [RFC PATCH 2/9] Update headers using update-linux-headers.sh

On Thu, Feb 09, 2017 at 12:55:49PM +1100, David Gibson wrote: > On Tue, Feb 07, 2017 at 01:56:45PM +1100, Sam Bobroff wrote: > > This provides some new definitions needed by ISA 3.00 guests. > > > > It is a large change because this is the first import since > > some kernel header files have

[Qemu-devel] [PATCH 17/22] target/openrisc: Represent MACHI:MACLO as a single unit

Significantly simplifies the implementation of the use of MAC. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/cpu.h| 3 +- target/openrisc/machine.c| 5 +- target/openrisc/sys_helper.c | 13

[Qemu-devel] [PATCH 09/22] target/openrisc: Put SR[OVE] in TB flags

Removes a call at execution time for overflow exceptions. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 4 ++-- target/openrisc/exception_helper.c | 2 +- target/openrisc/translate.c| 24 +++- 3 files changed, 18

[Qemu-devel] [PATCH 21/22] target/openrisc: Tidy ppc/npc implementation

The NPC SPR is really only supposed to be used for FPGA debugging. It contains the same contents as PC, unless one plays games. Follow the or1ksim implementation in flushing delayed branch state when it is changed. The PPC SPR need not be updated every instruction, merely when we exit the TB or

[Qemu-devel] [PATCH 07/22] target/openrisc: Rationalize immediate extraction

The architecture manual is consistent in using "I" for signed fields and "K" for unsigned fields. Mirror that. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 98

[Qemu-devel] [PATCH 15/22] target/openrisc: Enable trap, csync, msync, psync for user mode

Not documented as disabled for user mode. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 32 1 file changed, 32 deletions(-) diff --git

[Qemu-devel] [PATCH 16/22] target/openrisc: Implement msync

Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 6c8f05c..dd4ba8c 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@

[Qemu-devel] [PATCH 06/22] target/openrisc: Tidy insn dumping

Avoids warnings from unused variables etc. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 36 1 file changed, 12 insertions(+), 24 deletions(-) diff --git

[Qemu-devel] [PATCH 19/22] target/openrisc: Fix madd

Note that the specification for lf.madd.s is confused. It's the only mention of supposed FPMADDHI/FPMADDLO special registers. On the other hand, or1ksim implements a somewhat normal non-fused multiply and add. Mirror that. Reviewed-by: Bastian Koppelmann

[Qemu-devel] [PATCH 14/22] target/openrisc: Set flags on helpers

Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/helper.h | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h

[Qemu-devel] [PATCH 12/22] target/openrisc: Keep SR_CY and SR_OV in a separate variables

This significantly streamlines carry and overflow production. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 13 +++- target/openrisc/exception_helper.c | 31 -- target/openrisc/helper.h | 4 +- target/openrisc/translate.c

[Qemu-devel] [PATCH 18/22] target/openrisc: Implement muld, muldu, macu, msbu

Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 108 1 file changed, 108 insertions(+) diff --git a/target/openrisc/translate.c

[Qemu-devel] [PATCH 03/22] linux-user: Fix openrisc cpu_loop

We need to handle EXCP_DEBUG and EXCP_INTERRUPT. We need to send signals to the guest using queue_signal. Signed-off-by: Richard Henderson --- linux-user/main.c | 95 --- 1 file changed, 41 insertions(+), 54 deletions(-)

[Qemu-devel] [PATCH 05/22] target/openrisc: Implement lwa, swa

Signed-off-by: Richard Henderson --- target/openrisc/cpu.c | 1 + target/openrisc/cpu.h | 3 ++ target/openrisc/interrupt.c| 1 + target/openrisc/interrupt_helper.c | 1 + target/openrisc/machine.c | 24 ++--

[Qemu-devel] [PATCH 10/22] target/openrisc: Invert the decoding in dec_calc

Decoding the opcodes in the right order reduces by 100+ lines. Also, it happens to put the opcodes in the same order as Chapter 17. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 302

[Qemu-devel] [PATCH 01/22] target/openrisc: Rename the cpu from or32 to or1k

This is in keeping with the toolchain and or1ksim. Signed-off-by: Richard Henderson --- configure | 6 +++--- default-configs/or1k-linux-user.mak | 1 + default-configs/or1k-softmmu.mak| 4 default-configs/or32-linux-user.mak | 1 -

[Qemu-devel] [PATCH 00/22] target/openrisc updates

The bulk of this patch set is 2-3 years old, and was mostly reviewed by Bastian Koppelmann. But it languished because there were reports of it not booting kernel images, and I had problems putting together a set of tools that could even build a kernel. The OpenRISC community has picked up

[Qemu-devel] [PATCH 04/22] target/openrisc: Fix exception handling status registers

From: Stafford Horne I am working on testing instruction emulation patches for the linux kernel. During testing I found these 2 issues: - sets DSX (delay slot exception) but never clears it - EEAR for illegal insns should point to the bad exception (as per openrisc spec)

Re: [Qemu-devel] [RFC] virtio-pci: Allow PCIe virtio devices on root bus

On Wed, Feb 08, 2017 at 11:40:50AM +0100, Laszlo Ersek wrote: > On 02/08/17 07:16, David Gibson wrote: > > Marcel, > > > > Your original patch adding PCIe support to virtio-pci.c has the > > limitation noted below that PCIe won't be enabled if the device is on > > the root bus (rather than under

Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH 6/9] spapr: Add h_register_process_table() hypercall

On 07/02/17 13:56, Sam Bobroff wrote: > Both radix and hash modes require guests to use > h_register_process_table() to set up the MMU. Implement it using the > new KVM ioctl KVM_PPC_CONFIGURE_V3_MMU. > > This hypercall is also necessary for fully emulated guests, so it will > need to be reworked

Re: [Qemu-devel] iommu emulation

(cc qemu-devel and Alex) On Wed, Feb 08, 2017 at 09:14:03PM -0500, Jintack Lim wrote: > On Wed, Feb 8, 2017 at 10:49 AM, Jintack Lim wrote: > > Hi Peter, > > > > On Tue, Feb 7, 2017 at 10:12 PM, Peter Xu wrote: > >> On Tue, Feb 07, 2017 at 02:16:29PM

Re: [Qemu-devel] virtio-scsi-pci iothread spins at 100%

On Wed, Feb 8, 2017 at 6:52 PM, Fam Zheng wrote: > This means virtio-scsi event vq handler is returning true but actually no > progress is made. Can you try the following patch to see if it's because a > stalled cache of VQ index? > > diff --git a/hw/virtio/virtio.c

Re: [Qemu-devel] [RFC PATCH 0/9] ISA 3.00 KVM guest support

On 07/02/17 13:56, Sam Bobroff wrote: > Because KVM will soon provide the necessary infrastructure for KVM guests to > run on POWER9 CPUs, we can now start exploiting this new functionality from > QEMU. See: > https://lists.ozlabs.org/pipermail/linuxppc-dev/2017-January/153433.html > > This work

Re: [Qemu-devel] [RFC PATCH 10/17] target/ppc/POWER9: Add POWER9 mmu fault handler

On Wed, 2017-02-01 at 15:23 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:16PM +1100, Suraj Jitindar Singh wrote: > > > > Add a new mmu fault handler for the POWER9 cpu and add it as the > > handler > > for the POWER9 cpu definition. > > > > This handler checks if the guest is radix

Re: [Qemu-devel] [RFC PATCH 09/17] target/ppc/POWER9: Remove SDR1 register

On Wed, 2017-02-01 at 15:16 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:15PM +1100, Suraj Jitindar Singh wrote: > > > > The SDR1 registers was used to store the location of the hash page > > table. > > > > This register no longer exists on POWER9 processors, so don't > > create

Re: [Qemu-devel] Question about add AF_ALG backend for virtio-crypto

Hi Daniel, On 2017/2/8 18:53, Daniel P. Berrange wrote: > On Wed, Feb 08, 2017 at 06:46:04PM +0800, Longpeng (Mike) wrote: >> Hi Daniel, >> >> I was writing AF_ALG-backed for QEMU crypto these days, I think there're more >> than two ways to implements it. >> >> The first one look likes below: >>

Re: [Qemu-devel] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support

On Wed, 2017-02-01 at 12:04 +1100, David Gibson wrote: > On Thu, Jan 12, 2017 at 10:55:49PM -0800, no-re...@patchew.org wrote: > > > > Hi, > > > > Your series seems to have some coding style problems. See output > > below for > > more information: > > > > Message-id:

Re: [Qemu-devel] [RFC PATCH 08/17] target/ppc/POWER9: Add external partition table pointer to cpu state

On Wed, 2017-02-01 at 15:09 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:14PM +1100, Suraj Jitindar Singh wrote: > > > > Similarly to how we have an external hpt pointer in the cpu state, > > add > > an external partition table pointer and update it to point to the > > partition

Re: [Qemu-devel] [RFC PATCH 11/17] target/ppc/POWER9: Update to new pte format for POWER9 accesses

On Wed, 2017-02-01 at 15:28 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:17PM +1100, Suraj Jitindar Singh wrote: > > > > The page table entry format was updated for the POWER9 processor. > > > > It was decided that kernels would used the old format irrespective > > with the

Re: [Qemu-devel] [virtio-dev] Re: [virtio-dev] [PATCH v16 1/2] virtio-crypto: Add virtio crypto device specification

Hi, > > > On 02/08/2017 07:24 AM, Gonglei (Arei) wrote: > > Hi Halil, > > > > Thanks for your comments firstly. > > > > You are welcome :). Sorry it took so long -- I'm currently > quite busy. > It's fine. > >> > >> On 01/18/2017 09:22 AM, Gonglei wrote: > >>> The virtio crypto device is a

Re: [Qemu-devel] [RFC PATCH 07/17] target/ppc/POWER9: Add partition table pointer to sPAPRMachineState

On Wed, 2017-02-01 at 15:04 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:13PM +1100, Suraj Jitindar Singh wrote: > > > > POWER9 uses a partition table to store information relating to how > > address translation is performed on a per partition basis. > > > > Add a data area for

Re: [Qemu-devel] virtio-scsi-pci iothread spins at 100%

On Wed, 02/08 18:11, Ed Swierk wrote: > On Wed, Feb 8, 2017 at 5:47 PM, Fam Zheng wrote: > > No, something is wrong. The polling shouldn't keep running when there is no > > I/O > > activity. > > > > Can you try "perf top" to see what poll handlers are spinning? > > Samples:

Re: [Qemu-devel] [RFC PATCH 9/9] spapr: Small cleanup of PPC MMU enums

On Tue, Feb 07, 2017 at 01:56:52PM +1100, Sam Bobroff wrote: > The PPC MMU types are sometimes treated as if they were a bit field > and sometime as if they were an enum which causes maintenance > problems: flipping bits in the MMU type (which is done on both the 1TB > segment and 64K segment

Re: [Qemu-devel] [RFC PATCH 2/9] Update headers using update-linux-headers.sh

On Tue, Feb 07, 2017 at 01:56:45PM +1100, Sam Bobroff wrote: > This provides some new definitions needed by ISA 3.00 guests. > > It is a large change because this is the first import since > some kernel header files have become autogenerated. > > Note: update-linux-headers.sh currently generates

Re: [Qemu-devel] [RFC PATCH 5/9] spapr: Only setup HTP if necessary.

On Tue, Feb 07, 2017 at 01:56:48PM +1100, Sam Bobroff wrote: > Because KVM cannot support radix and hash modes concurrently, QEMU can > avoid allocating a hash page table if KVM supports radix mode. > > Signed-off-by: Sam Bobroff This isn't quite right, it's doing the

Re: [Qemu-devel] [RFC PATCH 7/9] spapr: Set ISA 3.00 radix and hash bits in OV5

On Tue, Feb 07, 2017 at 01:56:50PM +1100, Sam Bobroff wrote: > Set new option vector 5 bits to indicate KVM support for in-memory > radix or hash modes and related options. The existing logic will > propagate the results back to the guest in the device tree. This > allows guests to perform client

Re: [Qemu-devel] [RFC PATCH 0/9] ISA 3.00 KVM guest support

On Tue, Feb 07, 2017 at 01:56:43PM +1100, Sam Bobroff wrote: > > Because KVM will soon provide the necessary infrastructure for KVM guests to > run on POWER9 CPUs, we can now start exploiting this new functionality from > QEMU. See: >

Re: [Qemu-devel] [RFC PATCH 8/9] spapr: Advertise ISA 3.0 MMU features in pa_features

On Tue, Feb 07, 2017 at 01:56:51PM +1100, Sam Bobroff wrote: > Set the default ibm,pa_features bits for ISA 3.0. > > Providing the radix MMU support bit in ibm,pa-features will cause some > recent (e.g. 4.9) kernels to attempt to initialize the MMU as if they > were a radix host, which will cause

Re: [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction

On Mon, Feb 06, 2017 at 03:59:57PM +0530, Nikunj A Dadhania wrote: > From: Balamuruhan S > > lwat: Load Word Atomic > ldat: Load Doubleword Atomic > > The instruction includes as function code (5 bits) which gives a detail > on the operation to be performed. The patch

Re: [Qemu-devel] [RFC PATCH 4/9] target-ppc: support KVM_CAP_PPC_MMU_RADIX, KVM_CAP_PPC_MMU_HASH_V3

On Tue, Feb 07, 2017 at 01:56:47PM +1100, Sam Bobroff wrote: > Query and cache the value of two new KVM capabilities that indicate > KVM's support for new radix and hash modes of the MMU. > > Signed-off-by: Sam Bobroff > --- > target/ppc/kvm.c | 14 ++ >

Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH 1/9] spapr: fix off-by-one error in spapr_ovec_populate_dt()

On Tue, Feb 07, 2017 at 04:47:53PM +0100, Thomas Huth wrote: > On 07.02.2017 03:56, Sam Bobroff wrote: > > The last byte of the option vector was missing due to an off-by-one > > error. Without this fix, client architecture support negotiation will > > fail because the last byte of option vector

Re: [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14

On Mon, Feb 06, 2017 at 03:59:56PM +0530, Nikunj A Dadhania wrote: > This series contains 8 new instructions for POWER9 ISA3.0 > VSX Scalar Maximum DP > VSX Scalar Minimum DP > Load/Store Atomic instructions > > Balamuruhan S (2): > target-ppc: implement load atomic instruction >

Re: [Qemu-devel] [RFC PATCH 6/9] spapr: Add h_register_process_table() hypercall

On Tue, Feb 07, 2017 at 01:56:49PM +1100, Sam Bobroff wrote: > Both radix and hash modes require guests to use > h_register_process_table() to set up the MMU. Implement it using the > new KVM ioctl KVM_PPC_CONFIGURE_V3_MMU. > > This hypercall is also necessary for fully emulated guests, so it

Re: [Qemu-devel] [RFC PATCH 3/9] spapr: Add ibm, processor-radix-AP-encodings to the device tree

On Tue, Feb 07, 2017 at 01:56:46PM +1100, Sam Bobroff wrote: > Use the new ioctl, KVM_PPC_GET_RMMU_INFO, to fetch radix MMU > information from KVM and present the page encodings in the device tree > under ibm,processor-radix-AP-encodings. This provides page size > information to the guest which is

Re: [Qemu-devel] [virtio-dev] [PATCH v16 1/2] virtio-crypto: Add virtio crypto device specification

> > On 02/08/2017 04:46 AM, Gonglei (Arei) wrote: > > Hi Cornelia, > > > >> > >> On Tue, 7 Feb 2017 12:39:44 +0100 > >> Halil Pasic wrote: > >> > >>> On 01/18/2017 09:22 AM, Gonglei wrote: > >> > +\section{Crypto Device}\label{sec:Device Types / Crypto Device} >

[Qemu-devel] [Bug 1662050] Re: qemu-img convert a overlay qcow2 image into a entire image

@Eric Blake, I used virt-sparsify to sparsify the qcow2 overlay image. As you said, the actual disk usage is minimized and the apparent file size is unchanged.It is very valuable for me, because it means that my disk can hold more files. But we need to be careful when transfer the sparse qcow2

Re: [Qemu-devel] virtio-scsi-pci iothread spins at 100%

On Wed, Feb 8, 2017 at 5:47 PM, Fam Zheng wrote: > No, something is wrong. The polling shouldn't keep running when there is no > I/O > activity. > > Can you try "perf top" to see what poll handlers are spinning? Samples: 288K of event 'cycles', Event count (approx.):

[Qemu-devel] [PATCH v2] net: e1000e: fix an infinite loop issue

From: Li Qiang This issue is like the issue in e1000 network card addressed in this commit: e1000: eliminate infinite loops on out-of-bounds transfer start. Signed-off-by: Li Qiang --- Changes since v1: make wraparound detect in e1000e_ring_empty

Re: [Qemu-devel] [PATCH V7 2/2] Add a new qmp command to do checkpoint, query xen replication status

On 02/09/2017 05:35 AM, Eric Blake wrote: On 02/07/2017 11:24 PM, Zhang Chen wrote: We can call this qmp command to do checkpoint outside of qemu. Xen colo will need this function. Signed-off-by: Zhang Chen Signed-off-by: Wen Congyang

Re: [Qemu-devel] virtio-scsi-pci iothread spins at 100%

On Wed, 02/08 08:33, Ed Swierk wrote: > Recently I noticed that when I configure a virtio-scsi-pci device > using an iothread, as soon as the guest virtio-scsi driver loads, the > iothread spins at 100%: > > -object iothread,id=iothread1 -device virtio-scsi-pci,iothread=iothread1 > > This

Re: [Qemu-devel] [PATCH v16 1/2] virtio-crypto: Add virtio crypto device specification

> > On 02/07/2017 01:59 AM, Gonglei (Arei) wrote: > > Hi, > > > >> From: Michael S. Tsirkin [mailto:m...@redhat.com] > >> Sent: Tuesday, February 07, 2017 2:20 AM > >> Subject: Re: [Qemu-devel] [PATCH v16 1/2] virtio-crypto: Add virtio crypto > >> device specification > >> > >> On Mon, Feb 06,

Re: [Qemu-devel] Question about QEMU's threading model and stacking multiple block drivers

On Wed, 02/08 11:00, Adrian Suarez wrote: > > > > Do you only start submitting request to B (step 3) after the fast device > > I/O > > completes (step 2.a)? The fact that they are serialized incurs extra > > latency. > > Have you tried to do 2 and 3 in parallel with AIO? > > > In step 2, we

Re: [Qemu-devel] [PATCH] hw/ppc/pnv: Remove superfluous "qemu" prefix from error strings

On Wed, Feb 08, 2017 at 07:31:57PM +0100, Thomas Huth wrote: > error_report() already puts a prefix with the program name in front > of the error strings, so the "qemu:" prefix is not necessary here > anymore. > > Reported-by: Markus Armbruster > Signed-off-by: Thomas Huth

Re: [Qemu-devel] [PATCH v3 1/1] nios2: Add Altera JTAG UART emulation

> Please make the commit message a bit more verbose, looking just at the > commit message, I have no clue what patch I'm looking at. The embedded > IP UG also has like 30 cores in it, so some detail on which core and in > which chapter/page would help. OK, will do > > + * The Altera JTAG UART

Re: [Qemu-devel] [PATCH v3 18/18] block: pass option prefix down to crypto layer

On 26.01.2017 11:18, Daniel P. Berrange wrote: > While the crypto layer uses a fixed option name "key-secret", > the upper block layer may have a prefix on the options. e.g. > "luks-key-secret", "aes-key-secret", in order to avoid clashes > between crypto option names & other block option names.

Re: [Qemu-devel] [PATCH v5 05/10] ACPI: Add Virtual Machine Generation ID support

On 02/05/17 10:12, b...@skyportsystems.com wrote: > From: Ben Warren > > This implements the VM Generation ID feature by passing a 128-bit > GUID to the guest via a fw_cfg blob. > Any time the GUID changes, an ACPI notify event is sent to the guest > > The user

Re: [Qemu-devel] [PATCH v3 14/18] qcow2: add iotests to cover LUKS encryption support

On 26.01.2017 11:18, Daniel P. Berrange wrote: > This extends the 087 iotest to cover LUKS encryption when doing > blockdev-add. > > Two further tests are added to validate read/write of LUKS > encrypted images with a single file and with a backing file. > > Signed-off-by: Daniel P. Berrange

Re: [Qemu-devel] [PATCH v3 13/18] qcow2: add support for LUKS encryption format

On 26.01.2017 11:18, Daniel P. Berrange wrote: > This adds support for using LUKS as an encryption format > with the qcow2 file. The use of the existing 'encryption=on' > parameter is replaced by a new parameter 'encryption-format' > which takes the values 'aes' or 'luks'. e.g. > > # qemu-img

Re: [Qemu-devel] [PATCH v5 05/10] ACPI: Add Virtual Machine Generation ID support

On 02/08/17 23:34, Ben Warren wrote: > >> On Feb 7, 2017, at 4:48 PM, Laszlo Ersek > > wrote: >> >> On 02/05/17 10:12, b...@skyportsystems.com >> wrote: >>> From: Ben Warren

Re: [Qemu-devel] [PATCH v3 1/1] nios2: Add Altera JTAG UART emulation

On 8 February 2017 at 23:22, Marek Vasut wrote: > On 02/09/2017 12:06 AM, Juro Bystricky wrote: >> + * This program is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License >> + * as published by the Free Software

Re: [Qemu-devel] [PATCH v3 12/18] qcow2: extend specification to cover LUKS encryption

On 26.01.2017 11:18, Daniel P. Berrange wrote: > Update the qcow2 specification to describe how the LUKS header is > placed inside a qcow2 file, when using LUKS encryption for the > qcow2 payload instead of the legacy AES-CBC encryption > > Signed-off-by: Daniel P. Berrange

Re: [Qemu-devel] [PATCH v3 11/18] qcow2: convert QCow2 to use QCryptoBlock for encryption

On 26.01.2017 11:18, Daniel P. Berrange wrote: > This converts the qcow2 driver to make use of the QCryptoBlock > APIs for encrypting image content, using the legacyy QCow2 AES > scheme. > > With this change it is now required to use the QCryptoSecret > object for providing passwords, instead of

Re: [Qemu-devel] [PATCH v3 1/1] nios2: Add Altera JTAG UART emulation

On 02/09/2017 12:06 AM, Juro Bystricky wrote: > Hardware emulation based on: > https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf Please make the commit message a bit more verbose, looking just at the commit message, I have no clue what patch I'm looking at. The embedded IP UG

Re: [Qemu-devel] [PATCH v2 0/1] Nios2: Altera JATAG UART

no problem, just sent in a patch v3. I found a shorter link, so it should keep checkaptch happy as well. > -Original Message- > From: Peter Maydell [mailto:peter.mayd...@linaro.org] > Sent: Wednesday, February 8, 2017 3:00 PM > To: Bystricky, Juro > Cc: QEMU

[Qemu-devel] [PATCH v3 1/1] nios2: Add Altera JTAG UART emulation

Hardware emulation based on: https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf Signed-off-by: Juro Bystricky --- default-configs/nios2-softmmu.mak | 1 + hw/char/Makefile.objs | 1 + hw/char/altera_juart.c| 268

[Qemu-devel] [PATCH v3 0/1] nios2: Add Altera JTAG UART emulation

v3: including a link to HW registers specs Juro Bystricky (1): nios2: Add Altera JTAG UART emulation default-configs/nios2-softmmu.mak | 1 + hw/char/Makefile.objs | 1 + hw/char/altera_juart.c| 268 ++

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