On Thu, Apr 27, 2017 at 02:51:31PM -0500, Michael Roth wrote:
> Quoting David Gibson (2017-04-27 02:28:43)
> > Migrating between different CPU versions is a bit complicated for ppc.
> > A long time ago, we ensured identical CPU versions at either end by
> > checking the PVR had the same value. How
On Thu, Apr 27, 2017 at 04:31:53PM +1000, Sam Bobroff wrote:
> ics_get_kvm_state() "or"s set bits into irq->status but does not mask
> out clear bits.
>
> Correct this by initializing the IRQ status to zero before adding bits
> to it.
>
> Signed-off-by: Sam Bobroff
This definitely looks like a
On Thu, Apr 27, 2017 at 10:48:18AM +0530, Nikunj A Dadhania wrote:
> Patch 01: Use atomic_cmpxchg in store conditional
> 02: Handle first write to page during atomic operation
> 03: Generate memory barriers for sync/isync and load/store conditional
> 04: Fix CPU unplug in MTTCG
>
On Thu, Apr 27, 2017 at 04:32:03PM +1000, Sam Bobroff wrote:
> Kernel commit 17d48610ae0f ("KVM: PPC: Book 3S: XICS: Implement ICS
> P/Q states") added new bits to the state used by KVM IRQs. Currently,
> QEMU does not preserve these bits, so migrating (or otherwise saving
> and restoring) the gues
On 25/04/17 15:57, Peter Maydell wrote:
> On 21 April 2017 at 09:28, Mark Cave-Ayland
> wrote:
>> This was an artifact from very early versions of the code from before the
>> memory API and is no longer needed.
>>
>> Signed-off-by: Mark Cave-Ayland
>> Reviewed-by: Gerd Hoffmann
>> ---
>> hw/di
On 25/04/17 15:54, Peter Maydell wrote:
> On 21 April 2017 at 09:28, Mark Cave-Ayland
> wrote:
>> As all surfaces in QEMU are now either shared or 32-bit ARGB regardless of
>> the guest depth, remove all non-32-bit primitives from tcx_update_display()
>> and consequence their implementation which
On Thu, Apr 27, 2017 at 05:34:17PM +0800, Peter Xu wrote:
> Renaming *iommu_notifiers* into *iotlb_notifiers*. Again, let's reserve
> the iommu_notifier keyword to the notifiers that will be for per-iommu,
> and let the old per-mr notifier be iotlb_notifiers.
As with the previous patch, I really d
On Thu, Apr 27, 2017 at 05:34:18PM +0800, Peter Xu wrote:
> This is something similar to MemoryRegionOps, it's just for address
> spaces to store arch-specific hooks.
>
> The first hook I would like to introduce is iommu_get().
>
> For systems that have IOMMUs, we will create a special address sp
On Thu, Apr 27, 2017 at 05:34:14PM +0800, Peter Xu wrote:
> Renaming it to IOMMUMRNotifier. This is a corresponding change to
> previous patch, to emphasize that these notifiers are based on memory
> regions.
>
> Signed-off-by: Peter Xu
I think this patch could be folded with the previous one.
On Thu, Apr 27, 2017 at 05:34:13PM +0800, Peter Xu wrote:
> IOMMU notifiers before are mostly used for [dev-]IOTLB stuffs. It is not
> suitable for other kind of notifiers (one example would be the future
> virt-svm support). Considering that current notifiers are targeted for
> per memory region,
On Thu, Apr 27, 2017 at 05:34:16PM +0800, Peter Xu wrote:
> Actually it's notifying IOTLB updates (map, or unmap). Let's be explicit
> on the wording - replacing it with *_notify_iotlb*.
I really don't see the distinction here. This is notifying of a
change in IOMMU mappings. We use the IOTLBEnt
On Thu, Apr 27, 2017 at 05:34:15PM +0800, Peter Xu wrote:
> It's new name is iommu_mr_notifier_init(). Again, literal changes only.
>
> Signed-off-by: Peter Xu
Again, I think this could be folded with the previous two patches.
Signed-off-by: David Gibson
I also note that these patches will co
On Thu, Apr 27, 2017 at 09:13:16PM -0500, Eric Blake wrote:
> Libvirt would like to be able to distinguish between a SHUTDOWN
> event triggered solely by guest request and one triggered by a
> SIGTERM or other action on the host. While qemu_kill_report() is
> already able to tell whether a shutdow
On Sun, Apr 30, 2017 at 09:11:04PM +0800, Fam Zheng wrote:
> On Sat, 04/29 22:36, Alexey Kardashevskiy wrote:
> > > === OUTPUT BEGIN ===
> > > Checking PATCH 1/1: memory/iommu: QOM'fy IOMMU MemoryRegion...
> > > ERROR: spaces required around that '*' (ctx:WxO)
> > > #156: FILE: hw/dma/rc4030.c:720:
On Fri, Apr 28, 2017 at 10:26:31AM +0200, Cédric Le Goater wrote:
> Today, when a PowerNV guest runs, it uses the sensor definitions of
> the BMC simulator to populate the device tree. But an external IPMI
> BMC could also be used and, in that case, it is not (yet) possible to
> retrieve the sensor
I'm working with an emulation for a proprietary processor on an older QEMU source base. It looks
like the problem I am seeing in the old sources would still be present in the current source base.
I'm seeing incorrect values when there is a write to a memory-mapped I/O device when icount is set.
On Thu, Apr 27, 2017 at 05:31:48PM -0300, Eduardo Habkost wrote:
> On Thu, Apr 27, 2017 at 12:12:59PM +0200, Laurent Vivier wrote:
> > When there are more nodes than memory available to put the minimum
> > allowed memory by node, all the memory is put on the last node.
> >
> > This is because we p
** Changed in: qemu
Status: Fix Committed => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1653384
Title:
Assertion failed with USB pass through with XHCI controller
Status in
On Thu, Apr 27, 2017 at 12:23:51PM -0500, Michael Roth wrote:
> Quoting David Gibson (2017-04-27 02:28:41)
> > Server class POWER CPUs have a "compat" property, which is used to set the
> > backwards compatibility mode for the processor. However, this only makes
> > sense for machine types which d
On Sat, Apr 29, 2017 at 12:30:08 +0200, Richard Henderson wrote:
> On 04/28/2017 09:22 PM, Emilio G. Cota wrote:
> >On Fri, Apr 28, 2017 at 15:17:24 -0400, Emilio G. Cota wrote:
> >>+++ b/target/arm/translate-a64.c
> >>@@ -373,8 +373,7 @@ static inline void gen_goto_tb(DisasContext *s, int n,
> >>
I'm working with an emulation for a proprietary processor on an older QEMU source base. It looks
like the problem I am seeing in the old sources would still be present in the current source base.
I'm seeing incorrect values when there is a write to a memory-mapped I/O device when icount is set.
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: cover.1493593744.git.sho...@gmail.com
Type: series
Subject: [Qemu-devel] [PULL 00/11] Fixes and features for OpenRISC
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log
When debugging in gdb you might want to inspect instructions in mapped
pages or in exception vectors like 0x800 etc. This was previously not
possible in qemu since the *get_phys_page_debug() routine only looked
into the data tlb.
Change to fall back to look into instruction tlb and plain physical
The features property has stored the exact same thing as the cpucfgr
spr. Remove the feature enum and property as it is not needed.
In order to preserve the behavior or keeping features accross reset this
patch moves cpucfgr into the non reset region of the state struct. Since
the cpucfgr is read
From: Tim 'mithro' Ansell
Exception Prefix High (EPH) control bit of the Supervision Register
(SR).
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR)
Previously serialization did not persist the tlb, timer, pic and other
key state items. This meant snapshotting and restoring a running os
would crash. After adding these I am able to take snapshots of a
running linux os and restore at a later time.
I am currently not trying to maintain capatibil
The OpenRISC architecture has the Power Management Register (PMR)
special purpose register to manage cpu power states. The interesting
modes are:
* Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt
* Sleep Mode (SME) - Stop cpu and all units - wake on interrupt
* Suspend Model
For openrisc we implement tlb state as a 2d array of tlb entry structs.
This is added to allow easy storing of state of 2d arrays.
Signed-off-by: Stafford Horne
---
include/migration/vmstate.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/include/migration/vmstate.h b/incl
From: Tim 'mithro' Ansell
Exception Vector Base Address Register (EVBAR) - This optional register
can be used to apply an offset to the exception vector addresses.
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'
Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature. When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.
This patch only implements shad
Hello,
This are the openrisc patches I have been circulating on the mailing list
of the last few months. We have had help from a few new people and added
the following:
* Fixes for gdb memory debugging
* Added support for Shadow Registers, EVBAR, EPH
* Added support for idle state, no more 100
These are used to identify the processor in SMP system. Their
definition has been defined in verilog cores but it not yet part of the
spec but it will be soon.
The proposal for this is available:
https://openrisc.io/proposals/core-identifier-and-number-of-cores
Reviewed-by: Richard Henderson
In openRISC we are implementing the shadow registers as a 2d array.
Using this target long method rather than direct 32-bit alternatives is
consistent with the rest of our vm state serialization logic.
Signed-off-by: Stafford Horne
---
include/migration/cpu.h | 7 +++
1 file changed, 7 inser
Jia has claimed he is no longer able to maintain. I have fixing bugs here
and there and getting familiar with the code base. Orignal thread from Jia:
https://lists.librecores.org/pipermail/openrisc/2017-January/000321.html
Signed-off-by: Stafford Horne
Reviewed-by: Alex Bennée
---
MAINTAINER
** Description changed:
I'm trying to get a USB web camera working in Qemu & Raspbian. USB works
and V4L shows device info correctly and capturing frames from the camera
works sometimes, but mostly it crashes with error message:
qemu-system-arm: hw/usb/core.c:558: usb_packet_setup: Asse
Public bug reported:
I'm trying to get a USB web camera working in Qemu & Raspbian. USB works
and V4L shows device info correctly and capturing frames from the camera
works sometimes, but mostly it crashes with error message:
qemu-system-arm: hw/usb/core.c:558: usb_packet_setup: Assertion
`!usb_p
From: Jianjun Duan
In racing situations between hotplug events and migration operation,
a rtas hotplug event could have not yet be delivered to the source
guest when migration is started. In this case the pending_events of
spapr state need be transmitted to the target so that the hotplug
event ca
From: Jianjun Duan
ccs_list in spapr state maintains the device tree related
information on the rtas side for hotplugged devices. In racing
situations between hotplug events and migration operation, a rtas
hotplug event could be migrated from the source guest to target
guest, or the source guest
Following up the previous detach_cb change, this patch removes the
detach_cb_opaque entirely from the code.
The reason is that the drc->detach_cb_opaque object can't be
restored in the post load of the upcoming DRC migration and no detach
callbacks actually need this opaque. 'spapr_core_release' i
The idea of moving the detach callback functions to the constructor
of the dr_connector is to set them statically at init time, avoiding
any post-load hooks to restore it (after a migration, for example).
Summary of changes:
- hw/ppc/spapr_drc.c and include/hw/ppc/spapr_drc.h:
* spapr_dr_con
In pseries, a firmware abstraction called Dynamic Reconfiguration
Connector (DRC) is used to assign a particular dynamic resource
to the guest and provide an interface to manage configuration/removal
of the resource associated with it. In other words, DRC is the
'plugged state' of a device.
Before
v8:
- new patch added: 'removing spapr_drc_detach_cb opaques'. This new patch
removes
the need for the detach_cb_opaques inside the removal callback functions. See
the commit message of the patch for more info.
v7:
- removed the first patch. DRC registration is now done by vmstate_register
in pat
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.h | 2 +-
tcg/mips/tcg-target.inc.c | 13 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index e3240cfba7..d75cb63ed3 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg
Please find patches to support cross-tb optimizations on MIPS hosts
and to implement cross-tb optimizations for MIPS target.
Aurelien Jarno (3):
tcg/mips: implement goto_ptr
target/mips: optimize cross-page direct jumps in softmmu
target/mips: optimize indirect branches
target/mips/transla
Cc: Yongbok Kim
Signed-off-by: Aurelien Jarno
---
target/mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3022f349cb..1a7ac07c67 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4233
Cc: Yongbok Kim
Signed-off-by: Aurelien Jarno
---
target/mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1a7ac07c67..559f8fed89 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1072
The "msb" argument should correspond to (len - 1).
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 01ac7b2c81..2a7e1c7f5b 100644
--- a/tcg/mips/tcg-targ
Public bug reported:
When running a virtual machine with qemu 2.9.0 with this parameter for
sharing a folder:
-virtfs local,id=fsdev1,path=$HOME/git,security_model=none,mount_tag=git
then the folder is shared to the VM but in some subfolders I can't
delete files. The guest system then reports th
On Sat, 04/29 22:36, Alexey Kardashevskiy wrote:
> > === OUTPUT BEGIN ===
> > Checking PATCH 1/1: memory/iommu: QOM'fy IOMMU MemoryRegion...
> > ERROR: spaces required around that '*' (ctx:WxO)
> > #156: FILE: hw/dma/rc4030.c:720:
> > +DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion *
FONNEMANN Mark, on dim. 30 avril 2017 12:42:41 +, wrote:
> root@qemu:~# nslookup www.google.com
>*** Unknown host
>
>nslookup: www.google.com: Unknown host
Could you run tcpdump inside the guest so we are sure what the nslookup
call emits?
Samuel
>Could you show us your NG.cfg, your guest /sbin/ifconfig and /sbin/route
>output and /etc/resolv.conf >content for that host?
[mfonnemann@desktopPC qemu]$ cat NG.cfg
[drive]
format = "raw"
file = "qemu_rootfs_512.img"
[drive]
format = "raw"
file = "placeholder2.vhdx"
[drive]
format =
On 04/30/2017 11:47 AM, Richard Henderson wrote:
These aarch64 patches fail for me like so:
$ ../bld/aarch64-softmmu/qemu-system-aarch64 -M virt -cpu cortex-a57 \
-m 1024 -nographic -kernel ./aarch64-linux-3.15rc2-buildroot.img \
-append console=ttyAMA0
qemu-system-aarch64: /home/rth/w
These aarch64 patches fail for me like so:
$ ../bld/aarch64-softmmu/qemu-system-aarch64 -M virt -cpu cortex-a57 \
-m 1024 -nographic -kernel ./aarch64-linux-3.15rc2-buildroot.img \
-append console=ttyAMA0
qemu-system-aarch64: /home/rth/work/qemu/qemu/cpu-exec.c:599: cpu_loop_exec_tb:
Ass
FONNEMANN Mark, on sam. 29 avril 2017 23:15:08 +, wrote:
> [mfonnemann@desktopPC qemu]$ /usr/local/bin/qemu-system-i386 -display curses
> -readconfig NG.cfg --enable-kvm
Could you show us your NG.cfg, your guest /sbin/ifconfig and /sbin/route
output and /etc/resolv.conf content for that host?
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