Re: [Qemu-devel] [PATCH v3 17/18] numa: add '-numa cpu, ...' option for property based node mapping

On Wed, May 10, 2017 at 01:30:01PM +0200, Igor Mammedov wrote: > legacy cpu to node mapping is using cpu index values to map > VCPU to node with help of '-numa node,nodeid=node,cpus=x[-y]' > option. However cpu index is internal concept and QEMU users > have to guess /reimplement qemu's logic/ to

Re: [Qemu-devel] [virtio-dev] RE: virtio-net: configurable TX queue size

On 05/11/2017 04:07 AM, Michael S. Tsirkin wrote: On Wed, May 10, 2017 at 05:52:23PM +0800, Wei Wang wrote: On 05/07/2017 12:39 PM, Wang, Wei W wrote: On 05/06/2017 04:37 AM, Michael S. Tsirkin wrote: On Fri, May 05, 2017 at 10:27:13AM +0800, Jason Wang wrote: On 2017年05月04日 18:58, Wang, Wei

Re: [Qemu-devel] [RFC PATCH 6/8] memory: introduce AddressSpaceOps

On Wed, May 10, 2017 at 05:04:06PM +1000, David Gibson wrote: > On Mon, May 08, 2017 at 03:32:17PM +0800, Peter Xu wrote: > > On Mon, May 08, 2017 at 04:07:44PM +1000, David Gibson wrote: > > > On Mon, May 08, 2017 at 01:48:14PM +0800, Peter Xu wrote: > > > > On Mon, May 01, 2017 at 02:58:22PM

[Qemu-devel] [PATCH] virtio-net: keep the packet layout intact

The current implementation may change the packet layout when vnet_hdr needs an endianness swap. The layout change causes one more iov to be added to the iov[] passed from the guest, which is a barrier to making the TX queue size 1024 due to the possible off-by-one issue. This patch changes the

Re: [Qemu-devel] [PATCH 05/11] blockjob: separate monitor and blockjob APIs

On 09/05/2017 19:06, Jeff Cody wrote: >> Keep the two APIs separate in the blockjob.c file too. This will >> be useful when transitioning away from the AioContext lock, because >> there will be locking policies for the two categories, too---the >> monitor will have to call new

Re: [Qemu-devel] [PATCH RESEND V3 5/6] migration: calculate downtime on dst side

On Wed, May 10, 2017 at 04:58:59PM +0100, Daniel P. Berrange wrote: > On Wed, May 10, 2017 at 06:46:50PM +0300, Alexey wrote: > > On Tue, May 09, 2017 at 10:44:34AM +0100, Daniel P. Berrange wrote: > > > On Tue, May 09, 2017 at 10:40:34AM +0100, Dr. David Alan Gilbert wrote: > > > > * Peter Xu

Re: [Qemu-devel] [PATCH 7/8] target/ppc: optimize various functions using extract op

Philippe Mathieu-Daudé writes: > Applied using Coccinelle script. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/ppc/translate.c | 9 +++-- > target/ppc/translate/vsx-impl.inc.c | 21 +++-- > 2 files changed, 10

Re: [Qemu-devel] [PATCH v3 11/18] QMP: include CpuInstanceProperties into query_cpus output output

On Wed, May 10, 2017 at 01:29:55PM +0200, Igor Mammedov wrote: > if board supports CpuInstanceProperties, report them for > each CPU thread listed. Main motivation for this is to > provide these properties introspection via QMP interface > for using in test cases to verify numa node to cpu

Re: [Qemu-devel] [PATCH v3 01/18] numa: move source of default CPUs to NUMA node mapping into boards

On Wed, May 10, 2017 at 01:29:45PM +0200, Igor Mammedov wrote: > Originally CPU threads were by default assigned in > round-robin fashion. However it was causing issues in > guest since CPU threads from the same socket/core could > be placed on different NUMA nodes. > Commit fb43b73b (pc: fix

[Qemu-devel] [PULL 11/23] Add QemuMacDrivers qemu_vga.ndrv revision d4e7d7a built as submodule

From: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- Makefile | 3 ++- pc-bios/qemu_vga.ndrv | Bin 0 -> 14752 bytes 2 files changed, 2 insertions(+), 1

[Qemu-devel] [PULL 22/23] pnv: Fix build failures on some host platforms

This makes some changes to fix build failures on the 'min-glib' docker image, and maybe other platforms with a buildchain that's less tolerant about duplicated typedefs. Signed-off-by: David Gibson --- include/hw/ppc/pnv.h | 3 +-- include/hw/ppc/pnv_lpc.h | 4

[Qemu-devel] [PULL 23/23] target/ppc: Avoid printing wrong aliases in CPU help text

From: Thomas Huth When running with KVM, we update the "family" CPU alias to point to the right host CPU type, so that it for example possible to use "-cpu POWER8" on a POWER8NVL host. However, the function for printing the list of available CPU models is called earlier than

[Qemu-devel] [PULL 21/23] target/ppc: Allow workarounds for POWER9 DD1

POWER9 DD1 silicon has some bugs which mean it a) isn't really compliant with the ISA v3.00 and b) require a number of special workarounds in the kernel. At the moment, qemu isn't aware of DD1. For TCG we don't really want it to be (why bother emulating buggy silicon). But with KVM, the guest

[Qemu-devel] [PULL 16/23] target/ppc: Change tlbie invalid fields for POWER9 support

From: Suraj Jitindar Singh The tlbie[l] instructions are used to invalidate TLB entries used to cache address translations. In ISAv3.00 (POWER9) more fields were added to the tblie[l] instructions which were previously invalid. We don't care about any of these new

[Qemu-devel] [PULL 17/23] target/ppc: Implement ISA V3.00 radix page fault handler

From: Suraj Jitindar Singh ISA V3.00 introduced a new radix mmu model. Implement the page fault handler for this so we can run a tcg guest in radix mode and perform address translation correctly. In real mode (mmu turned off) addresses are masked to remove the top 4

[Qemu-devel] [PULL 18/23] target/ppc: Enable RADIX mmu mode for pseries TCG guest

From: Suraj Jitindar Singh Now that we have added all the infrastructure we can enable a pseries TCG guest to use radix. In order to do this we have to add the appropriate bits to the ibm,arch-vec-5-platform-support vector to represent that we support both hash and

[Qemu-devel] [PULL 20/23] spapr: Don't accidentally advertise HTM support on POWER9

Logic in spapr_populate_pa_features() enables the bit advertising Hardware Transactional Memory (HTM) in the guest's device tree only when KVM advertises its availability with the KVM_CAP_PPC_HTM feature. However, this assumes that the HTM bit is off in the base template used for the device tree

[Qemu-devel] [PULL 10/23] Add QemuMacDrivers as submodule

From: Mark Cave-Ayland The QemuMacDrivers project provides virtualisation drivers for PPC MacOS guests. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- .gitmodules | 3 +++

[Qemu-devel] [PULL 13/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs

From: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/ppc/mac_newworld.c | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PULL 14/23] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE

From: Suraj Jitindar Singh The UPRT and GTSE bits are set when a guest calls H_REGISTER_PROCESS_TABLE to choose determine how address translation is performed. Currently these bits in the LPCR are only set for the cpu which handles the H_CALL, however they need to be

[Qemu-devel] [PULL 08/23] ppc/xics: Fix stale irq->status bits after get

From: Sam Bobroff ics_get_kvm_state() "or"s set bits into irq->status but does not mask out clear bits. Correct this by initializing the IRQ status to zero before adding bits to it. Signed-off-by: Sam Bobroff Signed-off-by: David Gibson

[Qemu-devel] [PULL 15/23] target/ppc: Update tlbie to check privilege level based on GTSE

From: Suraj Jitindar Singh The Guest Translation Shootdown Enable (GTSE) bit in the Logical Partition Control Register (LPCR) can be set to enable a guest to use the tlbie instruction directly to invalidate translations. When the GTSE bit is set then the tlbie

[Qemu-devel] [PULL 09/23] ppc/xics: preserve P and Q bits for KVM IRQs

From: Sam Bobroff Kernel commit 17d48610ae0f ("KVM: PPC: Book 3S: XICS: Implement ICS P/Q states") added new bits to the state used by KVM IRQs. Currently, QEMU does not preserve these bits, so migrating (or otherwise saving and restoring) the guest state causes the P

[Qemu-devel] [PULL 06/23] tcg: enable MTTCG by default for PPC64 on x86

From: Nikunj A Dadhania This enables the multi-threaded system emulation by default for PPC64 guests using the x86_64 TCG back-end. Signed-off-by: Nikunj A Dadhania Reviewed-by: Alex Bennée Signed-off-by: David

[Qemu-devel] [PULL 07/23] target/ppc: do not reset reserve_addr in exec_enter

From: Nikunj A Dadhania In case when atomic operation is not supported, exit_atomic is called and we stop the world and execute the atomic operation. This results in a following call chain: tcg_gen_atomic_cmpxchg_tl() -> gen_helper_exit_atomic() ->

[Qemu-devel] [PULL 19/23] ppc: xics: fix compilation with CentOS 6

From: Paolo Bonzini The PowerPCCPU typedef is included twice if a file includes both hw/ppc/xics.h and target/ppc/cpu-qom.h. Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson

[Qemu-devel] [PULL 05/23] cpus: Fix CPU unplug for MTTCG

From: Bharata B Rao Ensure that the unplugged CPU thread is destroyed and the waiting thread is notified about it. This is needed for CPU unplug to work correctly in MTTCG mode. Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A

[Qemu-devel] [PULL 12/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs

From: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/ppc/mac_oldworld.c | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PULL 01/23] ppc/pnv: restrict BMC object to the BMC simulator

From: Cédric Le Goater Today, when a PowerNV guest runs, it uses the sensor definitions of the BMC simulator to populate the device tree. But an external IPMI BMC could also be used and, in that case, it is not (yet) possible to retrieve the sensor list. Generating the OEM SEL

[Qemu-devel] [PULL 02/23] target/ppc: Emulate LL/SC using cmpxchg helpers

From: Nikunj A Dadhania Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. However, portable parallel code is written assuming only cmpxchg which means that in practice this is a viable alternative. Signed-off-by: Nikunj A Dadhania

[Qemu-devel] [PULL 04/23] target/ppc: Generate fence operations

From: Nikunj A Dadhania Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+)

[Qemu-devel] [PULL 00/23] ppc-for-2.10 queue 20170511

yesterday (20170510), fixing an important style bug in one patch, and adding an extra couple of simple patches. Highlights of this set: * Some fixes for POWER9 * TCG support for POWER9 radix MMU * VGA rom for Mac machine types * Fixes for the XICS interrupt controller * MTTCG support

[Qemu-devel] [PULL 03/23] cputlb: handle first atomic write to the page

From: Nikunj A Dadhania In case where the conditional write is the first write to the page, TLB_NOTDIRTY will be set and stop_the_world is triggered. Handle this as a special case and set the dirty bit. After that fall through to the actual atomic instruction below.

Re: [Qemu-devel] [PATCH v3 09/12] intel_iommu: allow dev-iotlb context entry conditionally

On Thu, May 11, 2017 at 10:56:42AM +0800, Jason Wang wrote: > > > On 2017年05月10日 16:01, Peter Xu wrote: > >When device-iotlb is not specified, we should fail this check. > > > >Signed-off-by: Peter Xu > >--- > > hw/i386/intel_iommu.c | 13 - > > 1 file changed,

Re: [Qemu-devel] [PATCH v3 09/12] intel_iommu: allow dev-iotlb context entry conditionally

On 2017年05月10日 16:01, Peter Xu wrote: When device-iotlb is not specified, we should fail this check. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c

Re: [Qemu-devel] [PATCH v2 3/3] kvm: irqchip: skip update msi when disabled

On Tue, May 09, 2017 at 02:00:44PM +0800, Peter Xu wrote: > It's possible that one device kept its irqfd/virq there even when > MSI/MSIX was disabled globally for that device. One example is > virtio-net-pci (see commit f1d0f15a6 and virtio_pci_vq_vector_mask()). > It is used as a fast path to

[Qemu-devel] [PATCH v2 11/20] mirror: Switch mirror_do_read() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Convert another internal function (no semantic change). Signed-off-by: Eric Blake Reviewed-by: John Snow --- v2: rebase to earlier changes ---

[Qemu-devel] [PATCH v2 10/20] mirror: Switch mirror_cow_align() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Convert another internal function (no semantic change), and add mirror_clip_bytes() as a counterpart to mirror_clip_sectors(). Some of the conversion is a bit tricky, requiring temporaries

[Qemu-devel] [PATCH v2 18/20] block: Make bdrv_is_allocated() byte-based

We are gradually moving away from sector-based interfaces, towards byte-based. In the common case, allocation is unlikely to ever use values that are not naturally sector-aligned, but it is possible that byte-based values will let us be more precise about allocation at the end of an unaligned

[Qemu-devel] [PATCH v2 20/20] block: Make bdrv_is_allocated_above() byte-based

We are gradually moving away from sector-based interfaces, towards byte-based. In the common case, allocation is unlikely to ever use values that are not naturally sector-aligned, but it is possible that byte-based values will let us be more precise about allocation at the end of an unaligned

[Qemu-devel] [PATCH v2 08/20] mirror: Switch mirror_do_zero_or_discard() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Convert another internal function (no semantic change). Signed-off-by: Eric Blake Reviewed-by: John Snow --- v2: no change --- block/mirror.c | 20

[Qemu-devel] [PATCH v2 16/20] backup: Switch backup_do_cow() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Convert another internal function (no semantic change). Signed-off-by: Eric Blake Reviewed-by: John Snow --- v2: no change --- block/backup.c | 62

[Qemu-devel] [PATCH v2 19/20] block: Minimize raw use of bds->total_sectors

bdrv_is_allocated_above() was relying on intermediate->total_sectors, which is a field that can have stale contents depending on the value of intermediate->has_variable_length. An audit shows that we are safe (we were first calling through bdrv_co_get_block_status() which in turn calls

[Qemu-devel] [PATCH v2 15/20] backup: Switch block_backup.h to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Continue by converting the public interface to backup jobs (no semantic change), including a change to CowRequest to track by bytes instead of cluster indices. Note that this does not

[Qemu-devel] [PATCH v2 05/20] commit: Switch commit_populate() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Start by converting an internal function (no semantic change). Signed-off-by: Eric Blake Reviewed-by: John Snow --- v2: no change ---

[Qemu-devel] [PATCH v2 09/20] mirror: Update signature of mirror_clip_sectors()

Rather than having a void function that modifies its input in-place as the output, change the signature to reduce a layer of indirection and return the result. Suggested-by: John Snow Signed-off-by: Eric Blake --- v2: new patch --- block/mirror.c | 15

[Qemu-devel] [PATCH v2 17/20] backup: Switch backup_run() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Change the internal loop iteration of backups to track by bytes instead of sectors (although we are still guaranteed that we iterate by steps that are cluster-aligned). Signed-off-by: Eric

[Qemu-devel] [PATCH v2 14/20] backup: Switch BackupBlockJob to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Continue by converting an internal structure (no semantic change), and all references to tracking progress. Drop a redundant local variable bytes_per_cluster. Signed-off-by: Eric Blake

[Qemu-devel] [PATCH v2 02/20] trace: Show blockjob actions via bytes, not sectors

Upcoming patches are going to switch to byte-based interfaces instead of sector-based. Even worse, trace_backup_do_cow_enter() had a weird mix of cluster and sector indices. The trace interface is low enough that there are no stability guarantees, and therefore nothing wrong with changing our

[Qemu-devel] [PATCH v2 07/20] mirror: Switch MirrorBlockJob to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Continue by converting an internal structure (no semantic change), and all references to the buffer size. [checkpatch has a false positive on use of MIN() in this patch] Signed-off-by:

[Qemu-devel] [PATCH v2 13/20] block: Drop unused bdrv_round_sectors_to_clusters()

Now that the last user [mirror_iteration()] has converted to using bytes, we no longer need a function to round sectors to clusters. Signed-off-by: Eric Blake Reviewed-by: John Snow --- v2: hoist to earlier series, no change --- include/block/block.h | 4

[Qemu-devel] [PATCH v2 04/20] stream: Switch stream_run() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Change the internal loop iteration of streaming to track by bytes instead of sectors (although we are still guaranteed that we iterate by steps that are sector-aligned). Signed-off-by:

[Qemu-devel] [PATCH v2 01/20] blockjob: Track job ratelimits via bytes, not sectors

The user interface specifies job rate limits in bytes/second. It's pointless to have our internal representation track things in sectors/second, particularly since we want to move away from sector-based interfaces. Fix up a doc typo found while verifying that the ratelimit code handles the

[Qemu-devel] [PATCH v2 06/20] commit: Switch commit_run() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Change the internal loop iteration of committing to track by bytes instead of sectors (although we are still guaranteed that we iterate by steps that are sector-aligned). Signed-off-by:

[Qemu-devel] [PATCH v2 12/20] mirror: Switch mirror_iteration() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Change the internal loop iteration of mirroring to track by bytes instead of sectors (although we are still guaranteed that we iterate by steps that are both sector-aligned and multiples of

[Qemu-devel] [PATCH v2 00/20] make bdrv_is_allocated[_above] byte-based

There are patches floating around to add NBD_CMD_BLOCK_STATUS, but NBD wants to report status on byte granularity (even if the reporting will probably be naturally aligned to sectors or even much higher levels). I've therefore started the task of converting our block status code to report at a

[Qemu-devel] [PATCH v2 03/20] stream: Switch stream_populate() to byte-based

We are gradually converting to byte-based interfaces, as they are easier to reason about than sector-based. Start by converting an internal function (no semantic change). Signed-off-by: Eric Blake Reviewed-by: John Snow --- v2: no change ---

[Qemu-devel] [PATCH] spice: Use proper enum type for kbd led state

Although the Qemu and spice flags currently have the same value, it seems more correct to pass the spice flag values to spice_server_kbd_leds(), especially considering that this function already makes an effort to convert between the QEMU_*_LED and SPICE_KEYBOARD_MODIFIER_* values. Signed-off-by:

Re: [Qemu-devel] [PATCH v3 04/12] memory: fix address_space_get_iotlb_entry()

On Wed, May 10, 2017 at 04:01:47PM +0800, Peter Xu wrote: > This function has an assumption that we will definitely call translate() > once (or say, the addr will be located inside one IOMMU memory region), > otherwise an empty IOTLB will be returned. Nevertheless, this is not > what we want. When

Re: [Qemu-devel] [RFC PATCH 1/2] spapr: Make h_register_process_table hcall flags global

On Mon, May 08, 2017 at 02:36:16PM +0530, Bharata B Rao wrote: > The flags used in h_register_process_table hcall are needed in spapr.c > and hence move them to a header file. While doing so, give them > slightly specific names. > > Signed-off-by: Bharata B Rao

Re: [Qemu-devel] [RFC PATCH 2/2] spapr: Fix migration of Radix guests

On Mon, May 08, 2017 at 02:36:17PM +0530, Bharata B Rao wrote: > Currently HTAB savevm handlers get registered by default and migration > of radix guest will fail. > > - Ensure that HTAB savevm handlers are not registered for radix case. > - Ensure that we issue KVM_PPC_CONFIGURE_V3_MMU for radix

Re: [Qemu-devel] [PATCH 7/8] target/ppc: optimize various functions using extract op

On Wed, May 10, 2017 at 05:05:34PM -0300, Philippe Mathieu-Daudé wrote: > Applied using Coccinelle script. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: David Gibson > --- > target/ppc/translate.c | 9 +++-- >

Re: [Qemu-devel] [RFC PATCH v2] coccinelle: add a script to optimize tcg op using tcg_gen_extract()

Ok I just understood Richard explanation, so this patch is WRONG and I need to get some real rest :( On 05/10/2017 08:52 PM, Philippe Mathieu-Daudé wrote: Apply this script using: $ docker run -v `pwd`:`pwd` -w `pwd` petersenna/coccinelle \ --sp-file

Re: [Qemu-devel] [PATCH v3 09/15] target/sh4: optimize gen_store_fpr64

On 05/10/2017 03:26 PM, Aurelien Jarno wrote: Using extr and avoiding intermediate temps. Signed-off-by: Aurelien Jarno Reviewed-by: Philippe Mathieu-Daudé --- target/sh4/translate.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff

[Qemu-devel] [RFC PATCH v2] coccinelle: add a script to optimize tcg op using tcg_gen_extract()

Apply this script using: $ docker run -v `pwd`:`pwd` -w `pwd` petersenna/coccinelle \ --sp-file scripts/coccinelle/tcg_gen_extract.cocci \ --macro-file scripts/cocci-macro-file.h \ --dir target \ --in-place Signed-off-by: Philippe Mathieu-Daudé --- This is a

Re: [Qemu-devel] [Qemu-block] [PATCH 16/17] block: Make bdrv_is_allocated() byte-based

On 04/19/2017 04:40 PM, John Snow wrote: > > > On 04/19/2017 05:12 PM, Eric Blake wrote: >> On 04/19/2017 03:32 PM, John Snow wrote: >> @@ -279,9 +280,9 @@ static int mig_save_device_bulk(QEMUFile *f, BlkMigDevState *bmds) /* Skip unallocated sectors; intentionally

Re: [Qemu-devel] [Qemu-block] [PATCH 17/17] block: Make bdrv_is_allocated_above() byte-based

On 04/24/2017 08:48 PM, Eric Blake wrote: >> >> >>> -n = psectors_inter; >>> + offset + pnum_inter < (intermediate->total_sectors * >>> +BDRV_SECTOR_SIZE))) { >> >> Naive question: not worth using either bdrv_getlength for bytes, or the

Re: [Qemu-devel] [PATCH 1/8] coccinelle: add a script to optimize tcg op using tcg_gen_extract()

On 05/10/2017 05:19 PM, Richard Henderson wrote: On 05/10/2017 01:05 PM, Philippe Mathieu-Daudé wrote: +-tcg_gen_shri_tl(ret, arg, ofs); +-tcg_gen_andi_tl(ret, ret, len); ++tcg_gen_extract_tl(ret, arg, ofs, len); You can't simply copy the and mask to the extract length. You need to verify

Re: [Qemu-devel] [PATCH v2 1/3] visitor: Add 'supported_qtypes' parameter to visit_start_alternate()

On Wed, May 10, 2017 at 03:16:56PM +0200, Markus Armbruster wrote: > Eduardo Habkost writes: > > > This will allow visitors to make decisions based on the supported qtypes > > of a given alternate type. The new parameter can replace the old > > 'promote_int' argument, as

[Qemu-devel] [PATCH 2/2] tcx: make display updates thread safe

Signed-off-by: Mark Cave-Ayland --- hw/display/tcx.c | 68 +++--- 1 file changed, 24 insertions(+), 44 deletions(-) diff --git a/hw/display/tcx.c b/hw/display/tcx.c index 0e66dcd..6593c1d 100644 ---

[Qemu-devel] [PATCH 0/2] cg3/tcx: make display updates thread safe

Now the previous fixes/cleanups have been applied, it is a fairly trivial exercise to make cg3/tcx display updates thread safe. Gerd, do you want to take these patches via your vga queue? Signed-off-by: Mark Cave-Ayland Mark Cave-Ayland (2): cg3: make display

[Qemu-devel] [PATCH 1/2] cg3: make display updates thread safe

Signed-off-by: Mark Cave-Ayland --- hw/display/cg3.c | 41 + 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/hw/display/cg3.c b/hw/display/cg3.c index 7ef8a96..1de15a1 100644 --- a/hw/display/cg3.c +++

Re: [Qemu-devel] [PATCH 2/8] target/arm: optimize smul_dual() and neon_trn_u8() using extract op

On 05/10/2017 05:20 PM, Richard Henderson wrote: On 05/10/2017 01:05 PM, Philippe Mathieu-Daudé wrote: -tcg_gen_shri_i32(t1, t1, 8); -tcg_gen_andi_i32(t1, t1, 0x00ff00ff); +tcg_gen_extract_i32(t1, t1, 8, 0x00ff00ff); This is very wrong. See my previous comment. Arghhh I see, I

Re: [Qemu-devel] [PATCH 1/8] coccinelle: add a script to optimize tcg op using tcg_gen_extract()

On 05/10/2017 03:19 PM, Richard Henderson wrote: > On 05/10/2017 01:05 PM, Philippe Mathieu-Daudé wrote: >> +-tcg_gen_shri_tl(ret, arg, ofs); >> +-tcg_gen_andi_tl(ret, ret, len); >> ++tcg_gen_extract_tl(ret, arg, ofs, len); > > You can't simply copy the and mask to the extract length. > > You

Re: [Qemu-devel] [PATCH 1/8] coccinelle: add a script to optimize tcg op using tcg_gen_extract()

On 05/10/2017 05:12 PM, Eric Blake wrote: On 05/10/2017 03:05 PM, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- scripts/coccinelle/tcg_gen_extract.cocci | 26 ++ 1 file changed, 26 insertions(+) create mode 100644

Re: [Qemu-devel] [PATCH 2/8] target/arm: optimize smul_dual() and neon_trn_u8() using extract op

On 05/10/2017 01:05 PM, Philippe Mathieu-Daudé wrote: -tcg_gen_shri_i32(t1, t1, 8); -tcg_gen_andi_i32(t1, t1, 0x00ff00ff); +tcg_gen_extract_i32(t1, t1, 8, 0x00ff00ff); This is very wrong. See my previous comment. r~

Re: [Qemu-devel] [PATCH 1/8] coccinelle: add a script to optimize tcg op using tcg_gen_extract()

On 05/10/2017 01:05 PM, Philippe Mathieu-Daudé wrote: +-tcg_gen_shri_tl(ret, arg, ofs); +-tcg_gen_andi_tl(ret, ret, len); ++tcg_gen_extract_tl(ret, arg, ofs, len); You can't simply copy the and mask to the extract length. You need to verify it's all low bits and convert that to a count of the

Re: [Qemu-devel] [PATCH 2/8] target/arm: optimize smul_dual() and neon_trn_u8() using extract op

On 05/10/2017 03:05 PM, Philippe Mathieu-Daudé wrote: > Applied using Coccinelle script. Thinking forward a year - if I want to reproduce this (to see if other instances have crept in), I have to dig up a mail archive to learn the formula you used. Better is to list your coccinelle command line

[Qemu-devel] [PATCH 8/8] target/sparc: optimize various functions using extract op

Applied using Coccinelle script. Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/translate.c | 15 +-- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index aa6734d54e..a92b5c425c 100644 ---

Re: [Qemu-devel] [PATCH 1/8] coccinelle: add a script to optimize tcg op using tcg_gen_extract()

On 05/10/2017 03:05 PM, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > scripts/coccinelle/tcg_gen_extract.cocci | 26 ++ > 1 file changed, 26 insertions(+) > create mode 100644 scripts/coccinelle/tcg_gen_extract.cocci > >

Re: [Qemu-devel] [virtio-dev] RE: virtio-net: configurable TX queue size

On Wed, May 10, 2017 at 05:52:23PM +0800, Wei Wang wrote: > On 05/07/2017 12:39 PM, Wang, Wei W wrote: > > On 05/06/2017 04:37 AM, Michael S. Tsirkin wrote: > > > On Fri, May 05, 2017 at 10:27:13AM +0800, Jason Wang wrote: > > > > > > > > On 2017年05月04日 18:58, Wang, Wei W wrote: > > > > > Hi, > >

[Qemu-devel] [PATCH 5/8] target/m68k: optimize bcd_flags() using extract op

Applied using Coccinelle script. Signed-off-by: Philippe Mathieu-Daudé --- target/m68k/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 9f60fbc0db..babb9e2c5b 100644 ---

[Qemu-devel] [PATCH 6/8] target/mips: optimize bshfl() using extract op

Applied using Coccinelle script. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 3022f349cb..96177da9ae 100644 ---

[Qemu-devel] [PATCH 4/8] target/cris: optimize gen_swapb() using extract op

Applied using Coccinelle script. Signed-off-by: Philippe Mathieu-Daudé --- target/cris/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index 0ee05ca02d..c03403ac62 100644 ---

[Qemu-devel] [PATCH 2/8] target/arm: optimize smul_dual() and neon_trn_u8() using extract op

Applied using Coccinelle script. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/translate.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0b5a0bca06..3230efe1be 100644 ---

[Qemu-devel] [PATCH 7/8] target/ppc: optimize various functions using extract op

Applied using Coccinelle script. Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/translate.c | 9 +++-- target/ppc/translate/vsx-impl.inc.c | 21 +++-- 2 files changed, 10 insertions(+), 20 deletions(-) diff --git a/target/ppc/translate.c

[Qemu-devel] [PATCH 0/8] optimize various tcg_gen() functions using extract op

While reviewing a commit from Aurelien Jarno where he optimized a TCG generator for SH-4 [1] I found the same optimization done on PPC by Nikunj A Dadhania few months ago [2]. After asking on the ML about a cocci script [3] I thought it would be easier to learn about Coccinelle. citing Aurelien

[Qemu-devel] [PATCH 3/8] target/arm: optimize rev16() using extract op

Applied using Coccinelle script. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/translate-a64.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 24de30d92c..7ea130107e 100644 ---

[Qemu-devel] [PATCH 1/8] coccinelle: add a script to optimize tcg op using tcg_gen_extract()

Signed-off-by: Philippe Mathieu-Daudé --- scripts/coccinelle/tcg_gen_extract.cocci | 26 ++ 1 file changed, 26 insertions(+) create mode 100644 scripts/coccinelle/tcg_gen_extract.cocci diff --git a/scripts/coccinelle/tcg_gen_extract.cocci

Re: [Qemu-devel] [PATCH v4 4/4] fsdev: QMP interface for throttling

On 05/10/2017 03:41 AM, Pradeep Jagadeesh wrote: > This patch enables qmp interfaces for the fsdev > devices. This provides two interfaces one > for querying info of all the fsdev devices. The second one > to set the IO limits for the required fsdev device. > > Signed-off-by: Pradeep Jagadeesh

Re: [Qemu-devel] [PATCH v4 3/4] qmp: refactor duplicate code

On 05/10/2017 03:41 AM, Pradeep Jagadeesh wrote: > This patch factor out the duplicate qmp throttle interface code > that was present in both block and fsdev device files. > > Signed-off-by: Pradeep Jagadeesh > --- > blockdev.c | 53

Re: [Qemu-devel] [PULL 0/9] pci, virtio, vhost: fixes

Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PULL 0/9] pci, virtio, vhost: fixes Type: series Message-id: 1494443192-17177-1-git-send-email-...@redhat.com === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git

Re: [Qemu-devel] [PATCH v4 1/4] throttle: factor out duplicate code

On 05/10/2017 10:27 AM, Pradeep Jagadeesh wrote: >> >> Isn't it a bit overkill to introduce a new file for a single function ? >> Maybe you could simply move this to util/throttle.c ? >> > OK, but I will add one more function later patch. Still do you think > better to move to util/thottle.c? As

Re: [Qemu-devel] [PATCH] syscall: fix compiler warnings (clang 5)

>> >> The "for" loop scans the structure to find the rt_dev field, and we >> should always enter in the first "if", so "host_rt_dev_ptr" is always >> set. > > It's better indeed, I'll use g_assert_nonnull() and resend. Careful - we haven't yet resolved whether g_assert_nonnull() is safe to use.

Re: [Qemu-devel] [Question] SeaBIOS: cannot boot oracle linux if increase the maximum size of permanent high memory area

On Fri, May 05, 2017 at 10:49:05AM +, Gonglei (Arei) wrote: > Hi guys, > > Currently my workmate encountered an issues in the testing environment: > > A letter from him: > > In order to boot a BIG vm (with 4T mem, 255 vCPUs, 60 virtio-scsi > disk...), i have to increase the

[Qemu-devel] [PULL 7/9] iommu: Don't crash if machine is not PC_MACHINE

From: Eduardo Habkost Currently it's possible to crash QEMU using "-device *-iommu" and "-machine none": $ qemu-system-x86_64 -machine none -device amd-iommu qemu/hw/i386/amd_iommu.c:1140:amdvi_realize: Object 0x55627dafbc90 is not an instance of type

[Qemu-devel] [PULL 6/9] pc: add 2.10 machine type

From: Peter Xu CC: "Michael S. Tsirkin" CC: Paolo Bonzini CC: Richard Henderson CC: Eduardo Habkost Signed-off-by: Peter Xu Reviewed-by: Eduardo Habkost

[Qemu-devel] [PULL 9/9] acpi-defs: clean up open brace usage

patchew has been saying: ERROR: open brace '{' following struct go on the same line Fix up acpi-defs.h to follow this rule. Signed-off-by: Michael S. Tsirkin --- include/hw/acpi/acpi-defs.h | 34 -- 1 file changed, 12 insertions(+), 22

[Qemu-devel] [PULL 4/9] libvhost-user: fix crash when rings aren't ready

From: Marc-André Lureau Calling libvhost-user functions like vu_queue_get_avail_bytes() when the queue doesn't yet have addresses will result in the crashes like the following: Program received signal SIGSEGV, Segmentation fault. 0x55c414112ce4 in

[Qemu-devel] [PULL 8/9] ACPI: don't call acpi_pcihp_device_plug_cb on xen

From: Bruce Rogers Commit f0c9d64a exposed the issue that with a xenfv machine using pci passthrough, acpi pci hotplug code was being executed by mistake. Guard calls to acpi_pcihp_device_plug_cb (and corresponding acpi_pcihp_device_unplug_cb) with a check for xen_enabled().

  1   2   3   4   >