Re: [Qemu-devel] [PATCH 4/4] vvfat: initialize memory after allocating it

Le 16/07/2017 à 00:24, Philippe Mathieu-Daudé a écrit : Hi Hervé, On 07/15/2017 10:28 AM, Hervé Poussineau wrote: This prevents some host to guest memory content leaks. Fixes: https://bugs.launchpad.net/qemu/+bug/1599539 Signed-off-by: Hervé Poussineau ---

[Qemu-devel] [Bug 1286253] Re: virtio-net acceleration features not set when plugged into backend dynamically

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1286253 Title: virtio-net

Re: [Qemu-devel] [PATCH v2 09/27] linux-user/sh4: Clean env->flags on signal boundaries

On 07/15/2017 12:59 PM, Aurelien Jarno wrote: On 2017-07-06 16:20, Richard Henderson wrote: If a signal is delivered during the execution of a delay slot, or a gUSA region, clear those bits from the environment so that the signal handler does not start in that same state. How are signals

Re: [Qemu-devel] [PATCH v2 06/27] target/sh4: Handle user-space atomics

On 07/15/2017 12:14 PM, Aurelien Jarno wrote: On 2017-07-06 16:20, Richard Henderson wrote: For uniprocessors, SH4 uses optimistic restartable atomic sequences. Upon an interrupt, a real kernel would simply notice magic values in the registers and reset the PC to the start of the sequence. For

Re: [Qemu-devel] [PATCH 09/22] exec-all: shrink tb->invalid to uint8_t

On Wed, Jul 12, 2017 at 13:06:23 -1000, Richard Henderson wrote: > You've got a problem here in that you're not including CF_COUNT_MASK in the > hash and you dropped the flush when changing to parallel_cpus = true. That > means you could find an old TB with CF_COUNT > 1. > > Not required for

Re: [Qemu-devel] [PATCH v2 01/27] target/sh4: Use cmpxchg for movco

On 2017-07-06 16:20, Richard Henderson wrote: > As for other targets, cmpxchg isn't quite right for ll/sc, > suffering from an ABA race, but is sufficient to implement > portable atomic operations. > > Signed-off-by: Richard Henderson > --- > target/sh4/cpu.h | 3 ++- >

Re: [Qemu-devel] [PATCH v2 4/4] qga: improve error handling in transfer_memory_block

ping? On Mon, Apr 10, 2017 at 10:20 PM, Michael Roth wrote: > Quoting Philippe Mathieu-Daudé (2017-04-07 17:20:16) >> Suggested-by: Michael Roth >> Signed-off-by: Philippe Mathieu-Daudé > > Reviewed-by: Michael Roth

Re: [Qemu-devel] [PATCH v2 09/27] linux-user/sh4: Clean env->flags on signal boundaries

On 2017-07-06 16:20, Richard Henderson wrote: > If a signal is delivered during the execution of a delay slot, > or a gUSA region, clear those bits from the environment so that > the signal handler does not start in that same state. How are signals delivered in linux-user? At least in system mode

Re: [Qemu-devel] [PATCH v2 08/27] linux-user/sh4: Notice gUSA regions during signal delivery

On 2017-07-06 16:20, Richard Henderson wrote: > We translate gUSA regions atomically in a parallel context. > But in a serial context a gUSA region may be interrupted. > In that case, restart the region as the kernel would. > > Signed-off-by: Richard Henderson > --- >

Re: [Qemu-devel] [PATCH 4/4] vvfat: initialize memory after allocating it

Hi Hervé, On 07/15/2017 10:28 AM, Hervé Poussineau wrote: This prevents some host to guest memory content leaks. Fixes: https://bugs.launchpad.net/qemu/+bug/1599539 Signed-off-by: Hervé Poussineau --- block/vvfat.c | 1 + 1 file changed, 1 insertion(+) diff --git

Re: [Qemu-devel] [PATCH v2 06/27] target/sh4: Handle user-space atomics

On 07/16/2017 12:14 AM, Aurelien Jarno wrote: > Do you have actually have a good documentation about gUSA? I have found > a few documents (some of them in Japanese), the most complete one being > the LinuxTag paper. The ABI is also described in the kernel and the > glibc. That said I am missing

Re: [Qemu-devel] [PATCH v2 06/27] target/sh4: Handle user-space atomics

On 2017-07-06 16:20, Richard Henderson wrote: > For uniprocessors, SH4 uses optimistic restartable atomic sequences. > Upon an interrupt, a real kernel would simply notice magic values in > the registers and reset the PC to the start of the sequence. > > For QEMU, we cannot do this in quite the

Re: [Qemu-devel] [PATCH 16/28] nios2: replace cpu_nios2_init() with cpu_generic_init()

On 07/14/2017 10:52 AM, Igor Mammedov wrote: cpu_nios2_init() always falls back to TYPE_NIOS2_CPU object regardless of cpu_model. Put fallback logic into nios2_cpu_class_by_name() which would translate any cpu_model into TYPE_NIOS2_CPU class and replace cpu_nios2_init() with cpu_generic_init()

Re: [Qemu-devel] [PATCH 15/28] microblaze: replace cpu_mb_init() with cpu_generic_init()

On 07/14/2017 10:52 AM, Igor Mammedov wrote: cpu_mb_init() always falls back to TYPE_MICROBLAZE_CPU object regardless of cpu_model. Put fallback logic into mb_cpu_class_by_name() which would translate any cpu_model into TYPE_MICROBLAZE_CPU class and replace cpu_mb_init() with cpu_generic_init().

Re: [Qemu-devel] [PATCH 02/28] mips: MIPSCPU model subclasses

On 07/14/2017 10:51 AM, Igor Mammedov wrote: Register separate QOM types for each mips cpu model, so it would be possible to reuse generic CPU creation routines. Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé --- CC: Aurelien Jarno

Re: [Qemu-devel] [PATCH 03/28] mips: replace cpu_mips_init() with cpu_generic_init()

On 07/14/2017 10:51 AM, Igor Mammedov wrote: now cpu_mips_init() reimplements subset of cpu_generic_init() tasks, so just drop it and use cpu_generic_init() directly. Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé --- CC: Aurelien

Re: [Qemu-devel] [PATCH 01/28] mips: cpu: move mmu/fpu/mvp_init to realize time

On 07/14/2017 10:51 AM, Igor Mammedov wrote: it will help to replace custom cpu_mips_init() with cpu_generic_init(). Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé --- CC: Aurelien Jarno CC: Yongbok Kim

Re: [Qemu-devel] [PATCH 2/4] vvfat: add a constant for bootsector name

On 07/15/2017 10:28 AM, Hervé Poussineau wrote: Also add links to related compatibility problems. Signed-off-by: Hervé Poussineau Reviewed-by: Philippe Mathieu-Daudé --- block/vvfat.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-)

Re: [Qemu-devel] [PATCH 14/28] m68k: replace cpu_m68k_init() with cpu_generic_init()

Le 15/07/2017 à 20:08, Richard Henderson a écrit : > On 07/14/2017 03:52 AM, Igor Mammedov wrote: >> @@ -230,6 +230,8 @@ static void m68k_cpu_realizefn(DeviceState *dev, >> Error **errp) >> M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev); >> Error *local_err = NULL; >> +

[Qemu-devel] [RFC] RFC on Backup tool

This is a Request For Comments patch for qemu backup tool. As an Outreachy intern, I am assigned to the project for creating a backup tool. qemu-backup will be a command-line tool for performing full and incremental disk backups on running VMs. It is intended as a reference implementation for

[Qemu-devel] How to support AMD acceleration on Windows host

Hello all, - QEMU is a great work. Thanks for your effor. -  I am a begginer of QEMU. I dont't found the way to support AMD acceleration  on Windows host. I want to run x86 ABI android rom(or Android-x86) on AMD CPU quickly. - As I know:         - KQEMU isnot support HW CPU Virtualization

[Qemu-devel] [Bug 1600563] Re: min_io_size is currently limited to size uint16_t

The value is set to uint16_t by mistake. The value is passed to Qemu in bytes, but then it is divided by the sector size and passed to the vm in sectors through a 16 bit register field. The vm kernel then multiplies it again by sector size and shows (through /sys/block/x/queue) the value in bytes.

Re: [Qemu-devel] [PATCH 14/28] m68k: replace cpu_m68k_init() with cpu_generic_init()

On 07/14/2017 03:52 AM, Igor Mammedov wrote: @@ -230,6 +230,8 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp) M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev); Error *local_err = NULL; +register_m68k_insns(>env); + I think it would make more sense to do this

Re: [Qemu-devel] [PATCH 13/28] hppa: replace cpu_hppa_init() with cpu_generic_init()

On 07/14/2017 03:52 AM, Igor Mammedov wrote: drop custom cpu_hppa_init() in favor of cpu_generic_init(), to make cpu_generic_init() work all we need is to provide cc->class_by_name callback that would resolve any cpu_model to the sole TYPE_HPPA_CPU to match current behaviour. Signed-off-by:

Re: [Qemu-devel] [PATCH 12/28] alpha: replace cpu_alpha_init() with cpu_generic_init()

On 07/14/2017 03:52 AM, Igor Mammedov wrote: cpu_alpha_init() used to provide default fallback if invalid (i.e. non existent) cpu_model were provided. dp264 machine provides its own default so sole user of fallback is [bsd|linux]-user targets which specifies 'any' cpu model that fallbacks to

Re: [Qemu-devel] [PATCH v13 22/26] target/arm: [tcg] Port to tb_stop

On 07/14/2017 09:56 PM, Lluís Vilanova wrote: Richard Henderson writes: On 07/13/2017 11:42 PM, Lluís Vilanova wrote: -dc->base.is_jmp = DISAS_SKIP; +dc->base.is_jmp = DISAS_NORETURN; Really should fold this back into the patch that introduced SKIP temporarily. Sorry, I

Re: [Qemu-devel] [PATCH v13 18/26] target/arm: [tcg] Port to breakpoint_check

On 07/14/2017 09:56 PM, Lluís Vilanova wrote: Another possibility is is_jmp = DISAS_TOO_MANY, and exit the translation loop after the breakpoint check only for is_jmp > DISAS_TOO_MANY. That allows all of the DISAS_TARGET_N values to exit as well. After a quick check, I see that arm uses both

[Qemu-devel] Could you please create an account

Hello all,       Could you please create an account for me? account: tim3385 email:  tim3...@gmail.com  thanks best Dong Hao Sent from YoMail for Gmail

[Qemu-devel] [PULL 6/8] target/s390x: Mark ETF3 and ETF3_ENH facilities as available

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/cpu_models.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 8433010..9e9e649 100644 ---

[Qemu-devel] [PULL 5/8] target/s390x: Implement TRTR

Drop TRT from the set of insns handled internally by EXECUTE. It's more important to adjust the existing helper to handle both TRT and TRTR. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/helper.h | 1 +

[Qemu-devel] [PULL 7/8] target/s390x: Allow to enable "idtes" feature for TCG

From: David Hildenbrand STFL bit 4 and 5 are just indications to the guest, which TLB entries an IDTE call will clear. These are performance indicators for the guest. STFL bit 4: INVALIDATE DAT TABLE ENTRY (IDTE) performs the invalidation-and-clearing operation by

[Qemu-devel] [PULL 3/8] target/s390x: Tidy SRST

Since we require all registers saved on input, read R0 from ENV instead of passing it manually. Recognize the specification exception when R0 contains incorrect data. Keep high bits of result registers unmodified when in 31 or 24-bit mode. Reviewed-by: Aurelien Jarno

[Qemu-devel] [PULL 8/8] target/s390x: Fix risbg handling

The rotation is to the left, but extract shifts to the right. The computation of the extract parameters needs adjusting. For the entry condition, simplify 64 - rot + len <= 64 -rot + len <= 0 len <= rot Reviewed-by: Aurelien Jarno Reported-by:

[Qemu-devel] [PULL 1/8] target/s390x: Implement CSST

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/helper.h | 1 + target/s390x/cpu_models.c | 2 + target/s390x/mem_helper.c | 189 + target/s390x/translate.c | 13 +++-

[Qemu-devel] [PULL 0/8] target/s390x tcg improvements

: vmgenid-test: use boot-sector infrastructure (2017-07-14 17:03:03 +0100) are available in the git repository at: git://github.com/rth7680/qemu.git tags/pull-s390-20170715 for you to fetch changes up to 4fb4047e74c21a3692360b9b1df473d7512d8055: target/s390x: Fix risbg handling (2017-07-15

[Qemu-devel] [PULL 4/8] target/s390x: Implement SRSTU

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/helper.h | 1 + target/s390x/mem_helper.c | 41 + target/s390x/translate.c | 13 + target/s390x/insn-data.def | 2

[Qemu-devel] [PULL 2/8] target/s390x: Implement CONVERT UNICODE insns

Reviewed-by: Aurelien Jarno Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson --- target/s390x/helper.h | 6 + target/s390x/mem_helper.c | 310 + target/s390x/translate.c |

Re: [Qemu-devel] [PATCH] slirp: fill error when failing to initialize user network

HEllo, Hervé Poussineau, on sam. 15 juil. 2017 18:43:50 +0200, wrote: > With "-netdev user,id=net0,dns=1.2.3.4" > error was: > qemu-system-i386: -netdev user,id=net0,dns=1.2.3.4: Device 'user' could not > be initialized > > Error is now: > qemu-system-i386: -netdev user,id=net0,dns=1.2.3.4: DNS

[Qemu-devel] [PATCH] slirp: fill error when failing to initialize user network

With "-netdev user,id=net0,dns=1.2.3.4" error was: qemu-system-i386: -netdev user,id=net0,dns=1.2.3.4: Device 'user' could not be initialized Error is now: qemu-system-i386: -netdev user,id=net0,dns=1.2.3.4: DNS doesn't belong to network Signed-off-by: Hervé Poussineau

Re: [Qemu-devel] [PATCH v5 2/3] ACPI: Add APEI GHES Table Generation support

Michael, Thanks for the review and comments. > -邮件原件- > 发件人: Michael S. Tsirkin [mailto:m...@redhat.com] > 主题: Re: [PATCH v5 2/3] ACPI: Add APEI GHES Table Generation support > > On Wed, Jul 12, 2017 at 10:08:16AM +0800, Dongjiu Geng wrote: > > This implements APEI GHES Table by

[Qemu-devel] [PATCH] qga-win32: remove a redundancy code

In the first line of run_agent,it has set ga_state = s,don't need set ga_state = s again behind. Signed-off-by: Peng Hao --- qga/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qga/main.c b/qga/main.c index 405c129..dcd6104 100644 ---

[Qemu-devel] [PATCH 3/4] vvfat: correctly parse non-ASCII short and long file names

Write support works again when image contains non-ASCII names. It is either the case when user created a non-ASCII filename, or when initial directory contained a non-ASCII filename (since 0c36111f57ec2188f679e7fa810291b7386bdca1) Signed-off-by: Hervé Poussineau ---

[Qemu-devel] [PATCH 2/4] vvfat: add a constant for bootsector name

Also add links to related compatibility problems. Signed-off-by: Hervé Poussineau --- block/vvfat.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/block/vvfat.c b/block/vvfat.c index c2674d7703..e585a8e0be 100644 --- a/block/vvfat.c +++

[Qemu-devel] [PATCH 4/4] vvfat: initialize memory after allocating it

This prevents some host to guest memory content leaks. Fixes: https://bugs.launchpad.net/qemu/+bug/1599539 Signed-off-by: Hervé Poussineau --- block/vvfat.c | 1 + 1 file changed, 1 insertion(+) diff --git a/block/vvfat.c b/block/vvfat.c index afc6170a69..7340decef3

[Qemu-devel] [PATCH 0/4] vvfat: some fixes

Hi, This patchset is a follow-up for patch series sent here: http://lists.gnu.org/archive/html/qemu-devel/2017-05/msg05017.html Patches 1 and 2 define and use some constants to make the code more clear. Patch 3 make read-write mode work when using non-ASCII filenames. Patch 4 fixes the last

[Qemu-devel] [PATCH 1/4] vvfat: add constants for special values of name[0]

Signed-off-by: Hervé Poussineau --- block/vvfat.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/block/vvfat.c b/block/vvfat.c index 4fd28e1e87..c2674d7703 100644 --- a/block/vvfat.c +++ b/block/vvfat.c @@ -71,6 +71,11 @@ void

Re: [Qemu-devel] [PULL 0/4] slirp updates

Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PULL 0/4] slirp updates Message-id: 20170715123057.8529-1-samuel.thiba...@ens-lyon.org Type: series === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log

[Qemu-devel] [PULL 1/4] slirp: use DIV_ROUND_UP

From: Marc-André Lureau I used the clang-tidy qemu-round check to generate the fix: https://github.com/elmarco/clang-tools-extra Signed-off-by: Marc-André Lureau Signed-off-by: Samuel Thibault ---

[Qemu-devel] [PULL 0/4] slirp updates

warning: redirection vers https://people.debian.org/~sthibault/qemu.git/ The following changes since commit 4871b51b9241b10f4fd8e04bbb21577886795e25: vmgenid-test: use boot-sector infrastructure (2017-07-14 17:03:03 +0100) are available in the git repository at:

[Qemu-devel] [PULL 3/4] slirp: Handle error returns from slirp_send() in sosendoob()

From: Peter Maydell The code in sosendoob() assumes that slirp_send() always succeeds, but it might return an OS error code (for instance if the other end has disconnected). Catch these and return the caller either -1 on error or the number of urgent bytes actually

[Qemu-devel] [PULL 4/4] slirp: Handle error returns from sosendoob()

From: Peter Maydell sosendoob() can return a failure code, but all its callers ignore it. This is OK in sbappend(), as the comment there states -- we will try again later in sowrite(). Add a (void) cast to tell Coverity so. In sowrite() we do need to check the return

[Qemu-devel] [PULL 2/4] slirp: fork_exec(): Don't close() a negative number in fork_exec()

From: Peter Maydell In a fork_exec() error path we try to closesocket(s) when s might be a negative number because the thing that failed was the qemu_socket() call. Add a guard so we don't do this. (Spotted by Coverity: CID 1005727 issue 1 of 2.) Signed-off-by: Peter

Re: [Qemu-devel] [PATCH v2 2/2] slirp: Handle error returns from sosendoob()

Dr. David Alan Gilbert, on ven. 14 juil. 2017 15:24:19 +0100, wrote: > * Peter Maydell (peter.mayd...@linaro.org) wrote: > > sosendoob() can return a failure code, but all its callers ignore it. > > This is OK in sbappend(), as the comment there states -- we will try > > again later in sowrite().

Re: [Qemu-devel] [PATCH v5] Add manpage for QEMU Backup Tool

Hi, This series failed build test on s390x host. Please find the details below. Message-id: 1500118925-10569-1-git-send-email-chugh.ish...@research.iiit.ac.in Type: series Subject: [Qemu-devel] [PATCH v5] Add manpage for QEMU Backup Tool === TEST SCRIPT BEGIN === #!/bin/bash # Testing script

[Qemu-devel] [PATCH v5] Add manpage for QEMU Backup Tool

qemu-backup will be a command-line tool for performing full and incremental disk backups on running VMs. It is intended as a reference implementation for management stack and backup developers to see QEMU's backup features in action. The following commit is an initial implementation of manpage

Re: [Qemu-devel] [RFC 0/3] cryptodev: add vhost support

Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [RFC 0/3] cryptodev: add vhost support Message-id: 1500114070-181004-1-git-send-email-arei.gong...@huawei.com Type: series === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1

[Qemu-devel] [RFC 1/3] cryptodev: add vhost-user as a new cryptodev backend

Usage: -chardev socket,id=charcrypto0,path=/path/to/your/socket -object cryptodev-vhost-user,id=cryptodev0,chardev=charcrypto0 -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0 Signed-off-by: Gonglei Signed-off-by: Longpeng(Mike)

[Qemu-devel] [RFC 3/3] cryptodev-vhost-user: add crypto session handler

Introduce two vhost-user meassges: VHOST_USER_CREATE_CRYPTO_SESSION and VHOST_USER_CLOSE_CRYPTO_SESSION. At this point, the QEMU side support crypto operation in cryptodev host-user backend. Signed-off-by: Gonglei Signed-off-by: Longpeng(Mike)

[Qemu-devel] [RFC 0/3] cryptodev: add vhost support

Because the cryptodev-builtin beckend doesn't fit in production environment as its' poor performance. And the Intel guys are working on the DPDK vhost-crypto implementation. So let us push the cryptodev-vhost-user backend upstream so that the whole process can be accelerated. This is a RFC

[Qemu-devel] [RFC 2/3] cryptodev: add vhost support

Impliment the vhost-crypto's funtions, such as startup, stop and notification etc. Introduce an enum QCryptoCryptoDevBackendOptionsType in order to identify the cryptodev vhost backend is vhost-user or vhost-kernel-module (If exist). At this point, the cryptdoev-vhost-user works. Signed-off-by:

Re: [Qemu-devel] [PATCH v14 00/34] Generic translation framework

Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20170715094243.28371-1-...@twiddle.net Subject: [Qemu-devel] [PATCH v14 00/34] Generic translation framework Type: series === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git

[Qemu-devel] [PATCH v14 24/34] target/arm: [tcg] Port to translate_insn

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Message-Id: <150002485863.22386.13949856269576226529.st...@frigg.lan> [rth: Adjust for translate_insn interface

[Qemu-devel] [PATCH v14 34/34] target/arm: Perform per-insn cross-page check only for Thumb

ARM is a fixed-length ISA and we can compute the page crossing condition exactly once during init_disas_context. Signed-off-by: Richard Henderson --- target/arm/translate.c | 57 +- 1 file changed, 33 insertions(+), 24

[Qemu-devel] [PATCH v14 23/34] target/arm: [tcg, a64] Port to breakpoint_check

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Message-Id:

[Qemu-devel] [PATCH v14 28/34] target/arm: [tcg] Port to disas_log

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id:

[Qemu-devel] [PATCH v14 31/34] target/arm: [a64] Move page and ss checks to init_disas_context

Since AArch64 uses a fixed-width ISA, we can pre-compute the number of insns remaining on the page. Also, we can check for single-step once. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-)

[Qemu-devel] [PATCH v14 20/34] target/arm: [tcg] Port to tb_start

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id:

[Qemu-devel] [PATCH v14 27/34] target/arm: [tcg, a64] Port to tb_stop

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Message-Id:

[Qemu-devel] [PATCH v14 33/34] target/arm: Split out thumb_tr_translate_insn

We need not check for ARM vs Thumb state in order to dispatch disassembly of every instruction. Signed-off-by: Richard Henderson --- target/arm/translate.c | 134 +++-- 1 file changed, 86 insertions(+), 48 deletions(-) diff --git

[Qemu-devel] [PATCH v14 29/34] target/arm: [tcg, a64] Port to disas_log

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Message-Id:

[Qemu-devel] [PATCH v14 17/34] target/arm: [tcg] Port to DisasContextBase

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id:

[Qemu-devel] [PATCH v14 25/34] target/arm: [tcg, a64] Port to translate_insn

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Message-Id: <150002510079.22386.10164419868911710218.st...@frigg.lan> [rth: Adjust for translate_insn interface

[Qemu-devel] [PATCH v14 22/34] target/arm: [tcg, a64] Port to insn_start

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id:

[Qemu-devel] [PATCH v14 32/34] target/arm: Move ss check to init_disas_context

We can check for single-step just once. Signed-off-by: Richard Henderson --- target/arm/translate.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4b1230b..ebe1c1a 100644 ---

[Qemu-devel] [PATCH v14 21/34] target/arm: [tcg] Port to insn_start

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id:

[Qemu-devel] [PATCH v14 18/34] target/arm: [tcg] Port to init_disas_context

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id:

[Qemu-devel] [PATCH v14 15/34] target/i386: [tcg] Port to disas_log

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id:

[Qemu-devel] [PATCH v14 30/34] target/arm: [tcg] Port to generic translation framework

From: Lluís Vilanova Signed-off-by: Lluís Vilanova Message-Id: <150002631325.22386.10348327185029496649.st...@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.h | 8 +--- target/arm/translate-a64.c | 107

[Qemu-devel] [PATCH v14 16/34] target/i386: [tcg] Port to generic translation framework

From: Lluís Vilanova Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota Message-Id:

[Qemu-devel] [PATCH v14 19/34] target/arm: [tcg, a64] Port to init_disas_context

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id:

[Qemu-devel] [PATCH v14 13/34] target/i386: [tcg] Port to translate_insn

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id:

[Qemu-devel] [PATCH v14 26/34] target/arm: [tcg] Port to tb_stop

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Message-Id: <150002534291.22386.13499916738708680298.st...@frigg.lan> Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v14 11/34] target/i386: [tcg] Port to insn_start

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex

[Qemu-devel] [PATCH v14 14/34] target/i386: [tcg] Port to tb_stop

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id:

[Qemu-devel] [PATCH v14 07/34] target/arm: Set is_jmp properly after single-stepping

We have generated an exception, so use DISAS_NORETURN. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 1 + target/arm/translate.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c

[Qemu-devel] [PATCH v14 08/34] tcg: Add generic translation framework

From: Lluís Vilanova Signed-off-by: Lluís Vilanova Message-Id: <150002073981.22386.9870422422367410100.st...@frigg.lan> [rth: Moved max_insns adjustment from tb_start to init_disas_context. Removed pc_next return from translate_insn. Removed

[Qemu-devel] [PATCH v14 12/34] target/i386: [tcg] Port to breakpoint_check

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id:

[Qemu-devel] [PATCH v14 10/34] target/i386: [tcg] Port to init_disas_context

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id:

[Qemu-devel] [PATCH v14 05/34] target: [tcg] Use a generic enum for DISAS_ values

From: Lluís Vilanova Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id:

[Qemu-devel] [PATCH v14 09/34] target/i386: [tcg] Port to DisasContextBase

From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex

[Qemu-devel] [PATCH v14 03/34] target/i386: Use generic DISAS_* enumerators

This target is not sophisticated in its use of cleanups at the end of the translation loop. For the most part, any condition that exits the TB is dealt with by emitting the exiting opcode right then and there. Therefore the only is_jmp indicator that is needed is DISAS_NORETURN. For two stack

[Qemu-devel] [PATCH v14 04/34] target/arm: Use DISAS_NORETURN

Fold DISAS_EXC and DISAS_TB_JUMP into DISAS_NORETURN. In both cases all following code is dead. In the first case because we have exited the TB via exception; in the second case because we have exited the TB via goto_tb and its associated machinery. Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v14 06/34] target/arm: Delay check for magic kernel page

There's nothing magic about the exception that we generate in order to execute the magic kernel page. We can and should allow gdb to set a breakpoint at this location. Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++--- 1 file changed, 11

[Qemu-devel] [PATCH v14 00/34] Generic translation framework

This is my take on Lluis' v13. I've also written patches for Alpha, SH4, and HPPA as examples of more complicated cases. I have not included them here, but for the record: git://github.com/rth7680/qemu.git tgt-axp-2 tgt-sh4-2 tgt-pa have the patches. In the case of Alpha and SH4, there were

[Qemu-devel] [PATCH v14 01/34] Pass generic CPUState to gen_intermediate_code()

From: Lluís Vilanova Needed to implement a target-agnostic gen_intermediate_code() in the future. Signed-off-by: Lluís Vilanova Reviewed-by: David Gibson Reviewed-by: Richard Henderson Reviewed-by: Alex

[Qemu-devel] [PATCH v14 02/34] tcg: Add generic DISAS_NORETURN

This will allow some amount of cleanup to happen before switching the backends over to enum DisasJumpType. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index

Re: [Qemu-devel] [PATCH v3 2/8] target/s390x: Implement CONVERT UNICODE insns

On 07/14/2017 10:25 PM, Aurelien Jarno wrote: That said I still wonder if we can get generators like that: | static void in1_r1n(DisasContext *s, DisasFields *f, DisasOps *o) | { | int r1 = get_field(s->fields, r1); | o->in1 = tcg_const_i32(r1); | | #define SPEC_in1_r1n 0 and | static

Re: [Qemu-devel] [PATCH v3 1/8] target/s390x: Implement CSST

On 2017-07-14 14:22, Richard Henderson wrote: > On 07/14/2017 11:01 AM, Aurelien Jarno wrote: > > > +if (parallel_cpus) { > > > +int mask = 0; > > > +#if !defined(CONFIG_ATOMIC64) > > > +mask = -8; > > > +#elif !defined(CONFIG_ATOMIC128) > > > +mask = -16; > > > +#endif

Re: [Qemu-devel] [PATCH v3 2/8] target/s390x: Implement CONVERT UNICODE insns

On 2017-07-14 14:23, Richard Henderson wrote: > On 07/14/2017 11:08 AM, Aurelien Jarno wrote: > > On 2017-07-11 17:18, Thomas Huth wrote: > > > On 10.07.2017 22:45, Richard Henderson wrote: > > > > Signed-off-by: Richard Henderson > > > > --- > > > > target/s390x/helper.h

Re: [Qemu-devel] [PATCH v3.5 2/8] target/s390x: Implement CONVERT UNICODE insns

On 2017-07-11 08:23, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > v3.5: Added even register checks in the translator [thuth]. > --- > target/s390x/helper.h | 6 + > target/s390x/mem_helper.c | 310 > + >

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