Re: [Qemu-devel] New documentation for the LatticeMicro32 target

Am 2017-07-09 17:39, schrieb Programmingkid: I just made a documentation page for the LatticeMicro32 target. I need to know its current status, how much of this system is implemented, what software runs on it. If anyone could supply more information that would be appreciated. Pictures of this

Re: [Qemu-devel] [PATCH v5 2/3] ACPI: Add APEI GHES Table Generation support

Laszlo, Thanks for the comments. On 2017/7/14 3:41, Laszlo Ersek wrote: snip > > snip > >>> + >>> +error_source_table = (AcpiHardwareErrorSourceTable *)(table_data->data >>> ++ table_data->len - buffer->len); >>> +error_source_table->error_source_count = >>>

[Qemu-devel] [Bug 1181796] Re: Qemu locks up when incoming serial fills up

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1181796 Title: Qemu locks

Re: [Qemu-devel] [PATCH] qga-win32: remove a redundancy code

Cc'ing qemu-trivial On 07/15/2017 07:44 PM, Peng Hao wrote: In the first line of run_agent,it has set ga_state = s,don't need set ga_state = s again behind. Signed-off-by: Peng Hao Reviewed-by: Philippe Mathieu-Daudé --- qga/main.c | 2 +- 1 file

[Qemu-devel] [PATCH v3] spapr: disable decrementer during reset

Rebooting a SMP TCG guest is broken for both single/multi threaded TCG. When reset happens, all the CPUs are in halted state. First CPU is brought out of reset and secondary CPUs would be initialized by the guest kernel using a rtas call start-cpu. However, in case of TCG, decrementer interrupts

Re: [Qemu-devel] [Qemu-arm] [PATCH v5 2/6] armv7m: Convert armv7m.memory to DEFINE_PROP_LINK

On 07/16/2017 11:38 PM, Fam Zheng wrote: Signed-off-by: Fam Zheng Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index

Re: [Qemu-devel] [Qemu-arm] [PATCH v5 5/6] xilinx_axienet: Convert to DEFINE_PROP_LINK

On 07/16/2017 11:38 PM, Fam Zheng wrote: Signed-off-by: Fam Zheng Reviewed-by: Philippe Mathieu-Daudé --- hw/net/xilinx_axienet.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/hw/net/xilinx_axienet.c

Re: [Qemu-devel] [PATCH v5 6/6] xilinx_axidma: Convert to DEFINE_PROP_LINK

On 07/16/2017 11:38 PM, Fam Zheng wrote: Signed-off-by: Fam Zheng Reviewed-by: Philippe Mathieu-Daudé --- hw/dma/xilinx_axidma.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/hw/dma/xilinx_axidma.c

Re: [Qemu-devel] [PATCH v5 4/6] xlnx_zynqmp: Convert to DEFINE_PROP_LINK

On 07/16/2017 11:38 PM, Fam Zheng wrote: Signed-off-by: Fam Zheng Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/xlnx-zynqmp.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index

Re: [Qemu-devel] [Qemu-arm] [PATCH v5 1/6] armv7m: Convert bitband.source-mamory to DEFINE_PROP_LINK

On 07/16/2017 11:38 PM, Fam Zheng wrote: Signed-off-by: Fam Zheng Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index

[Qemu-devel] [PULL 15/15] travis: add no-TCG build

From: Paolo Bonzini It's fairly easy for --disable-tcg to bitrot. Test it in our CI. Signed-off-by: Paolo Bonzini Message-Id: <20170714093016.10897-1-pbonz...@redhat.com> Signed-off-by: Fam Zheng --- .travis.yml | 3 +++ 1 file

[Qemu-devel] [PULL 10/15] sheepdog: add queue_lock

From: Paolo Bonzini Reviewed-by: Stefan Hajnoczi Reviewed-by: Fam Zheng Signed-off-by: Paolo Bonzini Message-Id: <20170629132749.997-11-pbonz...@redhat.com> Signed-off-by: Fam Zheng ---

[Qemu-devel] [PULL 14/15] docker.py: Improve subprocess exit code handling

A few error handlings are missing because we ignore the subprocess exit code, for example "docker build" errors are currently ignored. Introduce _do_check() aside the existing _do() method and use it in a few places. Signed-off-by: Fam Zheng Message-Id:

[Qemu-devel] [PULL 09/15] qed: protect table cache with CoMutex

From: Paolo Bonzini This makes the driver thread-safe. The CoMutex is dropped temporarily while accessing the data clusters or the backing file. Signed-off-by: Paolo Bonzini Message-Id: <20170629132749.997-10-pbonz...@redhat.com> Reviewed-by: Stefan

[Qemu-devel] [PULL 13/15] docker.py: Drop infile parameter

The **kwargs can do this just well. Signed-off-by: Fam Zheng Message-Id: <20170712075528.22770-2-f...@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Fam Zheng --- tests/docker/docker.py | 6 ++ 1 file changed, 2

[Qemu-devel] [PULL 04/15] vpc: make it thread-safe

From: Paolo Bonzini Reviewed-by: Eric Blake Reviewed-by: Stefan Hajnoczi Reviewed-by: Fam Zheng Signed-off-by: Paolo Bonzini Message-Id: <20170629132749.997-5-pbonz...@redhat.com>

[Qemu-devel] [PULL 11/15] ssh: support I/O from any AioContext

From: Paolo Bonzini The coroutine may run in a different AioContext, causing the fd handler to busy wait. Fix this by resetting the handler in restart_coroutine, before the coroutine is restarted. Reviewed-by: Stefan Hajnoczi Reviewed-by: Fam Zheng

[Qemu-devel] [PULL 06/15] qed: move tail of qed_aio_write_main to qed_aio_write_{cow, alloc}

From: Paolo Bonzini This part is never called for in-place writes, move it away to avoid the "backwards" coding style typical of callback-based code. Reviewed-by: Stefan Hajnoczi Reviewed-by: Fam Zheng Signed-off-by: Paolo Bonzini

[Qemu-devel] [PULL 03/15] vdi: make it thread-safe

From: Paolo Bonzini The VirtualBox driver is using a mutex to order all allocating writes, but it is not protecting accesses to the bitmap because they implicitly happen under the AioContext mutex. Change this to use a CoRwlock explicitly. Reviewed-by: Eric Blake

[Qemu-devel] [PULL 05/15] vvfat: make it thread-safe

From: Paolo Bonzini Reviewed-by: Eric Blake Reviewed-by: Stefan Hajnoczi Reviewed-by: Fam Zheng Signed-off-by: Paolo Bonzini Message-Id: <20170629132749.997-6-pbonz...@redhat.com>

[Qemu-devel] [PULL 02/15] coroutine-lock: add qemu_co_rwlock_downgrade and qemu_co_rwlock_upgrade

From: Paolo Bonzini These functions are more efficient in the presence of contention. qemu_co_rwlock_downgrade also guarantees not to block, which may be useful in some algorithms too. Reviewed-by: Eric Blake Reviewed-by: Stefan Hajnoczi

[Qemu-devel] [PULL 08/15] qed: introduce bdrv_qed_init_state

From: Paolo Bonzini This will be used in the next patch, which will call bdrv_qed_do_open with a CoMutex taken. bdrv_qed_init_state provides a nice place to initialize it. Signed-off-by: Paolo Bonzini Message-Id:

[Qemu-devel] [PULL 12/15] docker: Don't enable networking as a side-effect of DEBUG=1

From: "Daniel P. Berrange" When trying to debug problems with tests it is natural to set DEBUG=1 when starting the docker environment. Unfortunately this has a side-effect of enabling an eth0 network interface in the container, which changes the operating environment of the

[Qemu-devel] [PULL 07/15] block: invoke .bdrv_drain callback in coroutine context and from AioContext

From: Paolo Bonzini This will let the callback take a CoMutex in the next patch. Reviewed-by: Stefan Hajnoczi Reviewed-by: Fam Zheng Signed-off-by: Paolo Bonzini Message-Id:

[Qemu-devel] [PULL 01/15] qcow2: call CoQueue APIs under CoMutex

From: Paolo Bonzini Reviewed-by: Eric Blake Reviewed-by: Stefan Hajnoczi Reviewed-by: Fam Zheng Signed-off-by: Paolo Bonzini Message-Id: <20170629132749.997-2-pbonz...@redhat.com>

[Qemu-devel] [PULL 00/15] Block and testing patches

The following changes since commit 4871b51b9241b10f4fd8e04bbb21577886795e25: vmgenid-test: use boot-sector infrastructure (2017-07-14 17:03:03 +0100) are available in the git repository at: git://github.com/famz/qemu.git tags/block-and-testing-pull-request for you to fetch changes up to

Re: [Qemu-devel] [PATCH 08/11] qed: introduce bdrv_qed_init_state

On Thu, 06/29 15:27, Paolo Bonzini wrote: > diff --git a/block/qed.c b/block/qed.c > index db390efdbd..8228a50f68 100644 > --- a/block/qed.c > +++ b/block/qed.c > @@ -363,6 +363,15 @@ static void coroutine_fn > bdrv_qed_co_drain(BlockDriverState *bs) > } > } > > +static void

Re: [Qemu-devel] [PATCH 0/3] migration: export cap/params to qdev props

On Fri, Jul 14, 2017 at 12:57:15PM -0300, Eduardo Habkost wrote: > On Fri, Jul 14, 2017 at 12:23:06PM +0800, Peter Xu wrote: > > On Wed, Jul 12, 2017 at 08:02:40PM +0100, Dr. David Alan Gilbert wrote: > > > * Peter Xu (pet...@redhat.com) wrote: > > > > We have the MigrationState as QDev now (which

[Qemu-devel] [Question] Seabios HANGs when mmio wirte in a nested vmware host wtih virito-scsi controller

Hello all, Recently, I met a werid question when i run a VM in the following platfrom: Vmware Vsphere 6.0/6.5 |-- centos 7.3 nested VM (with qemu 2.8, kmod 4.4.11, seabios 1.10) |-- VM (with virtio-scsi controller, modern mode) VM MUST hang in seabios when try to mmio write during

Re: [Qemu-devel] [PATCH 0/3] migration: export cap/params to qdev props

On Fri, Jul 14, 2017 at 05:32:10PM +0100, Dr. David Alan Gilbert wrote: > * Eduardo Habkost (ehabk...@redhat.com) wrote: > > On Fri, Jul 14, 2017 at 01:04:23PM +0800, Peter Xu wrote: > > > On Wed, Jul 12, 2017 at 04:05:58PM -0300, Eduardo Habkost wrote: > > > > On Wed, Jul 12, 2017 at 02:53:40PM

Re: [Qemu-devel] [RFC 16/29] vhost+postcopy: Stash RAMBlock and offset

On Fri, Jul 14, 2017 at 06:15:54PM +0100, Dr. David Alan Gilbert wrote: > * Peter Xu (pet...@redhat.com) wrote: > > On Wed, Jun 28, 2017 at 08:00:34PM +0100, Dr. David Alan Gilbert (git) > > wrote: > > > From: "Dr. David Alan Gilbert" > > > > > > Stash the RAMBlock and

[Qemu-devel] [PATCH v5 6/6] xilinx_axidma: Convert to DEFINE_PROP_LINK

Signed-off-by: Fam Zheng --- hw/dma/xilinx_axidma.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 3987b5f..9b48103 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@

[Qemu-devel] [PATCH v5 2/6] armv7m: Convert armv7m.memory to DEFINE_PROP_LINK

Signed-off-by: Fam Zheng --- hw/arm/armv7m.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8efc4e8..1c837da 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -132,12 +132,6 @@ static void

[Qemu-devel] [PATCH v5 5/6] xilinx_axienet: Convert to DEFINE_PROP_LINK

Signed-off-by: Fam Zheng --- hw/net/xilinx_axienet.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 5ffa739..d4c2c89 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c

[Qemu-devel] [PATCH v5 0/6] arm: Make use of DEFINE_PROP_LINK

This is the arm part that was left out from: https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg04006.html Make use of the new DEFINE_PROP_LINK, in favor of open coded the object_property_add_link. The advantage of it is the property now get reflected in the info qtree output, for a bit

[Qemu-devel] [PATCH v5 1/6] armv7m: Convert bitband.source-mamory to DEFINE_PROP_LINK

Signed-off-by: Fam Zheng --- hw/arm/armv7m.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index c8a11f2..8efc4e8 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -97,12 +97,6 @@ static void bitband_init(Object

[Qemu-devel] [PATCH v5 3/6] gicv3: Convert to DEFINE_PROP_LINK

Signed-off-by: Fam Zheng --- hw/intc/arm_gicv3_its_kvm.c | 19 +++ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 1f8991b..39903d5 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++

[Qemu-devel] [PATCH v5 4/6] xlnx_zynqmp: Convert to DEFINE_PROP_LINK

Signed-off-by: Fam Zheng --- hw/arm/xlnx-zynqmp.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 64f52f8..cd8a4aa 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -140,11 +140,6 @@

Re: [Qemu-devel] [RFC v2 0/8] VIRTIO-IOMMU device

> From: Jean-Philippe Brucker [mailto:jean-philippe.bruc...@arm.com] > Sent: Friday, July 14, 2017 7:26 PM > > On 14/07/17 08:20, Tian, Kevin wrote: > >> From: Jean-Philippe Brucker [mailto:jean-philippe.bruc...@arm.com] > >> Sent: Friday, July 7, 2017 11:15 PM > >> > >> On 07/07/17 07:21, Tian,

Re: [Qemu-devel] investigating TPM for OVMF-on-QEMU

Hi Laszlo This is a good summary. One minor comment is: 1) Tcg2Pei/Dxe are arechitecture driver. We do not expect a platform modify them. 2) Tcg2ConfigPei/Dxe are platform sample driver. A platform may have its own version based upon platform requirement. For example, if a platform supports

Re: [Qemu-devel] [PATCH v3 4/4] intel_iommu: implement mru list for iotlb

On Fri, Jul 14, 2017 at 03:28:09PM +0800, Jason Wang wrote: > > > On 2017年07月14日 12:32, Peter Xu wrote: > >On Thu, Jul 13, 2017 at 04:48:42PM +0800, Jason Wang wrote: > >> > >>On 2017年07月12日 16:13, Peter Xu wrote: > >>>It is not wise to disgard all the IOTLB cache when cache size reaches >

Re: [Qemu-devel] [RFC v2 6/8] virtio-iommu: Implement the translation and commands

On Fri, Jul 14, 2017 at 12:25:13PM +0100, Jean-Philippe Brucker wrote: > Hi Peter, > > On 14/07/17 03:17, Peter Xu wrote: > > > > [...] > > > >> static int virtio_iommu_unmap(VirtIOIOMMU *s, > >> @@ -133,10 +227,64 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, > >> uint64_t virt_addr =

Re: [Qemu-devel] [RFC v2 6/8] virtio-iommu: Implement the translation and commands

On Fri, Jul 14, 2017 at 06:40:34AM +, Bharat Bhushan wrote: > Hi Peter, > > > -Original Message- > > From: Peter Xu [mailto:pet...@redhat.com] > > Sent: Friday, July 14, 2017 7:48 AM > > To: Eric Auger > > Cc: eric.auger@gmail.com; peter.mayd...@linaro.org;

Re: [Qemu-devel] [PATCH] target/ppc: fix CPU hotplug when radix is enabled (TCG)

On Fri, Jul 14, 2017 at 06:13:58PM +0200, Cédric Le Goater wrote: > But when a guest initializes radix mode, it issues a H_REGISTER_PROC_TBL > to update the LPCR of all CPUs. Hot-plugged CPUs inherit from the same > setting under KVM but not under TCG. So, Let's check for radix and update > the

Re: [Qemu-devel] [PATCH v2 06/27] target/sh4: Handle user-space atomics

On 2017-07-16 11:59, Richard Henderson wrote: > On 07/16/2017 11:43 AM, Aurelien Jarno wrote: > > Indeed, if the same atomic code is used often it might be better to have > > it cached. That said it's only true for TB that are recognized, as IIRC > > TB with the exclusive lock are not cached. > >

Re: [Qemu-devel] [PATCH v2 06/27] target/sh4: Handle user-space atomics

On 07/16/2017 11:43 AM, Aurelien Jarno wrote: Indeed, if the same atomic code is used often it might be better to have it cached. That said it's only true for TB that are recognized, as IIRC TB with the exclusive lock are not cached. At the moment they are not. But in Emilio's multi-threaded

Re: [Qemu-devel] [PATCH v2 01/27] target/sh4: Use cmpxchg for movco

On 2017-07-16 01:22, Aurelien Jarno wrote: > On 2017-07-06 16:20, Richard Henderson wrote: > > As for other targets, cmpxchg isn't quite right for ll/sc, > > suffering from an ABA race, but is sufficient to implement > > portable atomic operations. > > > > Signed-off-by: Richard Henderson

Re: [Qemu-devel] [PATCH v2 06/27] target/sh4: Handle user-space atomics

On 2017-07-16 09:35, Richard Henderson wrote: > On 07/16/2017 05:18 AM, Aurelien Jarno wrote: > > That said for further improvements did you consider decoding the gUSA > > section in a helper. It might avoid having to emulate the atomic > > sequence with 3 TBs in the worst case (the original one,

[Qemu-devel] [PATCHv3 2/2] pci: add reserved slot check to do_pci_register_device()

Add a new slot_reserved_mask bitmask to PCIBus indicating whether or not each PCI slot on the bus is reserved. Ensure that it is initialised to zero to maintain the existing behaviour that all slots are available by default, and add the additional check with appropriate error reporting to

[Qemu-devel] [PATCH v2 34/45] tcg: define tcg_init_ctx and make tcg_ctx a pointer

Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this

[Qemu-devel] [PATCH v2 43/45] tcg: introduce regions to split code_gen_buffer

This is groundwork for supporting multiple TCG contexts. The naive solution here is to split code_gen_buffer statically among the TCG threads; this however results in poor utilization if translation needs are different across TCG threads. What we do here is to add an extra layer of indirection,

[Qemu-devel] [PATCH v2 45/45] tcg: enable multiple TCG contexts in softmmu

This enables parallel TCG code generation. However, we do not take advantage of it yet since tb_lock is still held during tb_gen_code. In user-mode we use a single TCG context; see the documentation added to tcg_region_init for the rationale. Note that targets do not need any conversion: targets

[Qemu-devel] [PATCH v2 28/45] translate-all: use a binary search tree to track TBs in TBContext

This is a prerequisite for supporting multiple TCG contexts, since we will have threads generating code in separate regions of code_gen_buffer. For this we need a new field (.size) in struct tb_tc to keep track of the size of the translated code. This field adds a 4-byte hole to the struct (and

[Qemu-devel] [PATCHv3 1/2] pci: move check for existing devfn into new pci_bus_devfn_available() helper

Also touch up the logic in do_pci_register_device() accordingly. Signed-off-by: Mark Cave-Ayland --- hw/pci/pci.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 0c6f74a..efc9c86 100644 ---

[Qemu-devel] [PATCH v2 40/45] osdep: introduce qemu_mprotect_rwx/none

Signed-off-by: Emilio G. Cota --- include/qemu/osdep.h | 2 ++ util/osdep.c | 40 2 files changed, 42 insertions(+) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 3cb36e6..dcecfbc 100644 --- a/include/qemu/osdep.h

[Qemu-devel] [PATCH v2 36/45] tcg: dynamically allocate optimizer globals + fold into TCGContext

Groundwork for supporting multiple TCG contexts. Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 12 tcg/optimize.c | 40 +++- 2 files changed, 35 insertions(+), 17 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index

[Qemu-devel] [PATCH v2 38/45] tcg: distribute profiling counters across TCGContext's

This is groundwork for supporting multiple TCG contexts. To avoid scalability issues when profiling info is enabled, this patch makes the profiling info counters distributed via the following changes: 1) Consolidate profile info into its own struct, TCGProfile, which TCGContext also includes.

[Qemu-devel] [PATCH v2 44/45] translate-all: do not allocate a guard page for code_gen_buffer

TCG regions already have a guard page. Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 47 --- 1 file changed, 12 insertions(+), 35 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index

[Qemu-devel] [PATCH v2 15/45] target/arm: check CF_PARALLEL instead of parallel_cpus

Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota --- target/arm/helper-a64.h| 4 target/arm/helper-a64.c| 38 -- target/arm/op_helper.c | 7 ---

[Qemu-devel] [PATCH v2 27/45] exec-all: extract tb->tc_* into a separate struct tc_tb

In preparation for adding tc.size to be able to keep track of TB's using the binary search tree implementation from glib. Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 20 ++-- accel/tcg/cpu-exec.c | 6 +++--- accel/tcg/translate-all.c | 20

[Qemu-devel] [PATCH v2 42/45] tcg: define TCG_HIGHWATER

Will come in handy very soon. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota --- tcg/tcg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index

[Qemu-devel] [PATCH v2 41/45] translate-all: use qemu_protect_rwx/none helpers

Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 49 ++- 1 file changed, 6 insertions(+), 43 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index fd3e4a0..913b1c5 100644 ---

[Qemu-devel] [PATCH v2 16/45] target/hppa: check CF_PARALLEL instead of parallel_cpus

Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota --- target/hppa/helper.h| 2 ++ target/hppa/op_helper.c | 32 target/hppa/translate.c | 12 ++-- 3 files changed, 40

[Qemu-devel] [PATCHv3 0/2] pci: allow PCI bus slots to be marked as reserved

For some machines it is impossible to plug devices into a particular PCI bus slot, e.g. for a real Ultra 5 there are 2 PCI bridges attached to the root bus behind which all devices must be plugged. Ignoring this rule will cause problems with interrupt routing since the interrupt numbers are

[Qemu-devel] [PATCH v2 39/45] osdep: move qemu_real_host_page_size/mask to osdep

These only depend on the host and therefore belong in the common osdep, not in a target-dependent object. Signed-off-by: Emilio G. Cota --- include/exec/cpu-all.h | 2 -- include/qemu/osdep.h | 8 exec.c | 5 + util/osdep.c | 9 +

[Qemu-devel] [PATCH v2 17/45] target/i386: check CF_PARALLEL instead of parallel_cpus

Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota --- target/i386/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index

[Qemu-devel] [PATCH v2 12/45] tcg: remove addr argument from lookup_tb_ptr

It is unlikely that we will ever want to call this helper passing an argument other than the current PC. So just remove the argument, and use the pc we already get from cpu_get_tb_cpu_state. This change paves the way to having a common "tb_lookup" function. Signed-off-by: Emilio G. Cota

[Qemu-devel] [PATCH v2 18/45] target/m68k: check CF_PARALLEL instead of parallel_cpus

Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota --- target/m68k/helper.h| 2 ++ target/m68k/op_helper.c | 32 target/m68k/translate.c | 12 ++-- 3 files changed, 40

[Qemu-devel] [PATCH v2 24/45] exec-all: introduce TB_PAGE_ADDR_FMT

And fix the following warning when DEBUG_TB_INVALIDATE is enabled in translate-all.c: CC mipsn32-linux-user/accel/tcg/translate-all.o /data/src/qemu/accel/tcg/translate-all.c: In function ‘tb_alloc_page’: /data/src/qemu/accel/tcg/translate-all.c:1201:16: error: format ‘%lx’ expects

[Qemu-devel] [PATCH v2 19/45] target/s390x: check CF_PARALLEL instead of parallel_cpus

Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota --- target/s390x/helper.h | 3 +++ target/s390x/mem_helper.c | 50 +++ target/s390x/translate.c | 20

[Qemu-devel] [PATCH v2 32/45] tcg: take tb_ctx out of TCGContext

Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota --- include/exec/tb-context.h | 2 ++ tcg/tcg.h | 2 -- accel/tcg/cpu-exec.c

[Qemu-devel] [PATCH v2 35/45] gen-icount: fold exitreq_label into TCGContext

Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota --- include/exec/gen-icount.h | 7 +++ tcg/tcg.h | 2 ++ 2 files changed, 5

[Qemu-devel] [PATCH v2 30/45] translate-all: report correct avg host TB size

Since commit 6e3b2bfd6 ("tcg: allocate TB structs before the corresponding translated code") we are not fully utilizing code_gen_buffer for translated code, and therefore are incorrectly reporting the amount of translated code as well as the average host TB size. Address this by: - Making the

[Qemu-devel] [PATCH v2 25/45] translate-all: define and use DEBUG_TB_INVALIDATE_GATE

This gets rid of an ifdef check while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Bennée Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 12 +--- 1 file changed, 9 insertions(+), 3

[Qemu-devel] [PATCH v2 33/45] tcg: take .helpers out of TCGContext

Groundwork for supporting multiple TCG contexts. The hash table becomes read-only after it is filled in, so we can save space by keeping just a global pointer to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota

[Qemu-devel] [PATCH v2 29/45] exec-all: rename tb_free to tb_remove

We don't really free anything in this function anymore; we just remove the TB from the binary search tree. Suggested-by: Alex Bennée Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 2 +- accel/tcg/cpu-exec.c | 2 +-

[Qemu-devel] [PATCH v2 14/45] tcg: define CF_PARALLEL and use it for TB hashing

This will enable us to decouple code translation from the value of parallel_cpus at any given time. It will also help us minimize TB flushes when generating code via EXCP_ATOMIC. Note that the declaration of parallel_cpus is brought to exec-all.h to be able to define there the inlines. The

[Qemu-devel] [PATCH v2 09/45] tcg/mips: constify tcg_target_callee_save_regs

Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Emilio G. Cota --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH v2 26/45] translate-all: define and use DEBUG_TB_CHECK_GATE

This prevents bit rot by ensuring the debug code is compiled when building a user-mode target. Unfortunately the helpers are user-mode-only so we cannot fully get rid of the ifdef checks. Add a comment to explain this. Suggested-by: Alex Bennée Signed-off-by: Emilio G.

[Qemu-devel] [PATCH v2 05/45] exec-all: fix typos in TranslationBlock's documentation

Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 887d7b3..28e3a24 100644 ---

[Qemu-devel] [PATCH v2 21/45] tcg: check CF_PARALLEL instead of parallel_cpus

Thereby decoupling the resulting translated code from the current state of the system. The tb->cflags field is not passed to tcg generation functions. So we add a bit to TCGContext, storing there whether CF_PARALLEL is set before translating every TB. Most architectures have <= 32 registers,

[Qemu-devel] [PATCH v2 11/45] exec-all: bring tb->invalid into tb->cflags

This gets rid of a hole in struct TranslationBlock. Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 3 +-- accel/tcg/cpu-exec.c | 2 +- accel/tcg/translate-all.c | 3 +-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/include/exec/exec-all.h

[Qemu-devel] [PATCH v2 22/45] cpu-exec: lookup/generate TB outside exclusive region during step_atomic

Now that all code generation has been converted to check CF_PARALLEL, we can generate !CF_PARALLEL code without having yet set !parallel_cpus -- and therefore without having to be in the exclusive region during cpu_exec_step_atomic. While at it, merge cpu_exec_step into cpu_exec_step_atomic.

[Qemu-devel] [PATCH v2 08/45] tcg/i386: constify tcg_target_callee_save_regs

Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH v2 10/45] translate-all: guarantee that tb_hash only holds valid TBs

This gets rid of the need to check the tb->invalid bit during lookups. After this change we do not need atomics to operate on tb->invalid: setting and checking its value is serialised with tb_lock. Signed-off-by: Emilio G. Cota --- accel/tcg/cpu-exec.c | 3 +--

[Qemu-devel] [PATCH v2 31/45] tci: move tci_regs to tcg_qemu_tb_exec's stack

Groundwork for supporting multiple TCG contexts. Compile-tested for all targets on an x86_64 host. Suggested-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tci.c | 552 +++--- 1 file

[Qemu-devel] [PATCH v2 04/45] tcg: fix corruption of code_time profiling counter upon tb_flush

Whenever there is an overflow in code_gen_buffer (e.g. we run out of space in it and have to flush it), the code_time profiling counter ends up with an invalid value (that is, code_time -= profile_getclock(), without later on getting += profile_getclock() due to the goto). Fix it by using the ti

[Qemu-devel] [PATCH v2 20/45] target/sparc: check CF_PARALLEL instead of parallel_cpus

Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index

[Qemu-devel] [PATCH v2 06/45] translate-all: make have_tb_lock static

It is only used by this object, and it's not exported to any other. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1

[Qemu-devel] [PATCH v2 02/45] translate-all: remove redundant !tcg_enabled check in dump_exec_info

This check is redundant because it is already performed by the only caller of dump_exec_info -- the caller was updated by b7da97eef ("monitor: Check whether TCG is enabled before running the "info jit" code"). Checking twice wouldn't necessarily be too bad, but here the check also returns with

[Qemu-devel] [PATCH v2 13/45] tcg: consolidate TB lookups in tb_lookup__cpu_state

This avoids duplicating code. cpu_exec_step will also use the new common function once we integrate parallel_cpus into tb->cflags. Performance-wise, I measured a small improvement when booting debian-arm. Note that inlining pays off: Performance counter stats for 'taskset -c 0 qemu-system-arm \

[Qemu-devel] [PATCH v2 03/45] cputlb: bring back tlb_flush_count under !TLB_DEBUG

Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried the increment of tlb_flush_count under TLB_DEBUG. This results in "info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG. Besides, under MTTCG tlb_flush_count is updated by several threads, so in order not to lose counts

[Qemu-devel] [PATCH v2 23/45] translate-all: define and use DEBUG_TB_FLUSH_GATE

This gets rid of some ifdef checks while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Bennée Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 20 +--- 1 file changed, 13 insertions(+),

[Qemu-devel] [PATCH v2 07/45] cpu-exec: rename have_tb_lock to acquired_tb_lock in tb_find

Reusing the have_tb_lock name, which is also defined in translate-all.c, makes code reviewing unnecessarily harder. Avoid potential confusion by renaming the local have_tb_lock variable to something else. Signed-off-by: Emilio G. Cota --- accel/tcg/cpu-exec.c | 10 +- 1

[Qemu-devel] [PATCH v2 37/45] tcg: introduce **tcg_ctxs to keep track of all TCGContext's

Groundwork for supporting multiple TCG contexts. Note that having n_tcg_ctxs is unnecessary. However, it is convenient to have it, since it will simplify iterating over the array: we'll have just a for loop instead of having to iterate over a NULL-terminated array (which would require n+1 elems)

[Qemu-devel] [PATCH v2 00/45] tcg: support for multiple TCG contexts

v1: https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg02059.html Thanks all for your comments on v1. This v2 patchset applies on top of stefanha's tracing tree (9212a18e371): https://github.com/stefanha/qemu/tree/tracing That tree has some changes (per-vcpu TCG tracing) that would

[Qemu-devel] [PATCH v2 01/45] vl: fix breakage of -tb-size

Commit e7b161d573 ("vl: add tcg_enabled() for tcg related code") adds a check to exit the program when !tcg_enabled() while parsing the -tb-size flag. It turns out that when the -tb-size flag is evaluated, tcg_enabled() can only return 0, since it is set (or not) much later by

Re: [Qemu-devel] [PATCH v2 17/29] virtio-serial: use DIV_ROUND_UP

On (Thu) 13 Jul 2017 [18:32:07], Marc-André Lureau wrote: > I used the clang-tidy qemu-round check to generate the fix: > https://github.com/elmarco/clang-tools-extra > > Signed-off-by: Marc-André Lureau Reviewed-by: Amit Shah Amit

Re: [Qemu-devel] [PATCH v2 06/27] target/sh4: Handle user-space atomics

On 07/16/2017 05:18 AM, Aurelien Jarno wrote: That said for further improvements did you consider decoding the gUSA section in a helper. It might avoid having to emulate the atomic sequence with 3 TBs in the worst case (the original one, the one to decode the sequence and the one holding the

Re: [Qemu-devel] [PATCHv2 0/2] pci: allow PCI bus slots to be marked as reserved

On 16/07/17 08:28, Marcel Apfelbaum wrote: >>> As in prev version, other than the minor comment >>> on replacing "if (...) return true; else return false" >>> with the actual value, I am OK with it. >> >> Okay great! So change pci_bus_devfn_available() to something like this? >> >> static bool

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