Re: [Qemu-devel] [PATCH 3/3] Unified Datagram Socket Transport - raw support

On 2017年07月19日 01:08, anton.iva...@cambridgegreys.com wrote: From: Anton Ivanov This adds raw socket support to the unified socket driver. Interesting, in fact, I've finished a tpacket backend. Let me post it sometime after hardfreeze. Signed-off-by:

Re: [Qemu-devel] [PATCH 2/3] Unified Datagram Socket Transport - GRE support

OK. Will address both comments in next version. Brgds, A. On 19/07/17 06:48, Jason Wang wrote: On 2017年07月19日 01:08, anton.iva...@cambridgegreys.com wrote: From: Anton Ivanov This adds GRETAP support to the unified socket driver. Signed-off-by: Anton

Re: [Qemu-devel] [PATCH 1/3] Unified Datagram Socket Transport

On 19/07/17 06:39, Jason Wang wrote: On 2017年07月19日 01:08, anton.iva...@cambridgegreys.com wrote: From: Anton Ivanov 1. Creates a common backend for socket transports using recvmmsg(). 2. Migrates L2TPv3 to the new backend It would be better if you could

Re: [Qemu-devel] [PATCH 2/3] Unified Datagram Socket Transport - GRE support

On 2017年07月19日 01:08, anton.iva...@cambridgegreys.com wrote: From: Anton Ivanov This adds GRETAP support to the unified socket driver. Signed-off-by: Anton Ivanov --- net/Makefile.objs | 2 +- net/clients.h | 4 +

Re: [Qemu-devel] [PATCH 1/3] Unified Datagram Socket Transport

On 2017年07月19日 01:08, anton.iva...@cambridgegreys.com wrote: From: Anton Ivanov 1. Creates a common backend for socket transports using recvmmsg(). 2. Migrates L2TPv3 to the new backend It would be better if you could further split out 2 from this patch.

[Qemu-devel] [PULL 10/14] target/sparc: optimize various functions using extract op

From: Philippe Mathieu-Daudé Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 14/14] tcg: Pass generic CPUState to gen_intermediate_code()

From: Lluís Vilanova Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Reviewed-by: Emilio

[Qemu-devel] [PULL 13/14] tcg/tci: enable bswap16_i64

From: Philippe Mathieu-Daudé Altough correctly implemented, bswap16_i64() never got tested/executed so the safety TODO() statement was never removed. Since it got now tested the TODO() can be removed. while running Alex Bennée's image aarch64-linux-3.15rc2-buildroot.img:

[Qemu-devel] [PULL 08/14] target/m68k: optimize bcd_flags() using extract op

From: Philippe Mathieu-Daudé Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id:

[Qemu-devel] [PULL 11/14] target/sparc: optimize gen_op_mulscc() using deposit op

From: Philippe Mathieu-Daudé Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20170718045540.16322-9-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/sparc/translate.c | 5

[Qemu-devel] [PULL 07/14] target/arm: optimize aarch32 rev16

From: Aurelien Jarno Use the same mask to avoid having to load two different constants, as suggested by Richard Henderson. Signed-off-by: Aurelien Jarno Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson

[Qemu-devel] [PULL 03/14] tcg: Expand glue macros before stringifying helper names

Signed-off-by: Richard Henderson --- include/exec/helper-tcg.h | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index bb92877..b0c5baf 100644 --- a/include/exec/helper-tcg.h +++

[Qemu-devel] [PULL 01/14] tcg/mips: reserve a register for the guest_base.

From: Jiang Biao Reserve a register for the guest_base using ppc code for reference. By doing so, we do not have to recompute it for every memory load. Signed-off-by: Jiang Biao Signed-off-by: Richard Henderson Message-Id:

[Qemu-devel] [PULL 12/14] target/alpha: optimize gen_cvtlq() using deposit op

From: Philippe Mathieu-Daudé Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20170718045540.16322-10-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/alpha/translate.c | 8

[Qemu-devel] [PULL 05/14] coccinelle: add a script to optimize tcg op using tcg_gen_extract()

From: Philippe Mathieu-Daudé The following thread was helpful while writing this script: https://github.com/coccinelle/coccinelle/issues/86 Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20170718045540.16322-3-f4...@amsat.org> Signed-off-by: Richard

[Qemu-devel] [PULL 06/14] target/arm: Optimize aarch64 rev16

It is much shorter to reverse all 4 half-words in parallel than extract, reverse, and deposit each in turn. Suggested-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 24 ++-- 1 file changed, 6

[Qemu-devel] [PULL 09/14] target/ppc: optimize various functions using extract op

From: Philippe Mathieu-Daudé Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: David Gibson

[Qemu-devel] [PULL 00/14] tcg-next patch queue

carrying it around further. r~ The following changes since commit 6887dc6700ccb7820d8a9d370f421ee361c748e8: Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20170718' into staging (2017-07-18 21:13:48 +0100) are available in the git repository at: git://github.com/rth7680

[Qemu-devel] [PULL 04/14] coccinelle: ignore ASTs pre-parsed cached C files

From: Philippe Mathieu-Daudé files generated using coccinelle tool: 'spatch --use-cache' Reviewed-by: Eric Blake Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20170718045540.16322-2-f4...@amsat.org> Signed-off-by: Richard Henderson

[Qemu-devel] [PULL 02/14] util/cacheinfo: Add missing include for ppc linux

From: Philippe Mathieu-Daudé This include was forgotten when splitting cacheinfo.c out of tcg/ppc/tcg-target.inc.c (see commit b255b2c8). For a Centos7 host, the include path implicitly pulls in the desired AT_*

Re: [Qemu-devel] [PATCH v2] hmp: allow cpu index for "info lapic"

Hi Eduardo, Thank you for your reply! >On Mon, Jul 17, 2017 at 09:49:37PM -0400, Yi Wang wrote: >> Add [vcpu] index support for hmp command "info lapic", which is >> useful when debugging ipi and so on. Current behavior is not >> changed when the parameter isn't specified. >> >>

[Qemu-devel] [PULL 8/8] target/alpha: Log temp leaks

Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index aaaf28f..90e6d52 100644 --- a/target/alpha/translate.c

[Qemu-devel] [PULL 7/8] target/alpha: Fix temp leak in gen_fbcond

Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 326af7f..aaaf28f 100644 ---

[Qemu-devel] [PULL 5/8] target/alpha: Fix temp leak in gen_mtpr

Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index d684a7b..5e37b1a 100644 ---

[Qemu-devel] [PULL 3/8] target/alpha: Merge several flag bytes into ENV->FLAGS

The flags are arranged such that we can manipulate them either a whole, or as individual bytes. The computation within cpu_get_tb_cpu_state is now reduced to a single load and mask. Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 2/8] target/alpha: Copy tb->flags into DisasContext

Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 4a627fc..48be19a 100644 ---

[Qemu-devel] [PULL 6/8] target/alpha: Fix temp leak in gen_call_pal

Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 5e37b1a..326af7f 100644

[Qemu-devel] [PULL 0/8] target/alpha cleanups

6887dc6700ccb7820d8a9d370f421ee361c748e8: Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20170718' into staging (2017-07-18 21:13:48 +0100) are available in the git repository at: git://github.com/rth7680/qemu.git tags/pull-axp-20170718 for you to fetch changes up to 8aa5c65fd3d4612d8ab690bef0980d26f30f381d

[Qemu-devel] [PULL 4/8] target/alpha: Fix temp leak in gen_bcond

Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/translate.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 140d6f3..d684a7b 100644 ---

[Qemu-devel] [PULL 1/8] target/alpha: Remove amask from tb->flags

This value is constant for the cpu and does not need to be stored within the TB. Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 9 --- target/alpha/translate.c | 70

[Qemu-devel] [PATCH for-2.10] util: Introduce include/qemu/cpuid.h

Clang 3.9 passes the CONFIG_AVX2_OPT configure test. However, the supplied does not contain the bit_AVX2 define that we use when detecting whether the routine can be enabled. Introduce a qemu-specific header that uses the compiler's definition of __cpuid et al, but supplies any missing bit_*

Re: [Qemu-devel] [PATCH] spapr: make default PHB optionnal

On Tue, Jul 04, 2017 at 10:47:22AM +0200, Greg Kurz wrote: > On Tue, 4 Jul 2017 17:29:01 +1000 > David Gibson wrote: > > > On Mon, Jul 03, 2017 at 06:48:25PM +0200, Greg Kurz wrote: > > > The sPAPR machine always create a default PHB during initialization, even > > >

[Qemu-devel] [Bug 757702] Re: ARM: singlestepping insn which UNDEFs should stop at UNDEF vector insn, not after it

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/757702 Title: ARM:

Re: [Qemu-devel] [PATCH] spapr: make default PHB optionnal

On Wed, Jul 12, 2017 at 05:09:37PM +0530, Shivaprasad G Bhat wrote: > > > On 07/12/2017 04:25 PM, Andrea Bolognani wrote: > > [libvir-list added to the loop] > > > > On Tue, 2017-07-04 at 10:47 +0200, Greg Kurz wrote: > > > On Tue, 4 Jul 2017 17:29:01 +1000 David Gibson > > >

[Qemu-devel] [Bug 796202] Re: Doing a 64 bit load from a 32 bit local APIC register is allowed

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/796202 Title: Doing a 64

[Qemu-devel] [Bug 959992] Re: segfault in apic_report_irq_delivered when booting tinycore_3.3.iso

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/959992 Title: segfault in

[Qemu-devel] [Bug 1234179] Re: QEMU segfaults during Windows 7 unattended install

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1234179 Title: QEMU

[Qemu-devel] [Bug 1198350] Re: USB pass-through fails with USBDEVFS_DISCONNECT: Invalid argument

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1198350 Title: USB

[Qemu-devel] [Bug 726619] Re: loadvm does not load (offline) snapshot anymore

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/726619 Title: loadvm does

[Qemu-devel] [Bug 924943] Re: usb-host devices given by command line are routed incomplete to the guest

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/924943 Title: usb-host

[Qemu-devel] [Bug 1034423] Re: Guests running OpenIndiana (and relatives) fail to boot on AMD hardware

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1034423 Title: Guests

[Qemu-devel] [Bug 752476] Re: monitor command mouse_button 1 moves mouse

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/752476 Title: monitor

Re: [Qemu-devel] [PATCH v3] spapr: disable decrementer during reset

On Wed, Jul 19, 2017 at 09:20:52AM +0530, Nikunj A Dadhania wrote: > David Gibson writes: > > > On Tue, Jul 18, 2017 at 10:53:01AM +0530, Nikunj A Dadhania wrote: > >> David Gibson writes: > >> > >> > On Mon, Jul 17, 2017 at 09:46:39AM

Re: [Qemu-devel] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model

On Wed, Jul 19, 2017 at 02:18:17PM +1000, Benjamin Herrenschmidt wrote: > On Wed, 2017-07-19 at 14:01 +1000, David Gibson wrote: > > On Wed, Jul 19, 2017 at 01:56:57PM +1000, Benjamin Herrenschmidt wrote: > > > On Wed, 2017-07-19 at 13:08 +1000, David Gibson wrote: > > > > On Wed, Jul 05, 2017 at

Re: [Qemu-devel] [PATCH v2] hmp: allow cpu index for "info lapic"

>On Mon, 17 Jul 2017 21:49:37 -0400 >Yi Wang wrote: > >> Add [vcpu] index support for hmp command "info lapic", which is >> useful when debugging ipi and so on. Current behavior is not >> changed when the parameter isn't specified. >we shouldn't expose cpu_index to users

Re: [Qemu-devel] [PATCH v2 00/45] tcg: support for multiple TCGcontexts

On 07/18/2017 04:17 PM, jiang.bi...@zte.com.cn wrote: Does that mean both the MTTCG feature and this patch set are all about system mode, and have nothing to do with linux-user mode? Yes. > MTTCG has only been enabled on a few targets: alpha, arm, ppc64. > Look for "mttcg=yes" in

Re: [Qemu-devel] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model

On Wed, 2017-07-19 at 14:01 +1000, David Gibson wrote: > On Wed, Jul 19, 2017 at 01:56:57PM +1000, Benjamin Herrenschmidt wrote: > > On Wed, 2017-07-19 at 13:08 +1000, David Gibson wrote: > > > On Wed, Jul 05, 2017 at 07:13:17PM +0200, Cédric Le Goater wrote: > > > > Let's provide an empty shell

Re: [Qemu-devel] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model

On Wed, 2017-07-19 at 13:08 +1000, David Gibson wrote: > > I'm somewhat uncomfortable with an irq allocater here in the intc > code. As a rule, irq allocation is the responsibility of the machine, > not any sub-component. Furthermore, it should allocate in a way which > is repeatable, since

Re: [Qemu-devel] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model

On Wed, Jul 19, 2017 at 01:56:57PM +1000, Benjamin Herrenschmidt wrote: > On Wed, 2017-07-19 at 13:08 +1000, David Gibson wrote: > > On Wed, Jul 05, 2017 at 07:13:17PM +0200, Cédric Le Goater wrote: > > > Let's provide an empty shell for the XIVE controller model with a > > > couple of attributes

Re: [Qemu-devel] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model

On Wed, 2017-07-19 at 13:08 +1000, David Gibson wrote: > On Wed, Jul 05, 2017 at 07:13:17PM +0200, Cédric Le Goater wrote: > > Let's provide an empty shell for the XIVE controller model with a > > couple of attributes for the IRQ number allocator. The latter is > > largely inspired by OPAL which

Re: [Qemu-devel] [RFC PATCH 00/26] guest exploitation of the XIVE interrupt controller (POWER9)

On Wed, 2017-07-19 at 13:00 +1000, David Gibson wrote: > So, this is probably obvious, but I'm not considering this a candidate > for qemu 2.10 (seeing as the soft freeze was yesterday). I'll still > try to review and, once ready, queue for 2.11. Right. I need to review still and we need to make

Re: [Qemu-devel] [PATCH v3] spapr: disable decrementer during reset

David Gibson writes: > On Tue, Jul 18, 2017 at 10:53:01AM +0530, Nikunj A Dadhania wrote: >> David Gibson writes: >> >> > On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote: >> >> Rebooting a SMP TCG guest is broken for

Re: [Qemu-devel] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model

On Wed, Jul 05, 2017 at 07:13:17PM +0200, Cédric Le Goater wrote: > Let's provide an empty shell for the XIVE controller model with a > couple of attributes for the IRQ number allocator. The latter is > largely inspired by OPAL which allocates IPI IRQ numbers from the > bottom of the IRQ number

Re: [Qemu-devel] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model

On Wed, Jul 19, 2017 at 01:08:49PM +1000, David Gibson wrote: > On Wed, Jul 05, 2017 at 07:13:17PM +0200, Cédric Le Goater wrote: > > Let's provide an empty shell for the XIVE controller model with a > > couple of attributes for the IRQ number allocator. The latter is > > largely inspired by OPAL

Re: [Qemu-devel] [RFC PATCH 00/26] guest exploitation of the XIVE interrupt controller (POWER9)

On Wed, Jul 05, 2017 at 07:13:13PM +0200, Cédric Le Goater wrote: > On a POWER9 sPAPR machine, the Client Architecture Support (CAS) > negotiation process determines whether the guest operates with an > interrupt controller using the XICS legacy model, as found on POWER8, > or in XIVE exploitation

Re: [Qemu-devel] [RFC PATCH 05/26] ppc/xive: define XIVE internal tables

On Wed, Jul 05, 2017 at 07:13:18PM +0200, Cédric Le Goater wrote: > The XIVE interrupt controller of the POWER9 uses a set of tables to > redirect exception from event sources to CPU threads. Among which we > choose to model : > > - the State Bit Entries (SBE), also known as Event State Buffer >

Re: [Qemu-devel] [PATCH RFC v2 7/9] s390x/pci: fence off instructions for non-pci

在 2017/7/18 下午10:24, Cornelia Huck 写道: If a guest running on a machine without zpci issues a pci instruction, throw them an exception. Signed-off-by: Cornelia Huck --- target/s390x/kvm.c | 54 +- 1 file changed, 41

Re: [Qemu-devel] [PATCH RFC v2 8/9] s390x/kvm: msi route fixup for non-pci

在 2017/7/18 下午11:22, Cornelia Huck 写道: On Tue, 18 Jul 2017 11:58:08 -0300 Philippe Mathieu-Daudé wrote: Hi Cornelia, On Tue, Jul 18, 2017 at 11:24 AM, Cornelia Huck wrote: If we don't provide pci, we cannot have a pci device for which we have to

Re: [Qemu-devel] [PATCH RFC v2 8/9] s390x/kvm: msi route fixup for non-pci

I think moving the new code on the top of this function would make it more readable. 在 2017/7/18 下午10:24, Cornelia Huck 写道: +} else { +DPRINTF("fixup_msi_route on non-pci machine?!\n"); +return -ENODEV; +}

Re: [Qemu-devel] Question for iotests 188, 189 and 087

Hi Eric, On 2017/7/18 下午10:57, Eric Blake wrote: On 07/17/2017 10:01 PM, Jing Liu wrote: Hi all, Do you anybody have iotests failure: 188, 189 and 087 of the latest qemu upsteam? I just wondered if it has something wrong with my test machines because I have different results with two

Re: [Qemu-devel] [PATCH v2 00/45] tcg: support for multiple TCGcontexts

> On 07/18/2017 02:22 PM, jiang.bi...@zte.com.cn wrote: > > Seeing your work on multiple TCG, it seems that it has some kind of > > connection > > with the MTTCG feature, > > > > but I do not figure out how they are connected in detail. > > > > Could you pls help to confirm the following

[Qemu-devel] host side todo list for virtio rdma

Here are some thoughts on bits that are still missing to get a working virtio-rdma, with some suggestions. These are very preliminary but I feel I kept these in my head (and discussed offline) for too long. All of the below is just my personal humble opinion. Feature Requirements: The basic

[Qemu-devel] [Bug 1703506] Re: SMT not supported by QEMU on AMD Ryzen CPU

>Please confirm what's the QEMU command-line being used (especially the -smp and -cpu options), and check if the bug persists if using "-cpu host". I'm using -cpu host already, here's just the cpu and smp commands: -cpu

Re: [Qemu-devel] [PATCH v2 00/45] tcg: support for multiple TCG contexts

On 07/18/2017 02:22 PM, jiang.bi...@zte.com.cn wrote: Seeing your work on multiple TCG, it seems that it has some kind of connection with the MTTCG feature, but I do not figure out how they are connected in detail. Could you pls help to confirm the following questions: 1. what is the

Re: [Qemu-devel] [PATCH] Update references of "struct ucontext" to "ucontext_t"

Yes, it is a dup. Sorry for the noise. On Tue, Jul 18, 2017 at 9:03 PM, Eric Blake wrote: > On 07/18/2017 07:58 PM, Nathaniel McCallum wrote: >> Glibc used to have: >> >>typedef struct ucontext { ... } ucontext_t; >> >> Glibc now has: >> >>typedef struct ucontext_t {

Re: [Qemu-devel] [PATCH] replace struct ucontext with ucontext_t type

On 06/29/2017 09:09 AM, Laurent Vivier wrote: > ... >> diff --git a/linux-user/signal.c b/linux-user/signal.c >> index 3d18d1b3ee..2c55a4f600 100644 >> --- a/linux-user/signal.c >> +++ b/linux-user/signal.c >> @@ -3346,7 +3346,7 @@ static void setup_rt_frame(int sig, struct >> target_sigaction

Re: [Qemu-devel] [PATCH] replace struct ucontext with ucontext_t type

On 06/29/2017 08:18 AM, Daniel P. Berrange wrote: > On Thu, Jun 29, 2017 at 10:05:13AM +0100, Peter Maydell wrote: >> On 28 June 2017 at 21:44, Khem Raj wrote: >>> The ucontext_t type had a tag struct ucontext until now >>> but newer glibc will drop it so we need to adjust and

Re: [Qemu-devel] [PATCH] Update references of "struct ucontext" to "ucontext_t"

On 07/18/2017 07:58 PM, Nathaniel McCallum wrote: > Glibc used to have: > >typedef struct ucontext { ... } ucontext_t; > > Glibc now has: > >typedef struct ucontext_t { ... } ucontext_t; > > However, Qemu used "struct ucontext" in declarations. This is a > private name and compatiblity

[Qemu-devel] [PATCH] Update references of "struct ucontext" to "ucontext_t"

Glibc used to have: typedef struct ucontext { ... } ucontext_t; Glibc now has: typedef struct ucontext_t { ... } ucontext_t; However, Qemu used "struct ucontext" in declarations. This is a private name and compatiblity cannot be guaranteed. This patch updates Qemu to only use the

Re: [Qemu-devel] Hacks for building on gcc 7 / Fedora 26

On 07/18/2017 06:59 PM, Richard Henderson wrote: >> +++ w/hw/usb/bus.c >> @@ -407,8 +407,9 @@ void usb_register_companion(const char *masterbus, >> USBPort *ports[], >> void usb_port_location(USBPort *downstream, USBPort *upstream, int >> portnr) >> { >> if (upstream) { >> -

Re: [Qemu-devel] [PATCH 1/2] vfio/ccw: allocate irq info with the right size

* Cornelia Huck [2017-07-18 11:07:49 +0200]: > On Tue, 18 Jul 2017 16:49:43 +0800 > Dong Jia Shi wrote: > > > * Cornelia Huck [2017-07-18 10:32:13 +0200]: > > > > > On Tue, 18 Jul 2017 03:49:25 +0200 > > > Dong Jia Shi

Re: [Qemu-devel] [PATCH v2 00/45] tcg: support for multiple TCG contexts

Hi, Seeing your work on multiple TCG, it seems that it has some kind of connection with the MTTCG feature, but I do not figure out how they are connected in detail. Could you pls help to confirm the following questions: what is the relationship between your patches and the MTTCG feature

Re: [Qemu-devel] [PATCH 02/29] pci: remove superfluous parenthesis

On 07/17/2017 08:09 PM, Philippe Mathieu-Daudé wrote: #define IOTEST_TEST(i) (iotest_test[((i) % ARRAY_SIZE(iotest_test))]) #define IOTEST_TYPE(i) (iotest_type[((i) / ARRAY_SIZE(iotest_test))]) Looks like array[(x)] is another candidate. -#define IOTEST_MAX_TEST

Re: [Qemu-devel] [PATCH 4/4] target/i386: Don't use x86_cpu_load_def() on "max" CPU model

On Tue, Jul 18, 2017 at 03:27:26PM +0200, Igor Mammedov wrote: > On Wed, 12 Jul 2017 13:20:58 -0300 > Eduardo Habkost wrote: > > > When commit 0bacd8b3046f ('i386: Don't set CPUClass::cpu_def on > > "max" model') removed the CPUClass::cpu_def field, we kept using > > the

Re: [Qemu-devel] Hacks for building on gcc 7 / Fedora 26

On 07/17/2017 03:48 AM, Eric Blake wrote: On 07/17/2017 08:42 AM, Eric Blake wrote: On 07/13/2017 08:07 AM, Philippe Mathieu-Daudé wrote: On 04/07/2017 04:21 PM, Philippe Mathieu-Daudé wrote: Hi Dave, On 04/07/2017 11:38 AM, Dr. David Alan Gilbert wrote: Hi, Fedora 26 has gcc 7.0.1

Re: [Qemu-devel] [PATCH v2 10/45] translate-all: guarantee that tb_hash only holds valid TBs

On 07/18/2017 01:30 PM, Emilio G. Cota wrote: Should I do those updates in the same patch where tb->invalid is brought over to cflags? Alternatives: have a later patch where all readers are converted to atomic_read, or keep tb->invalid as a separate field (we could use that 4-byte hole in struct

Re: [Qemu-devel] [PATCH v2 10/45] translate-all: guarantee that tb_hash only holds valid TBs

On Mon, Jul 17, 2017 at 19:29:57 -1000, Richard Henderson wrote: > On 07/17/2017 06:54 PM, Emilio G. Cota wrote: > >What threw me off was that in lookup_tb_ptr we're not checking tb->invalid, > >and that biased me into thinking that it's not needed. But I should have > >tried harder. Also, that's

Re: [Qemu-devel] [PATCH v2] hmp: allow cpu index for "info lapic"

On Tue, Jul 18, 2017 at 04:54:17PM +0200, Igor Mammedov wrote: > On Mon, 17 Jul 2017 21:49:37 -0400 > Yi Wang wrote: > > > Add [vcpu] index support for hmp command "info lapic", which is > > useful when debugging ipi and so on. Current behavior is not > > changed when the

Re: [Qemu-devel] [PATCH v2] hmp: allow cpu index for "info lapic"

On Mon, Jul 17, 2017 at 09:49:37PM -0400, Yi Wang wrote: > Add [vcpu] index support for hmp command "info lapic", which is > useful when debugging ipi and so on. Current behavior is not > changed when the parameter isn't specified. > > Signed-off-by: Yi Wang >

Re: [Qemu-devel] [PULL 00/31] target/sh4 queue

On 2017-07-18 15:40, no-re...@patchew.org wrote: > Hi, > > This series failed automatic build test. Please find the testing commands and > their output below. If you have docker installed, you can probably reproduce > it > locally. > > Subject: [Qemu-devel] [PULL 00/31] target/sh4 queue >

Re: [Qemu-devel] [PULL 00/31] target/sh4 queue

On 2017-07-18 15:42, no-re...@patchew.org wrote: > Hi, > > This series seems to have some coding style problems. See output below for > more information: > > Subject: [Qemu-devel] [PULL 00/31] target/sh4 queue > Message-id: 20170718215050.3812-1-aurel...@aurel32.net > Type: series > > === TEST

[Qemu-devel] windows qemu can't be debuged

Hello, all: I have compiled qemu in cygwin with mingw according to the qemu wiki. When I debug it with GDB, I get the error below: . Type "apropos word" to search for commands related to "word"... Reading symbols from qemu-system-x86_64.exe...done. (gdb) r -cdrom /t.iso -boot d -display

Re: [Qemu-devel] [PULL 00/31] target/sh4 queue

Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PULL 00/31] target/sh4 queue Message-id: 20170718215050.3812-1-aurel...@aurel32.net Type: series === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log --oneline

Re: [Qemu-devel] [PULL 00/31] target/sh4 queue

Hi, This series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally. Subject: [Qemu-devel] [PULL 00/31] target/sh4 queue Message-id: 20170718215050.3812-1-aurel...@aurel32.net Type: series ===

[Qemu-devel] [PULL for-2.10 7/7] xen: don't use xenstore to save/restore physmap anymore

From: Igor Druzhinin If we have a system with xenforeignmemory_map2() implemented we don't need to save/restore physmap on suspend/restore anymore. In case we resume a VM without physmap - try to recreate the physmap during memory region restore phase and remap map

[Qemu-devel] [PULL for-2.10 6/7] xen/mapcache: introduce xen_replace_cache_entry()

From: Igor Druzhinin This new call is trying to update a requested map cache entry according to the changes in the physmap. The call is searching for the entry, unmaps it and maps again at the same place using a new guest address. If the mapping is dummy this call will

[Qemu-devel] [PULL for-2.10 3/7] xen-platform: separate unplugging of NVMe disks

Commit 090fa1c8 "add support for unplugging NVMe disks..." extended the existing disk unplug flag to cover NVMe disks as well as IDE and SCSI. The recent thread on the xen-devel mailing list [1] has highlighted that this is not desirable behaviour: PV frontends should be able to distinguish NVMe

[Qemu-devel] [PULL for-2.10 5/7] xen/mapcache: add an ability to create dummy mappings

From: Igor Druzhinin Dummys are simple anonymous mappings that are placed instead of regular foreign mappings in certain situations when we need to postpone the actual mapping but still have to give a memory region to QEMU to play with. This is planned to be used for

[Qemu-devel] [PULL for-2.10 2/7] xen_pt_msi.c: Check for xen_host_pci_get_* failures in xen_pt_msix_init()

From: Peter Maydell Check the return status of the xen_host_pci_get_* functions we call in xen_pt_msix_init(), and fail device init if the reads failed rather than ploughing ahead. (Spotted by Coverity: CID 777338.) Signed-off-by: Peter Maydell

[Qemu-devel] [PULL for-2.10 4/7] xen: move physmap saving into a separate function

From: Igor Druzhinin Non-functional change. Signed-off-by: Igor Druzhinin Reviewed-by: Stefano Stabellini Reviewed-by: Paul Durrant --- hw/i386/xen/xen-hvm.c | 57

[Qemu-devel] [PULL for-2.10 1/7] hw/xen: Set emu_mask for igd_opregion register

From: Xiong Zhang In igd passthrough environment, guest could only access opregion at the first bootup time. Once guest shutdown, later guest couldn't access opregion anymore. This is because qemu set emulated guest opregion base address to host register. Later guest get

[Qemu-devel] [PULL for-2.0 0/7] please pull xen-20170718-tag

-20170718-tag for you to fetch changes up to 331b5189d756d431b1d18ae7097527ba3d3ea809: xen: don't use xenstore to save/restore physmap anymore (2017-07-18 14:16:52 -0700) Xen 2017/07/18

Re: [Qemu-devel] [PATCH] add scripts/git.orderfile

On Mon, Jul 17, 2017 at 12:16:32 +0200, Gerd Hoffmann wrote: > Based on a old patch by Laszlo. > Time to get this in ... > > Signed-off-by: Gerd Hoffmann > --- > scripts/git.orderfile | 29 + Reviewed-by: Emilio G. Cota Been using

Re: [Qemu-devel] Question for iotests 188, 189 and 087

On 07/18/2017 04:22 PM, Cleber Rosa wrote: > +++ 087.out.bad 2017-07-18 17:01:37.736038689 -0400 > @@ -27,7 +27,7 @@ > Testing: > QMP_VERSION > {"return": {}} > -{"error": {"class": "GenericError", "desc": "aio=native was specified, > but it requires cache.direct=on, which was not

Re: [Qemu-devel] [PATCH 0/8] target/alpha cleanups

On Thu, Jul 13, 2017 at 14:18:11 -1000, Richard Henderson wrote: > The new title holder for perf top is helper_lookup_tb_ptr. > Those targets that have a complicated cpu_get_tb_cpu_state > function are going to regret that. > > > This cleans up the Alpha version of that function such that it is

Re: [Qemu-devel] [PATCH 11/14] target/mips: Add segmentation control registers

On 18/07/2017 12:55, James Hogan wrote: > The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 & > CP0_SegCtl2 control the behaviour and required privilege of the legacy > virtual memory segments. > > Add them to the CP0 interface so they can be read and written when >

Re: [Qemu-devel] [PATCH for-2.10 4/4] bsd-user/main.c: Fix unused variable warning

On 07/18/2017 11:26 AM, Peter Maydell wrote: > On OpenBSD the compiler warns: > bsd-user/main.c:622:21: warning: variable 'sig' set but not used > [-Wunused-but-set-variable] > > This is because a lot of the signal delivery code is #if-0'd > out as unused. Reshuffle #ifdefs a bit to silence the

[Qemu-devel] [PULL 11/31] target/sh4: Recognize common gUSA sequences

From: Richard Henderson For many of the sequences produced by gcc or glibc, we can translate these as host atomic operations. Which saves the need to acquire the exclusive lock. Signed-off-by: Richard Henderson Message-Id:

[Qemu-devel] [PULL 16/31] target/sh4: Pass DisasContext to fpr64 routines

From: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson Message-Id: <20170718200255.31647-13-...@twiddle.net> [aurel32: fix whitespace issues]

[Qemu-devel] [PULL 15/31] target/sh4: Unify cpu_fregs into FREG

From: Richard Henderson We were treating FREG as an index and REG as a TCGv. Making FREG return a TCGv is both less confusing and a step toward cleaner banking of cpu_fregs. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Aurelien Jarno

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