Re: [Qemu-devel] [PATCH 01/17] openpic: debug w/ info_report()

On Sun, Nov 26, 2017 at 03:58:59PM -0600, Michael Davidsaver wrote: > Replace *printf() with *_report(). > Remove trailing new lines. > > Signed-off-by: Michael Davidsaver Applied to ppc-for-2.12. > --- > hw/intc/openpic.c | 102 >

Re: [Qemu-devel] [PATCH v4 3/3] spapr/rtas: do not reset the MSR in stop-self command

On Fri, Nov 24, 2017 at 08:05:50AM +0100, Cédric Le Goater wrote: > When a CPU is stopped with the 'stop-self' RTAS call, its state > 'halted' is switched to 1 and, in this case, the MSR is not taken into > account anymore in the cpu_has_work() routine. Only the pending > hardware interrupts are

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/25] ppc/xics: introduce an icp_create() helper

On Fri, Nov 24, 2017 at 10:55:47AM +0100, Greg Kurz wrote: > On Fri, 24 Nov 2017 13:51:00 +1100 > David Gibson wrote: > > > On Thu, Nov 23, 2017 at 02:29:31PM +0100, Cédric Le Goater wrote: > > > The sPAPR and the PowerNV core objects create the interrupt presenter >

Re: [Qemu-devel] [PATCH 07/17] e500: fix pci host bridge class/type

On Sun, Nov 26, 2017 at 03:59:05PM -0600, Michael Davidsaver wrote: > Correct some confusion wrt. the PCI facing > side of the PCI host bridge (not PCIe root complex). > The ref. manual for the mpc8533 (as well as > mpc8540 and mpc8540) give the class code as > PCI_CLASS_PROCESSOR_POWERPC. > While

Re: [Qemu-devel] [PATCH v4 2/3] spapr/rtas: fix reboot of a a SMP TCG guest

On Fri, Nov 24, 2017 at 08:05:49AM +0100, Cédric Le Goater wrote: > Just like for hot unplug CPUs, when a guest is rebooted, the secondary > CPUs can be awaken by the decrementer and start entering SLOF at the > same time the boot CPU is. > > To be safe, let's disable on the secondaries all the

Re: [Qemu-devel] [PATCH 03/17] i2c: add mpc8540 i2c controller

On Sun, Nov 26, 2017 at 03:59:01PM -0600, Michael Davidsaver wrote: > Signed-off-by: Michael Davidsaver > --- > hw/i2c/Makefile.objs | 1 + > hw/i2c/mpc8540_i2c.c | 307 > +++ > hw/i2c/trace-events | 6 + > 3 files

Re: [Qemu-devel] [PATCH v4 1/3] spapr/rtas: disable the decrementer interrupt when a CPU is unplugged

On Fri, Nov 24, 2017 at 08:05:48AM +0100, Cédric Le Goater wrote: > When a CPU is stopped with the 'stop-self' RTAS call, its state > 'halted' is switched to 1 and, in this case, the MSR is not taken into > account anymore in the cpu_has_work() routine. Only the pending > hardware interrupts are

Re: [Qemu-devel] [qemu-s390x] [PATCH v3 1/7] s390x/pci: factor out endianess conversion

On 25.11.2017 14:49, Pierre Morel wrote: > On 24/11/2017 07:19, Yi Min Zhao wrote: >> >> >> 在 2017/11/23 下午8:18, Thomas Huth 写道: >>> On 23.11.2017 13:07, Yi Min Zhao wrote: 在 2017/11/23 下午6:33, Cornelia Huck 写道: > On Thu, 23 Nov 2017 11:25:10 +0100 > Thomas Huth

Re: [Qemu-devel] [PATCH v3 2/7] s390x/pci: rework PCI STORE

On 25.11.2017 11:39, Pierre Morel wrote: > On 23/11/2017 10:01, Thomas Huth wrote: >> On 22.11.2017 23:05, Pierre Morel wrote: >>> Enhance the fault detection, correction of the fault reporting. >>> >>> Signed-off-by: Pierre Morel >>> Reviewed-by: Yi Min Zhao

Re: [Qemu-devel] [qemu-s390x] [PATCH v3 1/7] s390x/pci: factor out endianess conversion

在 2017/11/25 下午9:49, Pierre Morel 写道: On 24/11/2017 07:19, Yi Min Zhao wrote: 在 2017/11/23 下午8:18, Thomas Huth 写道: On 23.11.2017 13:07, Yi Min Zhao wrote: 在 2017/11/23 下午6:33, Cornelia Huck 写道: On Thu, 23 Nov 2017 11:25:10 +0100 Thomas Huth wrote: On 23.11.2017

Re: [Qemu-devel] [RFC v4 21/27] qmp: let migrate-incoming allow out-of-band

On Fri, Nov 24, 2017 at 01:14:53PM +, Dr. David Alan Gilbert wrote: > * Peter Xu (pet...@redhat.com) wrote: > > So it can get rid of being run on main thread. > > > > Signed-off-by: Peter Xu > > Last time I asked if you were sure that we didn't do locking, > and you

[Qemu-devel] [PATCH v3 3/3] nvdimm: add 'unarmed' option

Currently the only vNVDIMM backend can guarantee the guest write persistence is device DAX on Linux, because no host-side kernel cache is involved in the guest access to it. The approach to detect whether the backend is device DAX needs to access sysfs, which may not work with SELinux. Instead,

[Qemu-devel] [PATCH v3 1/3] hostmem-file: add "align" option

When mmap(2) the backend files, QEMU uses the host page size (getpagesize(2)) by default as the alignment of mapping address. However, some backends may require alignments different than the page size. For example, mmap a device DAX (e.g., /dev/dax0.0) on Linux kernel 4.13 to an address, which is

[Qemu-devel] [PATCH-for-2.12 v3 0/3] nvdimm: fixes for (non-)dax backends

Previous versions can be found at v2: https://lists.gnu.org/archive/html/qemu-devel/2017-06/msg01203.html v1: https://lists.gnu.org/archive/html/qemu-devel/2017-05/msg05919.html Changes in v3: * Add an option 'align' to 'memory-backend-file' to address the failure when mmap device dax

[Qemu-devel] [PATCH v3 2/3] nvdimm: add a macro for property "label-size"

Signed-off-by: Haozhong Zhang Reviewed-by: Stefan Hajnoczi --- hw/mem/nvdimm.c | 2 +- include/hw/mem/nvdimm.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c index

[Qemu-devel] [PULL 1/2] target/ppc: Move setting of patb_entry on hash table init

From: Suraj Jitindar Singh The patb_entry is used to store the location of the process table in guest memory. The msb is also used to indicate the mmu mode of the guest, that is patb_entry & 1 << 63 ? radix_mode : hash_mode. Currently we set this to zero in

[Qemu-devel] [PULL 0/2] ppc-for-2.11 queue 20171127

The following changes since commit e7b47c22e2df14d55e3e4426688c929bf8e3f7fb: osdep.h: Make TIME_MAX handle different time_t types (2017-11-24 13:23:36 +) are available in the Git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.11-20171127 for you to fetch changes up to

[Qemu-devel] [PULL 2/2] target/ppc: Fix setting of cpu->compat_pvr on incoming migration

From: Suraj Jitindar Singh cpu->compat_pvr is used to store the current compat mode of the cpu. On the receiving side during incoming migration we check compatibility with the compat mode by calling ppc_set_compat(). However we fail to set the compat mode with the

[Qemu-devel] [PATCH v3] gdbstub: add tracing

Signed-off-by: Doug Gale --- gdbstub.c| 101 ++- trace-events | 21 + 2 files changed, 87 insertions(+), 35 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 2a94030d3b..86482fa009 100644 ---

[Qemu-devel] [PATCH v2] gdbstub: add tracing

Signed-off-by: Doug Gale --- gdbstub.c| 101 ++- trace-events | 21 + 2 files changed, 87 insertions(+), 35 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 2a94030d3b..86482fa009 100644 ---

Re: [Qemu-devel] [PATCH] gdbstub: add tracing

Hi, This series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally. Subject: [Qemu-devel] [PATCH] gdbstub: add tracing Type: series Message-id: 20171127041038.22819-1-doug...@gmail.com ===

[Qemu-devel] [PATCH] gdbstub: add tracing

Signed-off-by: Doug Gale --- gdbstub.c| 100 ++- trace-events | 21 + 2 files changed, 86 insertions(+), 35 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 2a94030d3b..a75f319bd0 100644 ---

Re: [Qemu-devel] ui: Support non-zero minimum values for absolute input axes

Philippe Voinov: > This patch refactors ui/input.c to support absolute axis > minimum values other than 0. All dependent calls to qemu_input_queue_abs > have been updated to explicitly supply 0 as the axis minimum value. Shouldn't the patch also also pass old_value - 1 as the second argument?

Re: [Qemu-devel] [PATCH v9 13/13] xlnx-zcu102: Add support for the ZynqMP QSPI

On 11/26/2017 08:16 PM, Francisco Iglesias wrote: > Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy > QSPI) and connect Numonyx n25q512a11 flashes to it. > > Signed-off-by: Francisco Iglesias > Reviewed-by: Alistair Francis

Re: [Qemu-devel] [PATCH v9 08/13] xilinx_spips: Make tx/rx_data_bytes more generic and reusable

Hi Francisco, On 11/26/2017 08:16 PM, Francisco Iglesias wrote: > Make tx/rx_data_bytes more generic so they can be reused (when adding > support for the Zynqmp Generic QSPI). > > Signed-off-by: Francisco Iglesias > Reviewed-by: Edgar E. Iglesias

Re: [Qemu-devel] [PATCH v9 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands

On 11/26/2017 08:16 PM, Francisco Iglesias wrote: > Add support for SST READ ID 0x90/0xAB commands for reading out the flash > manufacturer ID and device ID. > > Signed-off-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daudé > --- >

Re: [Qemu-devel] [PATCH for 2.11] virtio-net: don't touch virtqueue if vm is stopped

On 2017年11月24日 18:44, Stefan Hajnoczi wrote: On Fri, Nov 24, 2017 at 10:57:11AM +0800, Jason Wang wrote: On 2017年11月23日 18:59, Stefan Hajnoczi wrote: On Thu, Nov 23, 2017 at 11:37:46AM +0800, Jason Wang wrote: Guest state should not be touched if VM is stopped, unfortunately we didn't check

Re: [Qemu-devel] [PATCH v3] rcu: reduce more than 7MB heap memory by malloc_trim()

On Sun, Nov 26, 2017 at 02:17:18PM +0800, Shannon Zhao wrote: > Hi, > > On 2017/11/24 14:30, Yang Zhong wrote: > > Since there are some issues in memory alloc/free machenism > > in glibc for little chunk memory, if Qemu frequently > > alloc/free little chunk memory, the glibc doesn't alloc > >

Re: [Qemu-devel] [RFC v4 23/27] monitor: enable IO thread for (qmp & !mux) typed

On Fri, Nov 24, 2017 at 11:01:49AM +, Dr. David Alan Gilbert wrote: > * Peter Xu (pet...@redhat.com) wrote: > > Start to use dedicate IO thread for QMP monitors that are not using > > MUXed chardev. > > > > Signed-off-by: Peter Xu > > Reviewed-by: Dr. David Alan Gilbert

Re: [Qemu-devel] [PATCH v2 3/6] ppc: e500: Allow only supported dynamic sysbus devices

On Sat, Nov 25, 2017 at 01:16:07PM -0200, Eduardo Habkost wrote: > platform_bus_create_devtree() already rejects all dynamic sysbus > devices except TYPE_ETSEC_COMMON, so register it as the only > allowed dynamic sysbus device for the ppce500 machine-type. > > Cc: Alexander Graf >

Re: [Qemu-devel] [RFC PATCH 1/1] s390x/css: unresrict cssids

* Halil Pasic [2017-11-24 17:39:04 +0100]: > > > On 11/24/2017 05:15 PM, Cornelia Huck wrote: > >>> In theory this should work. > >>> > >>> In reality it seems more complicated. A per-device property is easy and > >>> can be > >>> inspected on the command line (e.g.

Re: [Qemu-devel] [PATCH v2 1/6] machine: Replace has_dynamic_sysbus with list of allowed devices

On Sat, Nov 25, 2017 at 01:16:05PM -0200, Eduardo Habkost wrote: > The existing has_dynamic_sysbus flag makes the machine accept > every user-creatable sysbus device type on the command-line. > Replace it with a list of allowed device types, so machines can > easily accept some sysbus devices

Re: [Qemu-devel] [PATCH v2 4/6] spapr: Allow only supported dynamic sysbus devices

On Sat, Nov 25, 2017 at 01:16:08PM -0200, Eduardo Habkost wrote: > TYPE_SPAPR_PCI_HOST_BRIDGE is the only dynamic sysbus device not > rejected by ppc_spapr_reset(), so it can be the only entry on the > allowed list. > > Cc: David Gibson > Cc: Alexander Graf

[Qemu-devel] [PATCH v9 10/13] xilinx_spips: Add support for 4 byte addresses in the LQSPI

Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias

[Qemu-devel] [PATCH v9 09/13] xilinx_spips: Add support for zero pumping

Add support for zero pumping according to the transfer size register. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 47

[Qemu-devel] [PATCH v9 08/13] xilinx_spips: Make tx/rx_data_bytes more generic and reusable

Make tx/rx_data_bytes more generic so they can be reused (when adding support for the Zynqmp Generic QSPI). Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias ---

[Qemu-devel] [PATCH v9 07/13] xilinx_spips: Add support for RX discard and RX drain

Add support for the RX discard and RX drain functionality. Also transmit one byte per dummy cycle (to the flash memories) with commands that require these. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E.

[Qemu-devel] [PATCH v9 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done

Don't set TX FIFO UNDERFLOW interrupt after transmitting the commands. Also update interrupts after reading out the interrupt status. Signed-off-by: Francisco Iglesias Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias

[Qemu-devel] [PATCH v9 05/13] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass

Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the header for consistency (struct XilinxSPIPS is found there). Also move out a define and remove two double included headers (while touching the code). Finally, add 4 byte address commands to the FlashCMD enum.

[Qemu-devel] [PATCH v9 12/13] xilinx_spips: Add support for the ZynqMP Generic QSPI

Add support for the Zynq Ultrascale MPSoc Generic QSPI. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- default-configs/arm-softmmu.mak | 2 +-

[Qemu-devel] [PATCH v9 13/13] xlnx-zcu102: Add support for the ZynqMP QSPI

Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy QSPI) and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias

[Qemu-devel] [PATCH v9 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60)

Add support for the bank address register access commands (BRRD/BRWR) and the BULK_ERASE (0x60) command. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemiński Reviewed-by: Edgar E. Iglesias Tested-by: Edgar

[Qemu-devel] [PATCH v9 04/13] m25p80: Add support for n25q512a11 and n25q512a13

Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemiński Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias

[Qemu-devel] [PATCH v9 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands

Add support for SST READ ID 0x90/0xAB commands for reading out the flash manufacturer ID and device ID. Signed-off-by: Francisco Iglesias --- hw/block/m25p80.c | 32 1 file changed, 32 insertions(+) diff --git a/hw/block/m25p80.c

[Qemu-devel] [PATCH v9 06/13] xilinx_spips: Update striping to be big-endian bit order

Update striping functionality to be big-endian bit order (as according to the Zynq-7000 Technical Reference Manual). Output thereafter the even bits into the flash memory connected to the lower QSPI bus and the odd bits into the flash memory connected to the upper QSPI bus. Signed-off-by:

[Qemu-devel] [PATCH v9 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR

Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. This feature is supported by amongst others 1 or more flashtypes manufactured by Numonyx (Micron), Windbond, SST, Gigadevice, Eon and Macronix. Signed-off-by: Francisco Iglesias

[Qemu-devel] [PATCH v9 00/13] Add support for the ZynqMP Generic QSPI

Hi, This patch series is an attempt to add support for the ZynqMP QSPI (consisting of the Generic QSPI and the legacy QSPI) to the xlnx-zcu102 board and connect Numonyx n25q512a11 flashes to the QSPI. Also some functionality is added to m25p80. The series starts by adding support in m25p80 for

Re: [Qemu-devel] [PATCH v8 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands

On 26 November 2017 at 01:45, Philippe Mathieu-Daudé wrote: > Hi Francisco, > > On 11/24/2017 06:29 PM, Francisco Iglesias wrote: > > Add support for SST READ ID 0x90/0xAB commands for reading out the flash > > manufacuter ID and device ID. > > > > Signed-off-by: Francisco

[Qemu-devel] [PATCH 16/17] tests: run ds-rtc-i2c-test w/ ppc/mvme3100

Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 3 ++- tests/ds-rtc-i2c-test.c | 8 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tests/Makefile.include b/tests/Makefile.include index 56045cdf09..062d4e5b7b 100644 ---

[Qemu-devel] [PATCH 15/17] ppc: add mvme3100 machine

Signed-off-by: Michael Davidsaver --- default-configs/ppc-softmmu.mak | 1 + hw/ppc/Makefile.objs| 1 + hw/ppc/mvme3100.c | 740 hw/ppc/mvme3100_cpld.c | 192 +++ 4 files changed, 934

[Qemu-devel] [PATCH 12/17] e500: add i2c controller to CCSR

Add i2c controller found on mpc8540, mpc8544, and P2010 (newer ppc, unmodeled). Signed-off-by: Michael Davidsaver --- hw/ppc/e500_ccsr.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index

[Qemu-devel] [PATCH 17/17] tests: add mvme3100-test

Exercise some features of the mvme3100 CPLD logic and read from the eeprom w/ VPD. Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 3 ++ tests/mvme3100-test.c | 79 ++ 2 files changed, 82 insertions(+)

[Qemu-devel] [PATCH 14/17] e500: split mpc8544ds specific initialization

split off the remaining board specific parts of e500_init() as mpc85xx_init() which will be used by the existing mpc8544ds and generic e500 boards. Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 49 -

[Qemu-devel] [PATCH 05/17] timer: generalize Dallas/Maxim RTC i2c devices

Support for: ds1307, ds1337, ds1338, ds1339, ds1340, ds1375, ds1388, and ds3231. Tested with ds1338 and ds1375. Signed-off-by: Michael Davidsaver --- default-configs/arm-softmmu.mak | 2 +- hw/timer/Makefile.objs | 2 +- hw/timer/ds-rtc-i2c.c | 461

[Qemu-devel] [PATCH 09/17] e500: move mpic under CCSR

Start moving code out of ppce500_init() Existing ppce500_init_mpic() suggests that MPIC may not be created w/ KVM. However, ppce500_init() used mpicdev unconditionally, and would fail if the MPIC isn't created. So require creation. Not tested with KVM for lack of hardware. Signed-off-by:

[Qemu-devel] [PATCH 13/17] e500: move PCI host bridge into CCSR

Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 13 - hw/ppc/e500_ccsr.c | 27 +++ 2 files changed, 31 insertions(+), 9 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index cfd5ed0152..b0c8495aef 100644 ---

[Qemu-devel] [PATCH 07/17] e500: fix pci host bridge class/type

Correct some confusion wrt. the PCI facing side of the PCI host bridge (not PCIe root complex). The ref. manual for the mpc8533 (as well as mpc8540 and mpc8540) give the class code as PCI_CLASS_PROCESSOR_POWERPC. While the PCI_HEADER_TYPE field is oddly omitted, the tables in the "PCI

[Qemu-devel] [PATCH 08/17] e500: additional CCSR registers

Add CCSRBAR to allow CCSR region to be relocated. Guest memory size introspection via RAM config registers. Dummy RAM error controls. Clock introspection via Power on Reset PLL Status Register. Signed-off-by: Michael Davidsaver ccsrbase also update iack ---

[Qemu-devel] [PATCH 03/17] i2c: add mpc8540 i2c controller

Signed-off-by: Michael Davidsaver --- hw/i2c/Makefile.objs | 1 + hw/i2c/mpc8540_i2c.c | 307 +++ hw/i2c/trace-events | 6 + 3 files changed, 314 insertions(+) create mode 100644 hw/i2c/mpc8540_i2c.c diff --git

[Qemu-devel] [PATCH 06/17] tests: rewrite testing for DS RTC devices

Replace existing ds1338-test with more thorough test of time read and set. Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 4 +- tests/ds-rtc-i2c-test.c | 162 tests/ds1338-test.c | 77

[Qemu-devel] [PATCH 11/17] e500: derive baud from CCB clock

The CCB (Complex Core Bus) clock is the reference for the DUARTs with an extra divide by 16. >From the mpc8540, mpc8544, and P2010 ref manuals. CCB=333MHz, with divider=0x87a gives ~9600 baud. 333e6 Hz/(16*0x87a) = 9591 Hz. This is verified with a real mpc8540. The existing value for the

[Qemu-devel] [PATCH 01/17] openpic: debug w/ info_report()

Replace *printf() with *_report(). Remove trailing new lines. Signed-off-by: Michael Davidsaver --- hw/intc/openpic.c | 102 +++--- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/hw/intc/openpic.c

[Qemu-devel] [PATCH 04/17] qtest: add e500_i2c_create()

Add interface for testing i2c devices with PPC e500. Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 1 + tests/libqos/i2c-e500.c | 66 + tests/libqos/i2c.h | 3 +++ 3 files changed, 70 insertions(+)

[Qemu-devel] [PATCH 10/17] e500: move uarts CCSR

Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 13 - hw/ppc/e500_ccsr.c | 18 ++ 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 1872bb8eaa..2d87d91582 100644 --- a/hw/ppc/e500.c

[Qemu-devel] [PATCH 00/17] Add MVME3100 PPC SBC v2

Changes since previous iteration. openpic: debug w/ info_report() New i2c: start trace-events i2c: add mpc8540 i2c controller Debugging cleanup and fix a spurious warning triggered by Linux guests. qtest: add e500_i2c_create() Unchanged timer: generalize Dallas/Maxim RTC i2c devices

[Qemu-devel] [PATCH 02/17] i2c: start trace-events

Signed-off-by: Michael Davidsaver --- Makefile.objs | 1 + hw/i2c/trace-events | 1 + 2 files changed, 2 insertions(+) create mode 100644 hw/i2c/trace-events diff --git a/Makefile.objs b/Makefile.objs index 285c6f3c15..984ae8ecba 100644 --- a/Makefile.objs +++

Re: [Qemu-devel] [PATCH 13/25] spapr: introduce the XIVE Event Queues

On Fri, 2017-11-24 at 09:15 +0100, Cédric Le Goater wrote: > So The Linux driver is expected to choose priority 6. The priority > validity is then checked in each hcall returning H_P4/H_P3 in case of > failure. > > But it is true that we scale the arrays with : > > #define

[Qemu-devel] [PATCH] configure: Fix curses probe for older ncurses

Fix the curses probe with older ncurses (.e.g. 5.7, as used by OpenBSD). ncurses 5.7 requires _XOPEN_SOURCE_EXTENDED to be defined for WACS_* constants. Signed-off-by: Brad Smith diff --git a/configure b/configure index 0c6e7572db..9715b9c2cc 100755 --- a/configure +++

[Qemu-devel] [Bug 1673976] Re: linux-user clone() can't handle glibc posix_spawn() (causes locale-gen to assert)

Interestingly, this also affects Microsoft Windows Services For Linux, i.e. Microsoft's Linux emulation layer. > https://github.com/Microsoft/WSL/issues/1878 ** Bug watch added: github.com/Microsoft/WSL/issues #1878 https://github.com/Microsoft/WSL/issues/1878 -- You received this bug

Re: [Qemu-devel] glibc "linux: spawni.c: simplify error reporting to parent" breaks qemu-user/Windows Service For Linux

On 11/26/2017 09:28 PM, John Paul Adrian Glaubitz wrote: > I'm not sure yet what the actual problem is but I thought it should be > necessary > to point you at the problem. Ok, there is already a QEMU bug report for this [1]. Adrian > [1] https://bugs.launchpad.net/qemu/+bug/1673976 --

[Qemu-devel] glibc "linux: spawni.c: simplify error reporting to parent" breaks qemu-user/Windows Service For Linux

Hi Rasmus! Your recent commit "linux: spawni.c: simplify error reporting to parent" apparently broke both qemu-user and Microsoft's Windows Services for Linux which both fail with: dpkg: warning: ignoring pre-dependency problem! Preparing to unpack .../archives/bash_4.4-5_m68k.deb ... preinst:

Re: [Qemu-devel] [PATCH 7/8] sun4u_iommu: convert from IOMMU_DPRINTF to trace-events

On 11/26/2017 10:35 AM, Mark Cave-Ayland wrote: > Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé > --- > hw/sparc64/sun4u_iommu.c | 17 +++-- > hw/sparc64/trace-events |4 > 2 files changed, 7

Re: [Qemu-devel] [PATCH 2/8] sun4m: move IOMMU declarations from sun4m.h to sun4m_iommu.h

On 11/26/2017 10:35 AM, Mark Cave-Ayland wrote: > Also updating the relevant .c files as required. > > Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé > --- > hw/dma/sparc32_dma.c |1 + > hw/sparc/sun4m.c

Re: [Qemu-devel] [PATCH 6/8] sun4u_iommu: update to reflect IOMMU is no longer part of the APB device

On 11/26/2017 10:35 AM, Mark Cave-Ayland wrote: > Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé > --- > hw/sparc64/sun4u_iommu.c | 35 ++- > include/hw/sparc/sun4u_iommu.h |2 +- >

Re: [Qemu-devel] [PATCH 3/8] sun4m: remove include/hw/sparc/sun4m.h and all references to it

On 11/26/2017 10:35 AM, Mark Cave-Ayland wrote: > With the previous commit there is now nothing left in sun4m.h so it can be > removed, along with all remaining references to it. Nice! > > Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé

Re: [Qemu-devel] [PATCH v8 05/13] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass

On 11/24/2017 06:29 PM, Francisco Iglesias wrote: > Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the > header for consistency (struct XilinxSPIPS is found there). Also move out > a define and remove two double included headers (while touching the code). > Finally, add 4

Re: [Qemu-devel] [PATCH v8 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands

Hi Francisco, On 11/24/2017 06:29 PM, Francisco Iglesias wrote: > Add support for SST READ ID 0x90/0xAB commands for reading out the flash > manufacuter ID and device ID. > > Signed-off-by: Francisco Iglesias > Acked-by: Alistair Francis

[Qemu-devel] [PATCH 8/8] sun4u_iommu: add trace event for IOMMU translations

Signed-off-by: Mark Cave-Ayland --- hw/sparc64/sun4u_iommu.c |2 ++ hw/sparc64/trace-events |1 + 2 files changed, 3 insertions(+) diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index 51fbc39..4cf8e69 100644 ---

[Qemu-devel] [PATCH 1/8] sun4m: move sun4m_iommu.c from hw/dma to hw/sparc

This seems more appropriate and brings sun4m in line with the other architectures. Signed-off-by: Mark Cave-Ayland --- hw/dma/Makefile.objs |1 - hw/dma/sun4m_iommu.c | 406 --- hw/dma/trace-events| 10 --

[Qemu-devel] [PATCH 4/8] apb: QOMify IOMMU

This is in preparation to split the IOMMU device out of the APB. As part of this commit we also enforce separation of the IOMMU and APB devices by using a QOM object link to pass the IOMMU reference and accessing the IOMMU registers via a separate memory region mapped into the APB config space

[Qemu-devel] [PATCH 6/8] sun4u_iommu: update to reflect IOMMU is no longer part of the APB device

Signed-off-by: Mark Cave-Ayland --- hw/sparc64/sun4u_iommu.c | 35 ++- include/hw/sparc/sun4u_iommu.h |2 +- 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/hw/sparc64/sun4u_iommu.c

[Qemu-devel] [PATCH 3/8] sun4m: remove include/hw/sparc/sun4m.h and all references to it

With the previous commit there is now nothing left in sun4m.h so it can be removed, along with all remaining references to it. Signed-off-by: Mark Cave-Ayland --- hw/dma/sparc32_dma.c |1 - hw/intc/slavio_intctl.c |1 - hw/net/lance.c |2

[Qemu-devel] [PATCH 2/8] sun4m: move IOMMU declarations from sun4m.h to sun4m_iommu.h

Also updating the relevant .c files as required. Signed-off-by: Mark Cave-Ayland --- hw/dma/sparc32_dma.c |1 + hw/sparc/sun4m.c |1 + hw/sparc/sun4m_iommu.c |1 + include/hw/sparc/sun4m.h | 21 -

[Qemu-devel] [PATCH 7/8] sun4u_iommu: convert from IOMMU_DPRINTF to trace-events

Signed-off-by: Mark Cave-Ayland --- hw/sparc64/sun4u_iommu.c | 17 +++-- hw/sparc64/trace-events |4 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index 612fec4..51fbc39

[Qemu-devel] [PATCH 0/8] sparc: IOMMU tidy-up and reorganisation

Following on from the previous sun4u patchset, here is the next step of IOMMU-related updates for 2.12. This patchset does 2 main things: firstly it moves the sun4m IOMMU device out of hw/dma and into hw/sparc to match existing architectures. With this (and the previous sun4m DMA rework) the old

[Qemu-devel] [PATCH 5/8] sun4u: split IOMMU device out from apb.c to sun4u_iommu.c

By separating the sun4u IOMMU device into new sun4u_iommu.c and sun4m_iommu.h files we noticeably simplify apb.c whilst bringing sun4u in line with all the other IOMMU-supporting architectures. Signed-off-by: Mark Cave-Ayland --- hw/pci-host/apb.c |

[Qemu-devel] [PATCHv2 10/15] apb: remove pci_apb_init() and instantiate APB device using qdev

By making the special_base and mem_base values qdev properties, we can move the remaining parts of pci_apb_init() into the pbm init() and realize() functions. This finally allows us to instantiate the APB directly using standard qdev create/init functions in sun4u.c. Signed-off-by: Mark

[Qemu-devel] [PATCHv2 14/15] sparc64: introduce trace-events for hw/sparc64

This is in preparation for switching code in hw/sparc64 from DPRINTF over to trace events. Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé --- Makefile.objs |1

[Qemu-devel] [PATCHv2 12/15] ebus: wire up OBIO interrupts to APB pbm via qdev GPIOs

This enables us to remove the static array mapping in the ISA IRQ handler (and the embedded reference to the APB device) by formalising the interrupt wiring via the qdev GPIO API. For more clarity we replace the APB OBIO interrupt numbers with constants designating the interrupt source, and

[Qemu-devel] [PATCHv2 11/15] apb: split pci_pbm_map_irq() into separate functions for bus A and bus B

After the previous refactoring it is now possible to use separate functions to improve clarity of the interrupt paths. Similarly by checking the PCI devnfn to identify busA during apb_pci_bridge_realize() it becomes possible to completely remove the busA property from the PBMPCIBridge state.

[Qemu-devel] [PATCHv2 13/15] apb: replace OBIO interrupt numbers in pci_pbmA_map_irq() with constants

Following on from the previous commit, we can also do the same with with legacy OBIO interrupts in pci_pbmA_map_irq(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé ---

[Qemu-devel] [PATCHv2 15/15] sun4u: switch from EBUS_DPRINTF() macro to trace-events

Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé --- hw/sparc64/sun4u.c | 12 ++-- hw/sparc64/trace-events |3 +++ 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/hw/sparc64/sun4u.c

[Qemu-devel] [PATCHv2 09/15] apb: move the two secondary PCI bridges objects into APBState

This enables us to remove these parameters from pci_apb_init(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c | 14 +-

[Qemu-devel] [PATCHv2 05/15] sun4u: move initialisation of all ISABus devices into ebus_realize()

This belongs in the PCI-ISA bridge rather than at the machine level. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé --- hw/sparc64/sun4u.c | 78 +++- 1 file changed, 46

[Qemu-devel] [PATCHv2 06/15] apb: APB QOMify tidy-up

Use DeviceClass rather than SysBusDeviceClass in pbm_host_class_init() and adjust pci_pbm_init_device() accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c | 17 - 1 file

[Qemu-devel] [PATCHv2 08/15] apb: use gpios to wire up the apb device to the SPARC CPU IRQs

Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c |6 ++ hw/sparc64/sparc64.c |2 ++ hw/sparc64/sun4u.c | 12 include/hw/pci-host/apb.h |6 --

[Qemu-devel] [PATCHv2 04/15] sun4u: remove pci_ebus_init() function

This is initialisation that should really take place in the ebus realize function. As part of this we also rework the ebus IRQ mapping so that instead of having to pass in the array of pbm_irqs, we obtain a reference to them by looking up the APB device during ebus realize. Signed-off-by: Mark

[Qemu-devel] [PATCHv2 03/15] sun4u: move ISABus inside of EBusState

Since the EBus is effectively a PCI-ISA bridge then the underlying ISA bus should be contained within the PCI bridge itself. Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé

[Qemu-devel] [PATCHv2 01/15] apb: move QOM macros and typedefs from apb.c to apb.h

This also includes the related IOMMUState typedef and defines. Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c | 85

[Qemu-devel] [PATCHv2 07/15] apb: return APBState from pci_apb_init() rather than PCIBus

This is a first step towards removing pci_apb_init() completely. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c |8 hw/sparc64/sun4u.c|6 -- include/hw/pci-host/apb.h

  1   2   >