Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

On Wed, Jan 10, 2018 at 03:46:19PM -0800, Michael Clark wrote: > - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 > - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 > - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 Same question as

Re: [Qemu-devel] [PATCH qemu] target/ppc: Yet another fix for KVM-HV HPTE accessors

On Thu, Jan 11, 2018 at 03:08:32PM +1100, Alexey Kardashevskiy wrote: > As stated in the 1ad9f0a464fe commit log, the returned entries are not > a while PTEG. It was not a problem before 1ad9f0a464fe as it would read > a single record assuming it contains a whole PTEG but now the code tries >

Re: [Qemu-devel] vhost-pci and virtio-vhost-user

On 01/11/2018 12:14 AM, Stefan Hajnoczi wrote: Hi Wei, I wanted to summarize the differences between the vhost-pci and virtio-vhost-user approaches because previous discussions may have been confusing. vhost-pci defines a new virtio device type for each vhost device type (net, scsi, blk). It

Re: [Qemu-devel] [PATCH v14 5/9] target-arm: kvm64: inject synchronous External Abort

Hi Peter. On 2018/1/10 1:30, Peter Maydell wrote: > On 28 December 2017 at 05:54, Dongjiu Geng wrote: >> Add synchronous external abort injection logic, setup >> exception type and syndrome value. When switch to guest, >> guest will jump to the synchronous external abort

[Qemu-devel] [PULL 04/11] ppc4xx_i2c: Implement basic I2C functions

From: BALATON Zoltan Enough to please U-Boot and make it able to detect SDRAM SPD EEPROMs Signed-off-by: François Revol Signed-off-by: BALATON Zoltan Reviewed-by: David Gibson Signed-off-by: David Gibson

[Qemu-devel] [PULL 11/11] spapr: Correct compatibility mode setting for hotplugged CPUs

Currently the pseries machine sets the compatibility mode for the guest's cpus in two places: 1) at machine reset and 2) after CAS negotiation. This means that if we set or negotiate a compatiblity mode, then hotplug a cpu, the hotplugged cpu doesn't get the right mode set and will incorrectly

[Qemu-devel] [PULL 07/11] ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency

From: Cédric Le Goater The 'pnv' prefix is now used for all and the routines populating the device tree start with 'pnv_dt'. The handler of the PnvXScomInterface is also renamed to 'dt_xscom' which should reflect that it is populating the device tree under the 'xscom@' node of the

[Qemu-devel] [PULL 06/11] hw/ide: Emulate SiI3112 SATA controller

From: BALATON Zoltan This is a common generic PCI SATA controller that is also used in PCs but more importantly guests running on the Sam460ex board prefer this card and have a driver for it (unlike for other SATA controllers already emulated). Signed-off-by: BALATON Zoltan

[Qemu-devel] [PULL 08/11] target/ppc: more use of the PPC_*() macros

From: Cédric Le Goater Also introduce utilities to manipulate bitmasks (originaly from OPAL) which be will be used in the model of the XIVE interrupt controller. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 03/11] sm501: Add some more unimplemented registers

From: BALATON Zoltan These are not really implemented (just return zero or default values) but add these so guests accessing them can run. Signed-off-by: BALATON Zoltan Signed-off-by: David Gibson --- hw/display/sm501.c |

[Qemu-devel] [PULL 10/11] hw/ppc: Remove the deprecated spapr-pci-vfio-host-bridge device

From: Thomas Huth It's a deprecated dummy device since QEMU v2.6.0. That should have been enough time to allow the users to update their scripts in case they still use it, so let's remove this legacy code now. Reviewed-by: Alexey Kardashevskiy Signed-off-by:

[Qemu-devel] [PULL 05/11] spapr_pci: use warn_report()

From: Greg Kurz These two are definitely warnings. Let's use the appropriate API. Signed-off-by: Greg Kurz Signed-off-by: David Gibson --- hw/ppc/spapr_pci.c | 6 +++--- hw/ppc/spapr_pci_vfio.c | 2 +- 2 files changed, 4

[Qemu-devel] [PULL 00/11] ppc-for-2.12 queue 20180111

The following changes since commit 3cee4db661ab9c0fce7937b3bbfa188a1845f31f: Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-01-08' into staging (2018-01-09 15:22:47 +) are available in the Git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20180111

[Qemu-devel] [PULL 02/11] sm501: Add panel hardware cursor registers also to read function

From: BALATON Zoltan These were forgotten when adding panel layer support in ffd39257018 "SM501 emulation for R2D-SH4". Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé [dwg: Added reference to earlier commit in

[Qemu-devel] [PULL 09/11] Update dtc to fix compilation problem on Mac OS 10.6

From: John Arbuckle Currently QEMU does not build on Mac OS 10.6 because of a missing patch in the dtc subproject. Updating dtc to make the patch available fixes this problem. Signed-off-by: John Arbuckle Signed-off-by: David Gibson

[Qemu-devel] [PATCH qemu] target/ppc: Yet another fix for KVM-HV HPTE accessors

As stated in the 1ad9f0a464fe commit log, the returned entries are not a while PTEG. It was not a problem before 1ad9f0a464fe as it would read a single record assuming it contains a whole PTEG but now the code tries reading the entire PTEG and "if ((n - i) < invalid)" produces negative values

Re: [Qemu-devel] [PATCH v5 2/4][RFC] tap: do not close fd if only vhost failed to initialize

Hi Jason, > -Original Message- > From: Jason Wang [mailto:jasow...@redhat.com] > Sent: Thursday, January 11, 2018 11:35 AM > To: Zhoujian (jay) ; qemu-devel@nongnu.org > Cc: Huangweidong (C) ; m...@redhat.com; wangxin (U) >

Re: [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2)

Hi, This series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally. Type: series Message-id: 20180109154519.25634-1-ehabk...@redhat.com Subject: [Qemu-devel] [PATCH 0/7] CPU model updates for

Re: [Qemu-devel] [PATCH v5 2/4][RFC] tap: do not close fd if only vhost failed to initialize

On 2018年01月10日 15:39, Zhoujian (jay) wrote: +*vhost_init_failed = true; Why not simply check s->vhost_net after call net_init_tap_one()? s->vhost_net is always NULL if net_init_tap_one() failed, it can't distinguish failure reasons. On which condition net_init_tap_one() fail

Re: [Qemu-devel] [PATCH v5 3/7] vhost: Simplify ring verification checks

On 2018年01月10日 18:23, Igor Mammedov wrote: On Mon, 8 Jan 2018 17:54:50 + "Dr. David Alan Gilbert" wrote: * Igor Mammedov (imamm...@redhat.com) wrote: On Mon, 18 Dec 2017 20:13:36 + "Dr. David Alan Gilbert (git)" wrote: From: "Dr.

[Qemu-devel] [RFC PATCH 5/5] vfio/ccw: build schib with real schib information

The current implementation grabs chpids and path masks from sysfs to build the schib and chp for the virtual subchannels. Since now vfio-ccw provides a schib region for store subchannel information. Let's leverage it to get the chipids and the masks, and serve the virtual subchannels. While we

[Qemu-devel] [RFC PATCH 4/5] vfio/ccw: update subchanel information block lazily

We want to sync up channel path related information between the physical device and the virtual device. Thus here we read out subchannel information block from the schib region, and update the virtual sbuchannel information block. Since the kernel side will signal userland once it has channel

[Qemu-devel] [RFC PATCH 2/5] vfio/ccw: get schib region info

vfio-ccw provides an MMIO region for store subchannel information. We fetch this information via ioctls here, then we can use it to update schib for virtual subchannels later on. While we are at it, also modify the comment and error message for the config region a bit, to make these unified with

[Qemu-devel] [RFC PATCH 3/3] vfio: ccw: handle chp event

This adds channel path related event handler for vfio-ccw. This also signals userland when there is a chp event. Signed-off-by: Dong Jia Shi --- drivers/s390/cio/vfio_ccw_drv.c | 51 + drivers/s390/cio/vfio_ccw_fsm.c | 22

[Qemu-devel] [RFC PATCH 3/5] vfio/ccw: get irq info and set up handler for chp irq

vfio-ccw now resorts to the eventfd mechanism to communicate with userland for channel path related event. To get notification of the channel path event, userland basically needs to: 1. check the chp irq capability via issuing VFIO_DEVICE_GET_IRQ_INFO ioctl with VFIO_CCW_CHP_IRQ_INDEX. 2.

[Qemu-devel] [RFC PATCH 0/5] vfio/ccw: basic channel path event handling

Hi Folks, This is the QEMU couterpart for the "basic channel path event handling" series. For more information, please refer to the kernel counterpart. Dong Jia Shi (5): vfio: linux-headers update for vfio-ccw vfio/ccw: get schib region info vfio/ccw: get irq info and set up handler for

[Qemu-devel] [RFC PATCH 1/5] vfio: linux-headers update for vfio-ccw

This is a placeholder for a linux-headers update. Signed-off-by: Dong Jia Shi --- linux-headers/linux/vfio.h | 2 ++ linux-headers/linux/vfio_ccw.h | 6 ++ 2 files changed, 8 insertions(+) diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h

[Qemu-devel] [RFC PATCH 2/3] vfio: ccw: introduce channel path irq

This introduces a new irq for vfio-ccw to provide channel path related event for userland. Signed-off-by: Dong Jia Shi --- drivers/s390/cio/vfio_ccw_ops.c | 29 + drivers/s390/cio/vfio_ccw_private.h | 2 ++ include/uapi/linux/vfio.h

[Qemu-devel] [RFC PATCH 1/3] vfio: ccw: introduce schib region

This introduces a new region for vfio-ccw to provide subchannel information for user space. Signed-off-by: Dong Jia Shi --- drivers/s390/cio/vfio_ccw_fsm.c | 21 ++ drivers/s390/cio/vfio_ccw_ops.c | 79 +++--

[Qemu-devel] [RFC PATCH 0/3] vfio: ccw: basic channel path event handling

Hi Folks, Background == Some days ago, we had a discussion on the topic of channel path virtualization. Ref: Subject: [PATCH 0/3] Channel Path realted CRW generation Message-Id: <20170727015418.85407-1-bjsdj...@linux.vnet.ibm.com> URL:

Re: [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1515637324-96034-1-git-send-email-...@sifive.com Subject: [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3 === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1

Re: [Qemu-devel] [Qemu-discuss] ppc and icount

On Wed, Jan 10, 2018 at 10:34:18AM +, Peter Maydell wrote: > On 10 January 2018 at 08:57, Steven Seeger > wrote: > > Sorry for another post. I did a bisect and found what is the bad commit for > > me: > > > > 044897ef4a22af89aecb8df509477beba0a2e0ce is the

Re: [Qemu-devel] [PULL 00/12] ppc-for-2.12 queue 20180108

On Wed, Jan 10, 2018 at 02:33:41PM +0100, Paolo Bonzini wrote: > On 10/01/2018 02:55, David Gibson wrote: > > On Tue, Jan 09, 2018 at 03:15:25PM +, Peter Maydell wrote: > >> On 9 January 2018 at 12:16, David Gibson > >> wrote: > >>> Thanks. Even if you can

Re: [Qemu-devel] [PATCH v1 2/2] intel-iommu: Extend address width to 48 bits

> -Original Message- > From: Qemu-devel [mailto:qemu-devel-bounces+yi.l.liu=intel@nongnu.org] On > Behalf Of Prasad Singamsetty > Sent: Thursday, January 11, 2018 8:06 AM > To: Liu, Yi L > Cc: ehabk...@redhat.com; m...@redhat.com; konrad.w...@oracle.com;

Re: [Qemu-devel] virtio-9p: hot-plug/unplug about virtio-9p device

On 2018/1/8 18:10, Greg Kurz wrote: > On Tue, 19 Dec 2017 13:41:12 +0800 > sochin.jiang wrote: > >> Hi, guys. >> >> I'm looking for the hot-plug/unplug features of virtio-9p device >> recently, and found there's a lack of support. >> >> I am wondering why

[Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU RISC-V code generator has complete coverage for the Base ISA v2.2, Privileged ISA v1.9.1 and Privileged ISA v1.10: - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 - RISC-V Instruction Set Manual Volume II:

[Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure

This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'

[Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark --- hw/riscv/sifive_e300.c | 232 +

[Qemu-devel] [PATCH v3 15/21] RISC-V Spike Machines

RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V Instruction Set Simulator. The following machines are implemented: - 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1 - 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10 Signed-off-by:

[Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console

HTIF (Host Target Interface) provides console emulation for QEMU. HTIF allows identical copies of BBL (Berkeley Boot Loader) and linux to run on both Spike and QEMU. BBL provides HTIF console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The HTIF interface

[Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block

The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Signed-off-by: Michael Clark --- hw/riscv/sifive_clint.c | 312

[Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers

Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark --- target/riscv/helper.c| 499 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c | 682

[Qemu-devel] [PATCH v3 20/21] SiFive Freedom U500 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark --- hw/riscv/sifive_u500.c | 338 +

[Qemu-devel] [PATCH v3 04/21] RISC-V Disassembler

The RISC-V disassembler has no dependencies outside of the 'disas' directory so it can be applied independently. The majority of the disassembler is machine-generated from instruction set metadata: - https://github.com/michaeljclark/riscv-meta Expected checkpatch errors for consistency and

[Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub

GDB Register read and write routines. Signed-off-by: Michael Clark --- target/riscv/gdbstub.c | 59 ++ 1 file changed, 59 insertions(+) create mode 100644 target/riscv/gdbstub.c diff --git a/target/riscv/gdbstub.c

[Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block

The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark --- hw/riscv/sifive_plic.c | 554 +

[Qemu-devel] [PATCH v3 16/21] RISC-V VirtIO Machine

RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark --- hw/riscv/virt.c | 364

[Qemu-devel] [PATCH v3 10/21] RISC-V Linux User Emulation

Implementation of linux user emulation for RISC-V. Signed-off-by: Michael Clark --- linux-user/elfload.c | 22 +++ linux-user/main.c | 114 +++ linux-user/riscv/syscall_nr.h | 275 +++

[Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition

Add CPU state header, CPU definitions and initialization routines Signed-off-by: Michael Clark --- target/riscv/cpu.c | 391 + target/riscv/cpu.h | 271 +++ target/riscv/cpu_bits.h | 417

[Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block

Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 107 + include/hw/riscv/sifive_prci.h | 43 + 2

[Qemu-devel] [PATCH v3 17/21] SiFive RISC-V UART Device

QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in

[Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection

Implements the physical memory protection extension as specified in Privileged ISA Version 1.10. PMP (Physical Memory Protection) is as-of-yet unused and needs testing. The SiFive verification team have PMP test cases that will be run. Nothing currently depends on PMP support. It would be

[Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3

QEMU RISC-V Emulation Support (RV64GC, RV32GC) This patch series has major clean ups to target/riscv. There may be some feedback that has been missed however the changelog is growing quite large so we have decided to respin the patch series. No new features have been added however a number of

[Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support

Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 591 + 2 files changed, 595 insertions(+), 3 deletions(-) create mode 100644

[Qemu-devel] [PATCH v3 02/21] RISC-V ELF Machine Definition

Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson Signed-off-by: Michael Clark --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 ---

[Qemu-devel] [PATCH v3 12/21] RISC-V HART Array

Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 insertions(+)

[Qemu-devel] [PATCH v3 01/21] RISC-V Maintainers

Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Signed-off-by: Michael Clark --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bc2d3a4..17af5b4 100644 ---

Re: [Qemu-devel] [PATCH v5 1/4] vhost: remove assertion to prevent crash

Hi Igor, > -Original Message- > From: Igor Mammedov [mailto:imamm...@redhat.com] > Sent: Wednesday, January 10, 2018 9:31 PM > To: Zhoujian (jay) > Cc: qemu-devel@nongnu.org; Huangweidong (C) ; > m...@redhat.com; wangxin (U)

Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1515628000-93285-1-git-send-email-...@sifive.com Subject: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2 === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1

Re: [Qemu-devel] [PATCH] 9pfs: drop v9fs_register_transport()

On Mon, 8 Jan 2018, Greg Kurz wrote: > Stefano, can you ack/nack this one ? > > On Wed, 20 Dec 2017 20:42:54 +0100 > Greg Kurz wrote: > > > No good reasons to do this outside of v9fs_device_realize_common(). > > > > Signed-off-by: Greg Kurz Reviewed-by:

Re: [Qemu-devel] [PATCH v3 1/2] 9pfs: allow PDU to complete without sending a reply

On Mon, 18 Dec 2017, Greg Kurz wrote: > The 9p protocol mostly relies on a request/reply dialog between the > client and the server. A notable exception to this rule is request > cancellation (ie, flush in 9p wording): the server shouldn't send a > reply when the request was flushed. > > This

[Qemu-devel] [PATCHv2] linux-user: Add getcpu() support

Signed-off-by: Samuel Thibault --- Difference from v1: handle failure of put_user_u32 with goto efault; --- linux-user/syscall.c | 16 1 file changed, 16 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index

Re: [Qemu-devel] [PATCH v2] 9pfs: Correctly handle cancelled requests

On Wed, 20 Dec 2017, Greg Kurz wrote: > On Tue, 12 Dec 2017 15:14:06 -0800 (PST) > Stefano Stabellini wrote: > > > On Fri, 8 Dec 2017, Greg Kurz wrote: > > > Cc'ing Stefano using a more appropriate address :) > > > > Thanks Greg for the ping, one comment inline below.

Re: [Qemu-devel] [PATCH v1 2/2] intel-iommu: Extend address width to 48 bits

Hi Yi L, On 12/1/2017 3:29 AM, Liu, Yi L wrote: On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote: From: Prasad Singamsetty The current implementation of Intel IOMMU code only supports 39 bits iova address width. This patch provides

Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/1] spapr: Check SMT based on KVM_CAP_PPC_SMT_POSSIBLE

On Tue, Jan 09, 2018 at 01:48:13PM +0100, Greg Kurz wrote: > On Fri, 5 Jan 2018 22:47:22 -0200 > Jose Ricardo Ziviani wrote: > > > Power9 supports 4 HW threads/core but it's possible to emulate > > doorbells to implement virtual SMT. KVM has the

Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

FYI - I intended these emails to go to the RISC-V Patches but unfortunately had the wrong address on the 'cc. This time around, the patches are in the qemu-devel archives here: - http://lists.nongnu.org/archive/html/qemu-devel/2018-01/threads.html On Thu, Jan 11, 2018 at 12:46 PM, Michael Clark

[Qemu-devel] [PATCH v2 04/21] RISC-V Disassembler

The RISC-V disassembler has no dependencies outside of the 'disas' directory so it can be applied independently. The majority of the disassembler is machine-generated from instruction set metadata: - https://github.com/michaeljclark/riscv-meta Expected checkpatch errors for consistency and

[Qemu-devel] [PATCH v2 19/21] SiFive Freedom E300 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark --- hw/riscv/sifive_e300.c | 232 +

[Qemu-devel] [PATCH v2 20/21] SiFive Freedom U500 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark --- hw/riscv/sifive_u500.c | 338 +

[Qemu-devel] [PATCH v2 15/21] RISC-V Spike Machines

RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V Instruction Set Simulator. The following machines are implemented: - 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1 - 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10 Signed-off-by:

[Qemu-devel] [PATCH v2 08/21] RISC-V TCG Code Generation

TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU RISC-V code generator has complete coverage for the Base ISA v2.2, Privileged ISA v1.9.1 and Privileged ISA v1.10: - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 - RISC-V Instruction Set Manual Volume II:

[Qemu-devel] [PATCH v2 21/21] RISC-V Build Infrastructure

This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'

[Qemu-devel] [PATCH v2 14/21] SiFive RISC-V PLIC Block

The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark --- hw/riscv/sifive_plic.c | 554 +

[Qemu-devel] [PATCH v2 18/21] SiFive RISC-V PRCI Block

Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 107 + include/hw/riscv/sifive_prci.h | 43 + 2

[Qemu-devel] [PATCH v2 16/21] RISC-V VirtIO Machine

RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark --- hw/riscv/virt.c | 364

[Qemu-devel] [PATCH v2 17/21] SiFive RISC-V UART Device

QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in

[Qemu-devel] [PATCH v2 12/21] RISC-V HART Array

Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 insertions(+)

[Qemu-devel] [PATCH v2 10/21] RISC-V Linux User Emulation

Implementation of linux user emulation for RISC-V. Signed-off-by: Michael Clark --- linux-user/elfload.c | 22 +++ linux-user/main.c | 114 +++ linux-user/riscv/syscall_nr.h | 275 +++

[Qemu-devel] [PATCH v2 11/21] RISC-V HTIF Console

HTIF (Host Target Interface) provides console emulation for QEMU. HTIF allows identical copies of BBL (Berkeley Boot Loader) and linux to run on both Spike and QEMU. BBL provides HTIF console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The HTIF interface

[Qemu-devel] [PATCH v2 13/21] SiFive RISC-V CLINT Block

The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Signed-off-by: Michael Clark --- hw/riscv/sifive_clint.c | 312

[Qemu-devel] [PATCH v2 09/21] RISC-V Physical Memory Protection

Implements the physical memory protection extension as specified in Privileged ISA Version 1.10. PMP (Physical Memory Protection) is as-of-yet unused and needs testing. The SiFive verification team have PMP test cases that will be run. Nothing currently depends on PMP support. It would be

[Qemu-devel] [PATCH v2 03/21] RISC-V CPU Core Definition

Add CPU state header, CPU definitions and initialization routines Signed-off-by: Michael Clark --- target/riscv/cpu.c | 391 + target/riscv/cpu.h | 271 +++ target/riscv/cpu_bits.h | 417

[Qemu-devel] [PATCH v2 07/21] RISC-V GDB Stub

GDB Register read and write routines. Signed-off-by: Michael Clark --- target/riscv/gdbstub.c | 59 ++ 1 file changed, 59 insertions(+) create mode 100644 target/riscv/gdbstub.c diff --git a/target/riscv/gdbstub.c

[Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

QEMU RISC-V Emulation Support (RV64GC, RV32GC) This patch series has major clean ups to target/riscv. There may be some feedback that has been missed however the changelog is growing quite large so we have decided to respin the patch series. No new features have been added however a number of

[Qemu-devel] [PATCH v2 05/21] RISC-V CPU Helpers

Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark --- target/riscv/helper.c| 499 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c | 682

[Qemu-devel] [PATCH v2 06/21] RISC-V FPU Support

Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 591 + 2 files changed, 595 insertions(+), 3 deletions(-) create mode 100644

[Qemu-devel] [PATCH v2 02/21] RISC-V ELF Machine Definition

Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson Signed-off-by: Michael Clark --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 ---

[Qemu-devel] [PATCH v2 01/21] RISC-V Maintainers

Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Signed-off-by: Michael Clark --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bc2d3a4..17af5b4 100644 ---

[Qemu-devel] [PATCH v2 2/6] nbd/server: refactor negotiation functions parameters

From: Vladimir Sementsov-Ogievskiy Instead of passing currently negotiating option and its length to many of negotiation functions let's just store them on NBDClient struct to be state-variables of negotiation phase. This unifies semantics of negotiation functions and

[Qemu-devel] [PATCH v2 6/6] nbd/server: structurize option reply sending

From: Vladimir Sementsov-Ogievskiy Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Eric Blake Message-Id: <20171122101958.17065-6-vsement...@virtuozzo.com> Signed-off-by: Eric Blake ---

[Qemu-devel] [PATCH v2 3/6] nbd/server: Better error for NBD_OPT_EXPORT_NAME failure

When a client abruptly disconnects before we've finished reading the name sent with NBD_OPT_EXPORT_NAME, we are better off logging the failure as EIO (we can't communicate with the client), rather than EINVAL (the client sent bogus data). Signed-off-by: Eric Blake ---

[Qemu-devel] [PATCH v2 5/6] nbd/server: Add helper functions for parsing option payload

Rather than making every callsite perform length sanity checks and error reporting, add the helper functions nbd_opt_read() and nbd_opt_drop() that use the length stored in the client struct; also add an assertion that optlen is reduced to zero after each option is handled. Note that the call in

[Qemu-devel] [PATCH v2 1/6] nbd/server: Hoist nbd_reject_length() earlier

No semantic change, but will make it easier for an upcoming patch to refactor code without having to add forward declarations. Signed-off-by: Eric Blake --- nbd/server.c | 56 1 file changed, 28 insertions(+), 28

[Qemu-devel] [PATCH v2 4/6] nbd/server: Add va_list form of nbd_negotiate_send_rep_err()

This will be useful for the next patch. Based on a patch by Vladimir Sementsov-Ogievskiy Signed-off-by: Eric Blake --- nbd/server.c | 24 ++-- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/nbd/server.c b/nbd/server.c index

[Qemu-devel] [PATCH v2 0/6] NBD server refactoring before BLOCK_STATUS

This is my promised revision of Vladimir's v1 posted here: https://lists.gnu.org/archive/html/qemu-devel/2017-11/msg04119.html Sorry for my delay; it was due in part to an embargo while dealing with 2 bounds-check CVEs in the NBD code that I discovered while reviewing his v1 (fixed in time for

[Qemu-devel] [PULL 2/2] nbd: rename nbd_option and nbd_opt_reply

From: Vladimir Sementsov-Ogievskiy Rename nbd_option and nbd_opt_reply to NBDOption and NBDOptionReply to correspond to Qemu coding style and other structures here. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Eric Blake

[Qemu-devel] [PULL 1/2] nbd/server: add additional assert to nbd_export_put

From: Vladimir Sementsov-Ogievskiy This place is not obvious, nbd_export_close may theoretically reduce refcount to 0. It may happen if someone calls nbd_export_put on named export not through nbd_export_set_name when refcount is 1. Signed-off-by: Vladimir

[Qemu-devel] [PULL 0/2] nbd patches for 10 Jan

The following changes since commit 3cee4db661ab9c0fce7937b3bbfa188a1845f31f: Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-01-08' into staging (2018-01-09 15:22:47 +) are available in the Git repository at: git://repo.or.cz/qemu/ericb.git tags/pull-nbd-2018-01-10 for

[Qemu-devel] [Bug 1175089] Re: Crash why dragon fly 3.4.1

Triaging old bug tickets... can you still reproduce this issue with the latest version of QEMU? Or could we close this ticket nowadays? ** Changed in: qemu Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to

[Qemu-devel] [Bug 1163474] Re: qemu mount usb permission denied

Triaging old bug tickets ... Sounds like this was rather a problem with your distro / udev than with qemu. In case you still have the problem, please report it to the Debian bug tracker first. ** Changed in: qemu Status: New => Invalid -- You received this bug notification because you

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