On 2018年02月22日 17:04, Thomas Huth wrote:
The functions are only used in this single .c file, so there is
no need to put all this code in a header that is included from
multiple places.
Signed-off-by: Thomas Huth
---
hw/net/net_rx_pkt.c| 44
On 2018年02月21日 18:18, Thomas Huth wrote:
"-net" is a legacy option that often causes confusion and
misconfigurations for the users, since most people are not aware
of the underlying "vlan" (i.e. hub) concept that is used for this
parameter. The prefered way of configuring your network stack is
On Mon, 01/22 23:07, Max Reitz wrote:
> @@ -101,7 +105,7 @@ static BlockErrorAction
> mirror_error_action(MirrorBlockJob *s, bool read,
> }
> }
>
> -static void mirror_iteration_done(MirrorOp *op, int ret)
> +static void coroutine_fn mirror_iteration_done(MirrorOp *op, int ret)
> {
>
On Sat, Feb 17, 2018 at 7:32 PM, Philippe Mathieu-Daudé wrote:
> [Me]
>> +#define DEBUG_SII9022 0
>> +
>> +#define DPRINTF(fmt, ...) \
>> +do { \
>> +if (DEBUG_SII9022) { \
>> +printf("sii9022: " fmt, ## __VA_ARGS__); \
>> +} \
>> +} while (0)
From: Dave Airlie
Due to a kernel bug we can never increase the size of capability
set 1, so introduce a new capability set in parallel, old userspace
will continue to use the old set, new userspace will start using
the new one when it detects a fixed kernel.
v2: don't use a
The following changes since commit 0a773d55ac76c5aa89ed9187a3bc5af8c5c2a6d0:
maintainers: Add myself as a OpenBSD maintainer (2018-02-23 12:05:07 +)
are available in the git repository at:
git://git.kraxel.org/qemu tags/vga-20180227-pull-request
for you to fetch changes up to
v8:
- rebased on the master
v7:
- rebased on the master
v2 ... v6:
- delete the "used_memslots" global variable, and add it
for vhost-user and vhost-kernel separately
- refine the function, commit log
- used_memslots refactoring
Jay Zhou (2):
vhost: fix memslot limit check
vhost:
Since used_memslots will be updated to the actual value after
registering memory listener for the first time, move the
memslots limit checking to the right place.
Reviewed-by: Igor Mammedov
Signed-off-by: Jay Zhou
---
hw/virtio/vhost.c | 19
Used_memslots is shared by vhost kernel and user, it is equal to
dev->mem->nregions, which is correct for vhost kernel, but not for
vhost user, the latter one uses memory regions that have file
descriptor. E.g. a VM has a vhost-user NIC and 8(vhost user memslot
upper limit) memory slots, it will
dev could be NULL if the PCI device can not be found due to some
reasons, so we must not dereference the pointer in this case.
Signed-off-by: Thomas Huth
---
tests/libqos/virtio-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Gonglei
I posted the RFC verion a few months ago for DPDK
vhost-crypto implmention, and now it's time to send
the formal version. Because we need an user space scheme
for better performance.
The vhost user crypto server side patches had been
sent to DPDK
From: Gonglei
Signed-off-by: Gonglei
---
backends/cryptodev-vhost-user.c | 4
include/sysemu/cryptodev-vhost-user.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/backends/cryptodev-vhost-user.c
From: Gonglei
Introduce two vhost-user meassges: VHOST_USER_CREATE_CRYPTO_SESSION
and VHOST_USER_CLOSE_CRYPTO_SESSION. At this point, the QEMU side
support crypto operation in cryptodev host-user backend.
Signed-off-by: Gonglei
Signed-off-by:
From: Gonglei
Usage:
-chardev socket,id=charcrypto0,path=/path/to/your/socket
-object cryptodev-vhost-user,id=cryptodev0,chardev=charcrypto0
-device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0
Signed-off-by: Gonglei
Signed-off-by:
From: Gonglei
Impliment the vhost-crypto's funtions, such as startup,
stop and notification etc. Introduce an enum
QCryptoCryptoDevBackendOptionsType in order to
identify the cryptodev vhost backend is vhost-user
or vhost-kernel-module (If exist).
At this point, the
** Also affects: gentoo
Importance: Undecided
Status: New
** No longer affects: gentoo
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1750899
Title:
Mouse cursor sometimes can't pass the
The appended adds assertions to make sure we do not longjmp with page
locks held. Some notes:
- user-mode has nothing to check, since page_locks are !user-mode only.
- The checks only apply to page collections, since these have relatively
complex callers.
- Some simple page_lock/unlock
Use mmap_lock in user-mode to protect TCG state and the page
descriptors.
In !user-mode, each vCPU has its own TCG state, so no locks
needed. Per-page locks are used to protect the page descriptors.
Per-TB locks are used in both modes to protect TB jumps.
Some notes:
- tb_lock is removed from
The acquisition of tb_lock was added when the async tlb_flush
was introduced in e3b9ca810 ("cputlb: introduce tlb_flush_* async work.")
tb_lock was there to allow us to do memset() on the tb_jmp_cache's.
However, since f3ced3c5928 ("tcg: consistently access cpu->tb_jmp_cache
atomically") all
Use the recently-gained QHT feature of returning the matching TB if it
already exists. This allows us to get rid of the lookup we perform
right after acquiring tb_lock.
Suggested-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
accel/tcg/cpu-exec.c
This applies to both user-mode and !user-mode emulation.
Instead of relying on a global lock, protect the list of incoming
jumps with tb->jmp_lock. This lock also protects tb->cflags,
so update all tb->cflags readers outside tb->jmp_lock to use
atomic reads via tb_cflags().
In order to find the
This commit does several things, but to avoid churn I merged them all
into the same commit. To wit:
- Use uintptr_t instead of TranslationBlock * for the list of TBs in a page.
Just like we did in (c37e6d7e "tcg: Use uintptr_t type for
jmp_list_{next|first} fields of TB"), the rationale is
Groundwork for supporting parallel TCG generation.
Instead of using a global lock (tb_lock) to protect changes
to pages, use fine-grained, per-page locks in !user-mode.
User-mode stays with mmap_lock.
Sometimes changes need to happen atomically on more than one
page (e.g. when a TB that spans
Groundwork for supporting parallel TCG generation.
We never remove entries from the radix tree, so we can use cmpxchg
to implement lockless insertions.
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 24 ++--
This paves the way for enabling scalable parallel generation of TCG code.
Instead of tracking TBs with a single binary search tree (BST), use a
BST for each TCG region, protecting it with a lock. This is as scalable
as it gets, since each TCG thread operates on a separate region.
The core of
tb_lock was needed when the function did retranslation. However,
since fca8a500d519 ("tcg: Save insn data and use it in
cpu_restore_state_from_tb") we don't do retranslation.
Get rid of the comment.
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 4 +---
1 file
The meaning of "existing" is now changed to "matches in hash and
ht->cmp result". This is saner than just checking the pointer value.
Note that we now return NULL on insertion success, or the existing
pointer on failure. We can do this because NULL pointers are not
allowed to be inserted in QHT.
qht_lookup now uses the default cmp function. qht_lookup_custom is defined
to retain the old behaviour, that is a cmp function is explicitly provided.
qht_insert will gain use of the default cmp in the next patch.
Signed-off-by: Emilio G. Cota
---
accel/tcg/cpu-exec.c | 4
Thereby making it per-TCGContext. Once we remove tb_lock, this will
avoid an atomic increment every time a TB is invalidated.
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 5 +++--
include/exec/tb-context.h | 1 -
tcg/tcg.c | 14 ++
This greatly simplifies next commit's diff.
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 77 ---
1 file changed, 39 insertions(+), 38 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
So that we pass a same-page range to tb_invalidate_phys_page_range,
instead of always passing an end address that could be on a different
page.
As discussed with Peter Maydell on the list [1], tb_invalidate_phys_page_range
doesn't actually do much with 'end', which explains why we have never
hit
With this set we finally remove tb_lock. The performance gains
when booting a guest are compelling at low core counts. However,
beyond 8 cores performance doesn't improve due to unrelated
contention--see results in the last patch of the series
("tcg: remove tb_lock").
I have another series that
Groundwork for supporting parallel TCG generation.
Move the hole to the end of the struct, so that a u32
field can be added there without bloating the struct.
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
> -Original Message-
> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> Sent: Monday, February 26, 2018 10:43 PM
> To: Igor Mammedov; Tan, Jianfeng
> Cc: Jason Wang; Maxime Coquelin; qemu-devel@nongnu.org; Michael S .
> Tsirkin
> Subject: Re: [Qemu-devel] [RFC] exec: eliminate ram
> -Original Message-
> From: Igor Mammedov [mailto:imamm...@redhat.com]
> Sent: Monday, February 26, 2018 8:56 PM
> To: Tan, Jianfeng
> Cc: Paolo Bonzini; Jason Wang; Maxime Coquelin; qemu-devel@nongnu.org;
> Michael S . Tsirkin
> Subject: Re: [Qemu-devel] [RFC] exec: eliminate ram
On Mon, Feb 26, 2018 at 10:54:11AM +0200, Gal Hammer wrote:
> Hi Peter,
>
> On Fri, Feb 2, 2018 at 12:11 PM, Peter Xu wrote:
> > On Thu, Feb 01, 2018 at 02:48:20PM +0200, Michael S. Tsirkin wrote:
> >
> > [...]
> >
> >> > > > > PFN is GPA>>12. Do you have more than 1<<44
On Fri, Feb 23, 2018 at 3:22 PM, Francisco Iglesias
wrote:
> Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
> chip selects are enabled (e.g reading/writing with stripe).
>
> Signed-off-by: Francisco Iglesias
On Thu, Feb 15, 2018 at 2:05 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/sd/sd.c | 27 ---
> hw/sd/trace-events | 1
When doing drive mirror to a low speed shared storage, if there was heavy
BLK IO write workload in VM after the 'ready' event, drive mirror block job
can't be canceled immediately, it would keep running until the heavy BLK IO
workload stopped in the VM.
Libvirt depends on the current
Hi Folks,
Just a quick update regarding the process of submitting the RISC-V QEMU port
upstream for inclusion in the QEMU 2.12 release this coming April.
We’ve just submitted our first pull request after receiving positive feedback
from the v6 patch series submitted last week. We recently
On Mon, Feb 26, 2018 at 12:35:31PM +0800, Wei Wang wrote:
> On 02/09/2018 08:15 PM, Dr. David Alan Gilbert wrote:
> > * Wei Wang (wei.w.w...@intel.com) wrote:
> > > This patch adds a timer to limit the time that host waits for the free
> > > page hints reported by the guest. Users can specify the
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
The following changes since commit 0a773d55ac76c5aa89ed9187a3bc5af8c5c2a6d0:
maintainers: Add myself as a OpenBSD maintainer (2018-02-23 12:05:07 +)
are available in the git repository at:
https://github.com/riscv/riscv-qemu.git
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 1519683480-33201-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v7 00/23] RISC-V QEMU Port Submission
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
On 02/26/2018 04:57 PM, Eric Blake wrote:
Commit f0df84c6 added watchdog-set-action in the main qapi-schema.json,
but it belongs better in qapi/run-state.json alongside the definition
of WatchdogAction.
I'm adding:
The command was written prior to commit 0e201d34 creating the latter
file,
On 02/26/2018 04:24 PM, Michael Clark wrote:
I've pushed a signed tag which includes the cover letter for the pull
request.
https://github.com/riscv/riscv-qemu/releases/tag/riscv-qemu-upstream-v7
Apologies. I'm not exactly sure how to format a pull request email.
I use:
$ git request-pull
On 02/26/2018 04:18 PM, Michael Clark wrote:
This adds RISC-V into the build system enabling the following targets:
- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user
This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and
Commit f0df84c6 added watchdog-set-action in the main qapi-schema.json,
but it belongs better in qapi/run-state.json alongside the definition
of WatchdogAction.
Signed-off-by: Eric Blake
---
Based on my review of 24/29, I'm inserting this patch right before
rebasing that one
Michael, can you please apply this patch to stable?
git cherry-pick 302705876
Regards,
Stefan
The flags of the CMD_INIT control channel command were not
initialized properly. Fix this and set to 0.
Signed-off-by: Stefan Berger
Reviewed-by: Marc-André Lureau
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1519683480-33201-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v7 00/23] RISC-V QEMU Port Submission
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
On 02/23/2018 11:41 AM, Markus Armbruster wrote:
+++ b/Makefile
@@ -92,10 +92,70 @@ include $(SRC_PATH)/rules.mak
GENERATED_FILES = qemu-version.h config-host.h qemu-options.def
GENERATED_FILES += qapi-builtin-types.h qapi-builtin-types.c
GENERATED_FILES += qapi-types.h qapi-types.c
I've pushed a signed tag which includes the cover letter for the pull
request.
https://github.com/riscv/riscv-qemu/releases/tag/riscv-qemu-upstream-v7
Apologies. I'm not exactly sure how to format a pull request email.
On Tue, Feb 27, 2018 at 11:17 AM, Michael Clark wrote:
>
This adds RISC-V into the build system enabling the following targets:
- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user
This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
This provides a RISC-V Board compatible with the the SiFive U500 SDK.
The following machine is implemented:
- 'sifive_u500'; CLINT, PLIC, UART, device-tree
Acked-by: Richard Henderson
Signed-off-by: Michael Clark
---
hw/riscv/sifive_u500.c
QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.
The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:
- 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10
Acked-by:
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Acked-by: Richard Henderson
Signed-off-by: Michael Clark
---
hw/riscv/virt.c
Test finisher memory mapped device used to exit simulation.
Acked-by: Richard Henderson
Signed-off-by: Michael Clark
---
hw/riscv/sifive_test.c | 93 ++
include/hw/riscv/sifive_test.h | 42
This provides a RISC-V Board compatible with the the SiFive E300 SDK.
The following machine is implemented:
- 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
Acked-by: Richard Henderson
Signed-off-by: Michael Clark
---
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Acked-by: Richard Henderson
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 254
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Acked-by: Richard Henderson
Signed-off-by: Michael Clark
---
hw/riscv/sifive_prci.c | 89 ++
TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
RISC-V code generator has complete coverage for the Base ISA v2.2,
Privileged ISA v1.9.1 and Privileged ISA v1.10:
- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II:
Implementation of linux user emulation for RISC-V.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
linux-user/elfload.c | 22 +++
linux-user/main.c | 99 +
linux-user/riscv/syscall_nr.h
Implements the physical memory protection extension as specified in
Privileged ISA Version 1.10.
PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
The SiFive verification team have PMP test cases that will be run.
Nothing currently depends on PMP support. It would be
The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.
Acked-by: Richard Henderson
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 505
The RISC-V HTIF (Host Target Interface) console device requires access
to the symbol table to locate the 'tohost' and 'fromhost' symbols.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
hw/core/loader.c | 18 --
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF
allows identical copies of BBL (Berkeley Boot Loader) and linux to run
on both Spike and QEMU. BBL provides HTIF console access via the
SBI (Supervisor Binary Interface) and the linux kernel SBI console.
The HTIT chardev
Holds the state of a heterogenous array of RISC-V hardware threads.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
hw/riscv/riscv_hart.c | 89 +++
include/hw/riscv/riscv_hart.h | 39
Privileged control and status register helpers and page fault handling.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/helper.c| 503
target/riscv/helper.h| 78 ++
Helper routines for FPU instructions and NaN definitions.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
fpu/softfloat-specialize.h | 7 +-
target/riscv/fpu_helper.c | 373 +
2 files
The RISC-V disassembler has no dependencies outside of the 'disas'
directory so it can be applied independently. The majority of the
disassembler is machine-generated from instruction set metadata:
- https://github.com/michaeljclark/riscv-meta
Expected checkpatch errors for consistency and
GDB Register read and write routines.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/gdbstub.c | 62 ++
1 file changed, 62 insertions(+)
create mode 100644
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Michael Clark
---
MAINTAINERS | 11
QEMU RISC-V Emulation Support (RV64GC, RV32GC)
With this reelase we have contacted all contributors and have received
agreement to re-license their work as GPLv2+. This release also updates
linux-user/riscv/termbits.h which should fix S390 builds. The spike_v1.9
machine has been renamed to
Define RISC-V ELF machine EM_RISCV 243
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Michael Clark
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h
Add CPU state header, CPU definitions and initialization routines
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 390 +
target/riscv/cpu.h | 275
Closing according to comment #2.
** Changed in: qemu
Status: New => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1428958
Title:
random IO errors / data corruption in VMs
Triaging old bug tickets... can you still reproduce this issue with the
latest version of QEMU? Or could we close this ticket nowadays?
** Changed in: qemu
Status: New => Incomplete
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to
Triaging old bug tickets... can you still reproduce this issue with the
latest version of QEMU? Or could we close this ticket nowadays? Can you
provide a binary to reproduce this issue?
** Changed in: qemu
Status: New => Incomplete
--
You received this bug notification because you are a
On Mon, 26 Feb 2018 09:35:51 +0100
Gerd Hoffmann wrote:
> On Fri, Feb 23, 2018 at 10:05:17AM +0100, Gerd Hoffmann wrote:
> > > Hi Gerd,
> > >
> > > It's a little bit concerning that the only way we can test the
> > > region-based display support is with proprietary drivers
The normal gdb definition of the XER registers is only 32 bit,
and that's what the current version of power64-core.xml also
says (seems copied from gdb's). But qemu's idea of the XER register
is target_ulong (in CPUPPCState, ppc_gdb_register_len and
ppc_cpu_gdb_read_register)
That mismatch leads
Hi Eric,
On Mon, Feb 26, 2018 at 5:14 AM, Auger Eric wrote:
> Hi Jintack,
>
> On 21/02/18 05:03, Jintack Lim wrote:
>> Hi,
>>
>> I'm using vhost with the virtual intel-iommu, and this page[1] shows
>> the QEMU command line example.
>>
>> qemu-system-x86_64 -M
On Fri, Feb 16, 2018 at 01:16:20PM +, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> This message is sent just before the end of postcopy to get the
> client to stop using userfault since we wont respond to any more
> requests. It should close
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: cover.1519647019.git.arei.gong...@huawei.com
Subject: [Qemu-devel] [PATCH v7 0/4]
* Zhangjixiang (jixiang_zh...@h3c.com) wrote:
> From 295640e6f4aa83b843e245bb1af9995be37de84d Mon Sep 17 00:00:00 2001
> From: zhangjixiang
> Date: Sun, 25 Feb 2018 09:47:51 +0800
> Subject: [PATCH] HMP: Initialize err before using
>
> When bdrv_snapshot_delete return
On 02/23/2018 11:20 AM, Markus Armbruster wrote:
Eric Blake writes:
On 02/11/2018 03:35 AM, Markus Armbruster wrote:
Whenever qapi-schema.json changes, we run six programs eleven times to
update eleven files. Similar for qga/qapi-schema.json. This is
silly. Replace the
On 02/26/2018 02:29 PM, Collin L. Walling wrote:
On 02/26/2018 01:48 PM, Cornelia Huck wrote:
On Mon, 26 Feb 2018 11:42:29 +0100
Thomas Huth wrote:
[...]
3 files changed, 66 insertions(+), 4 deletions(-)
+static void s390_ipl_set_boot_menu(S390IPLState *ipl)
+{
+
On 02/26/2018 01:48 PM, Cornelia Huck wrote:
On Mon, 26 Feb 2018 11:42:29 +0100
Thomas Huth wrote:
From: "Collin L. Walling"
Set boot menu options for an s390 guest and store them in
the iplb. These options are set via the QEMU command line
On Mon, 26 Feb 2018 11:42:29 +0100
Thomas Huth wrote:
> From: "Collin L. Walling"
>
> Set boot menu options for an s390 guest and store them in
> the iplb. These options are set via the QEMU command line
> option:
>
> -boot
On 02/26/2018 12:01 PM, Dr. David Alan Gilbert wrote:
> * Wei Huang (w...@redhat.com) wrote:
>> The x86 boot block header currently is generated with a shell script.
>> To better support other CPUs (e.g. aarch64), we convert the script
>> into Makefile. This allows us to 1) support
On 02/26/2018 03:03 AM, Andrew Jones wrote:
> On Fri, Feb 23, 2018 at 04:13:08PM -0600, Wei Huang wrote:
>>
>>
>> On 02/22/2018 03:00 AM, Andrew Jones wrote:
>>> On Wed, Feb 21, 2018 at 10:44:17PM -0600, Wei Huang wrote:
This patch adds migration test support for aarch64. The test code,
This patch moves the auto detection functions for cross compilation from
roms/Makefile to rules.mak. So the functions can be shared among Makefiles
in QEMU.
Signed-off-by: Wei Huang
Reviewed-by: Andrew Jones
---
roms/Makefile | 24 +++-
This patch moves the settings related migration-test from the
migration-test.c file to a seperate header file. It also renames the
x86-a-b-bootblock.s file extension from .s to .S, allowing gcc
pre-processor to include the C-style header file correctly.
Signed-off-by: Wei Huang
This patch adds migration test support for aarch64. The test code, which
implements the same functionality as x86, is booted as a kernel in qemu.
Here are the design choices we make for aarch64:
* We choose this -kernel approach because aarch64 QEMU doesn't provide a
built-in fw like x86
This patchset adds a migration test for aarch64. It leverages
Dave Gilbert's recent patch "tests/migration: Add source to PC boot block"
to create a new test case for aarch64.
V5->V6:
* Add Reviewed-by to patch 1-3
* Add more design notes in patch 4 (aarch64 assembly compilation, bin space)
The x86 boot block header currently is generated with a shell script.
To better support other CPUs (e.g. aarch64), we convert the script
into Makefile. This allows us to 1) support cross-compilation easily,
and 2) avoid creating a script file for every architecture.
Signed-off-by: Wei Huang
* Wei Huang (w...@redhat.com) wrote:
> The x86 boot block header currently is generated with a shell script.
> To better support other CPUs (e.g. aarch64), we convert the script
> into Makefile. This allows us to 1) support cross-compilation easily,
> and 2) avoid creating a script file for every
Fixes an issue where if the tpr is assigned to the array but not a different
value from what is already expected on the vp the code will skip incrementing
the reg_count. In this case its possible that we set an invalid memory section
of the next call for DeliverabilityNotifications that was not
The use of WHvGetExitContextSize will break ABI compatibility if the platform
changes the context size while a qemu compiled executable does not recompile.
To avoid this we now use sizeof and let the platform determine which version
of the struction was passed for ABI compatibility.
The code already is holding the qemu_mutex for the IO thread. We do not need
to additionally take the lock again in this case.
Signed-off-by: Justin Terry (VM)
---
target/i386/whpx-all.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/i386/whpx-all.c
Minor code cleanup. The calls to __debugbreak() are not required and should
no longer be used to prevent unnecessary breaks.
Signed-off-by: Justin Terry (VM)
---
target/i386/whpx-all.c | 12
1 file changed, 12 deletions(-)
diff --git a/target/i386/whpx-all.c
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