[Qemu-devel] [Bug 1185311] Re: could not hot-remove disabled NIC from Win2012 guest by 'devel_del id1'

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1185311 Title: could not

[Qemu-devel] [Bug 1176366] Re: TCPIP not working on qemu 1.4.50 (master)

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1176366 Title: TCPIP not

Re: [Qemu-devel] [PATCH] i386/kvm: add support for KVM_CAP_X86_DISABLE_EXITS

2018-03-24 4:18 GMT+08:00 Eduardo Habkost : > On Fri, Mar 16, 2018 at 07:36:42AM -0700, Wanpeng Li wrote: >> From: Wanpeng Li >> >> This patch adds support for KVM_CAP_X86_DISABLE_EXITS. Provides userspace >> with >> per-VM

Re: [Qemu-devel] [PATCH v6 06/26] RISC-V: Mark ROM read-only after copying in code

On Sat, Mar 24, 2018 at 2:23 PM, Peter Maydell wrote: > On 24 March 2018 at 18:13, Michael Clark wrote: > > The sifive_u machine already marks its ROM readonly. This fixes > > the remaining boards. > > > > Cc: Sagar Karandikar

Re: [Qemu-devel] [PATCH v6 08/26] RISC-V: Make sure rom has space for fdt

On Sat, Mar 24, 2018 at 2:25 PM, Peter Maydell wrote: > On 24 March 2018 at 18:13, Michael Clark wrote: > > Remove a potential buffer overflow (not seen in practice). > > Perhaps cpu_physical_memory_write already has bound checks. > >

Re: [Qemu-devel] [PATCH 00/14] Generalize Dallas/Maxim I2C RTC devices v2

Hi, This series failed docker-build@min-glib build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180324192455.12254-1-mdavidsa...@gmail.com Subject: [Qemu-devel] [PATCH 00/14]

Re: [Qemu-devel] [PATCH 00/14] Generalize Dallas/Maxim I2C RTC devices v2

Hi, This series failed docker-quick@centos6 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180324192455.12254-1-mdavidsa...@gmail.com Subject: [Qemu-devel] [PATCH 00/14]

[Qemu-devel] [PATCH v6 21/26] RISC-V: Remove support for adhoc X_COP interrupt

This is essentially dead-code elimination. Support for more local interrupts will be added in a future revision, as they will be defined in a future version of the Privileged ISA specification. Cc: Sagar Karandikar Cc: Bastian Koppelmann

Re: [Qemu-devel] [PULL 0/5] migration queue

On 23 March 2018 at 20:23, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > The following changes since commit 4c2c1015905fa1d616750dfe024b4c0b35875950: > > Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20180323'

[Qemu-devel] [PATCH 11/14] timer: generalize ds1338

Add class level handling for address space size and control register. Signed-off-by: Michael Davidsaver --- hw/timer/ds-rtc.c | 63 --- 1 file changed, 46 insertions(+), 17 deletions(-) diff --git a/hw/timer/ds-rtc.c

Re: [Qemu-devel] [PATCH v6 06/26] RISC-V: Mark ROM read-only after copying in code

On 24 March 2018 at 18:13, Michael Clark wrote: > The sifive_u machine already marks its ROM readonly. This fixes > the remaining boards. > > Cc: Sagar Karandikar > Cc: Bastian Koppelmann > Signed-off-by: Michael Clark

Re: [Qemu-devel] [PATCH v6 08/26] RISC-V: Make sure rom has space for fdt

On 24 March 2018 at 18:13, Michael Clark wrote: > Remove a potential buffer overflow (not seen in practice). > Perhaps cpu_physical_memory_write already has bound checks. cpu_physical_memory_write() writes to the guest address space, so it won't overflow. If you ask it to write

[Qemu-devel] [PATCH v1] RISC-V: RISC-V TCG backend work in progress

This patch adds an experimental RISC-V TCG backend. We have been dogfooding the RISC-V QEMU front-end with Fedora to develop a RISC-V TCG backend. The RISC-V TCG backend can be built inside of the QEMU RISC-V 'virt' machine using the Fedora stage 4 disk image: -

[Qemu-devel] [PATCH 03/14] timer: ds1338 persist 12-hour mode selection

Need to save HOUR[HOUR12] bit to keep track of guest selection of 12-hour mode. Write through current time registers to achieve this. Will be overwritten by the next read/latch. Signed-off-by: Michael Davidsaver --- hw/timer/ds1338.c | 4 +--- 1 file changed, 1

[Qemu-devel] [PATCH v6 26/26] RISC-V: Workaround for critical mstatus.FS MTTCG bug

This change is a workaround for a bug where mstatus.FS is not correctly reporting dirty when MTTCG and SMP are enabled which results in the floating point register file not being saved during context switches. This a critical bug for RISC-V in QEMU as it results in floating point register file

[Qemu-devel] [PATCH v6 20/26] RISC-V: No traps on writes to misa, minstret, mcycle

These fields are marked WARL in the specification so illegal writes are silently dropped. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt ---

Re: [Qemu-devel] [PATCH v6 06/26] RISC-V: Mark ROM read-only after copying in code

On Sat, Mar 24, 2018 at 12:45 PM, Michael Clark wrote: > > > On Sat, Mar 24, 2018 at 11:13 AM, Michael Clark wrote: > >> The sifive_u machine already marks its ROM readonly. This fixes >> the remaining boards. >> >> Cc: Sagar Karandikar

[Qemu-devel] [PATCH 13/14] timer: ds-rtc model ds1375

differences from ds1338 * Has alarms (not modeled) * different control register (not modeled) * smaller address space (0x20 vs. 0x40) Signed-off-by: Michael Davidsaver --- hw/timer/ds-rtc.c | 30 -- 1 file changed, 28 insertions(+), 2

[Qemu-devel] [PATCH 07/14] timer: ds1338 fix wday_offset handling

Correctly handle different real weekday in guest and host timezones. Allow guest to use any day as start of week (day 1). eg. Monday instead of Sunday. Signed-off-by: Michael Davidsaver --- hw/timer/ds1338.c | 24 1 file changed, 16

[Qemu-devel] [PATCH 01/14] tests: more thorough tests of ds1338

Test current time and set+get round trip. Separate current time test from set/get tests to avoid test order issues. Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 4 ++ tests/ds-rtc-common.h | 67 +

Re: [Qemu-devel] [PATCH v6 06/26] RISC-V: Mark ROM read-only after copying in code

On Sat, Mar 24, 2018 at 11:13 AM, Michael Clark wrote: > The sifive_u machine already marks its ROM readonly. This fixes > the remaining boards. > > Cc: Sagar Karandikar > Cc: Bastian Koppelmann > Signed-off-by: Michael

Re: [Qemu-devel] [PATCH v6 26/26] RISC-V: Workaround for critical mstatus.FS MTTCG bug

On Sat, Mar 24, 2018 at 11:13:40AM -0700, Michael Clark wrote: > This change is a workaround for a bug where mstatus.FS > is not correctly reporting dirty when MTTCG and SMP are > enabled which results in the floating point register file > not being saved during context switches. This a critical >

Re: [Qemu-devel] [PATCH 2/5] tests: more thorough test of ds1338

> On 02/20/2018 09:44 AM, Michael Davidsaver wrote: >> On 02/18/2018 11:39 PM, Thomas Huth wrote: ... >> That magic (together with patch 1/5) is IMHO a little bit ugly. I've hit >> the same problem with the m48t59 test recently, and I solved it by >> moving the qtest_start() and qtest_end() calls

Re: [Qemu-devel] [PATCH v6 10/26] RISC-V: Improve page table walker spec compliance

On Sat, Mar 24, 2018 at 11:13 AM, Michael Clark wrote: > - Inline PTE_TABLE check for better readability > - Improve readibility of User page U mode and SUM test > - Disallow non U mode from fetching from User pages > - Add reserved PTE flag check: W or W|X > - Add misaligned

[Qemu-devel] [PATCH 10/14] timer: rename file ds1338.c -> ds-rtc.c

Signed-off-by: Michael Davidsaver --- default-configs/arm-softmmu.mak | 2 +- hw/timer/Makefile.objs | 2 +- hw/timer/{ds1338.c => ds-rtc.c} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename hw/timer/{ds1338.c => ds-rtc.c} (100%) diff --git

[Qemu-devel] [PATCH 04/14] timer: ds1338 clarify HOUR handling

Simplify and comment the translation between registers and struct tm. Signed-off-by: Michael Davidsaver --- hw/timer/ds1338.c | 35 +-- 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/hw/timer/ds1338.c b/hw/timer/ds1338.c

[Qemu-devel] [PATCH 09/14] timer: rename ds1338 -> dsrtc

Prepare to generalize with a more generic name. Keep device name and vmstate name "ds1338" for compatibility. Signed-off-by: Michael Davidsaver --- hw/timer/ds1338.c | 74 +++ 1 file changed, 37 insertions(+), 37

Re: [Qemu-devel] [PATCH for-2.12] qemu-pr-helper: Actually allow users to specify pidfile

On 03/24/2018 12:14 AM, Michal Privoznik wrote: Due to wrong specification of arguments to getopt_long() any attempt to set pidfile resulted in: 1) the default to be leaked 2) the @pidfile variable to be set to NULL (because optarg is NULL without this patch). Broken since the introduction in

[Qemu-devel] [PATCH 02/14] timer: ds1338 use registerfields.h

Use names for registers and bits except for R_CTRL which will be dealt with later, and isn't modeled anyway. Signed-off-by: Michael Davidsaver --- hw/timer/ds1338.c | 84 ++- 1 file changed, 58 insertions(+), 26

[Qemu-devel] [PATCH 06/14] tests: ds-rtc test 12 hour mode

Signed-off-by: Michael Davidsaver --- tests/ds-rtc-set-test.c | 52 + 1 file changed, 52 insertions(+) diff --git a/tests/ds-rtc-set-test.c b/tests/ds-rtc-set-test.c index 35e1a36281..c48406ee2c 100644 ---

Re: [Qemu-devel] [PATCH PULL 0/8] RDMA queue

On 23 March 2018 at 15:52, Marcel Apfelbaum wrote: > The following changes since commit 4c2c1015905fa1d616750dfe024b4c0b35875950: > > Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20180323' into > staging (2018-03-23 10:20:54 +) > > are available in the

[Qemu-devel] [PATCH 08/14] tests: ds-rtc test wday offset

Signed-off-by: Michael Davidsaver --- tests/ds-rtc-common.h | 10 +++--- tests/ds-rtc-current-test.c | 9 - tests/ds-rtc-set-test.c | 6 -- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/tests/ds-rtc-common.h

[Qemu-devel] [PATCH 12/14] timer: ds-rtc handle CENTURY bit

Signed-off-by: Michael Davidsaver --- hw/timer/ds-rtc.c | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/hw/timer/ds-rtc.c b/hw/timer/ds-rtc.c index 2df1bce3f8..5a4df1b115 100644 --- a/hw/timer/ds-rtc.c +++ b/hw/timer/ds-rtc.c @@

[Qemu-devel] [PATCH 05/14] timer: ds1338 change write handling

instead of a read-modify-write, do direct translation of device registers to struct tm members. This new ds1338_update() is the reverse of the existing capture_current_time(). Simplifies later handling of CENTURY bit in similar Dallas RTC chips. Signed-off-by: Michael Davidsaver

Re: [Qemu-devel] [PATCH v6 26/26] RISC-V: Workaround for critical mstatus.FS MTTCG bug

On Sat, Mar 24, 2018 at 11:13 AM, Michael Clark wrote: > This change is a workaround for a bug where mstatus.FS > is not correctly reporting dirty when MTTCG and SMP are > enabled which results in the floating point register file > not being saved during context switches. This a

[Qemu-devel] [PATCH 14/14] tests: drop ds1338-test

redundant to ds-rtc-*-test.c Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 2 -- tests/ds1338-test.c| 75 -- 2 files changed, 77 deletions(-) delete mode 100644 tests/ds1338-test.c diff --git

[Qemu-devel] [PATCH 00/14] Generalize Dallas/Maxim I2C RTC devices v2

This series generalizes the ds1338 model to also support the ds1375. As previously, only the time of day registers are modeled. This series is largely a do-over wrt. my previous series. This time I started with incremental changes from the existing ds1338 model, and only add support for the

Re: [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5

On Sat, Mar 24, 2018 at 11:54 AM, Michael Clark wrote: > Hi Peter, > > I did actually have the full `riscv-qemu-2.12-fixes-v5` tag in the second > PR. See below. > > It was the v4 pull request prior to this where I made the mistake of not > including the series version in the

Re: [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5

Hi Peter, I did actually have the full `riscv-qemu-2.12-fixes-v5` tag in the second PR. See below. It was the v4 pull request prior to this where I made the mistake of not including the series version in the tag. I had since dropped the riscv_isa_string and rcu_read_lock patches so deleted the

Re: [Qemu-devel] [PULL 00/25] RISC-V Post-merge spec conformance and cleanup

On Fri, Mar 23, 2018 at 3:20 AM, Peter Maydell wrote: > On 20 March 2018 at 22:25, Michael Clark wrote: > > -BEGIN PGP SIGNED MESSAGE- > > Hash: SHA1 > > > > The following changes since commit f1a63fcfcd92c88be8942b5ae71aef > 9749a4f135: > > >

Re: [Qemu-devel] [PATCH] ccid-card: include libcacard.h only

On 03/24/2018 12:01 PM, Marc-André Lureau wrote: > Hi > > On Sat, Mar 24, 2018 at 6:13 AM, Michal Privoznik wrote: >> When trying to build with latest libcacard-2.5.1, I hit the >> following error: >> >> In file included from hw/usb/ccid-card-passthru.c:12:0: >>

[Qemu-devel] [PATCH v6 08/26] RISC-V: Make sure rom has space for fdt

Remove a potential buffer overflow (not seen in practice). Perhaps cpu_physical_memory_write already has bound checks. This change however makes space for the maximum device tree size and adds an explicit bounds check and error message. It doesn't trigger, but it may help in the future if the

[Qemu-devel] [PATCH v6 10/26] RISC-V: Improve page table walker spec compliance

- Inline PTE_TABLE check for better readability - Improve readibility of User page U mode and SUM test - Disallow non U mode from fetching from User pages - Add reserved PTE flag check: W or W|X - Add misaligned PPN check - Set READ flag for PTE X flag if mstatus.mxr is in effect - Change access

[Qemu-devel] [PATCH v6 06/26] RISC-V: Mark ROM read-only after copying in code

The sifive_u machine already marks its ROM readonly. This fixes the remaining boards. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt ---

[Qemu-devel] [PATCH v6 19/26] RISC-V: vectored traps are optional

Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by:

[Qemu-devel] [PATCH v6 23/26] RISC-V: Clear mtval/stval on exceptions without info

mtval/stval must be set on all exceptions but zero is a legal value if there is no exception specific info. Placing the instruction bytes for illegal instruction exceptions in mtval/stval is an optional feature and is currently not supported by QEMU RISC-V. Cc: Sagar Karandikar

[Qemu-devel] [PATCH v6 11/26] RISC-V: Update E order and I extension order

Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I

[Qemu-devel] [PATCH v6 14/26] RISC-V: Use memory_region_is_ram in pte update

After reading cpu_physical_memory_write and friends, it seems that memory_region_is_ram is a more appropriate interface, and matches the intent of the code that is calling it. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by:

[Qemu-devel] [PATCH v6 00/26] RISC-V: Fixes and cleanups for QEMU 2.12

This is a series of bug fixes and code cleanups that we would like to get in before the QEMU 2.12 release. We are respinning v6 of this series to include two new bug fixes. These changes are present in the downstream riscv.org riscv-all branch: -

[Qemu-devel] [PATCH v6 16/26] RISC-V: Hardwire satp to 0 for no-mmu case

satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and

[Qemu-devel] [PATCH v6 24/26] RISC-V: Remove erroneous comment from translate.c

Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Palmer Dabbelt Signed-off-by: Michael Clark --- target/riscv/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git

[Qemu-devel] [PATCH v6 18/26] RISC-V: riscv-qemu port supports sv39 and sv48

Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Qemu-devel] [PATCH v6 25/26] RISC-V: Fix incorrect disassembly for addiw

This fixes a bug in the disassembler constraints used to lift instructions into pseudo-instructions, whereby addiw instructions are always lifted to sext.w instead of just lifting addiw with a zero immediate. An associated fix has been made to the metadata used to machine generate the

Re: [Qemu-devel] [PULL 0/4] QAPI patches for 2018-03-23, for 2.12-rc1

On 23 March 2018 at 17:37, Eric Blake wrote: > The following changes since commit 4c2c1015905fa1d616750dfe024b4c0b35875950: > > Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20180323' into > staging (2018-03-23 10:20:54 +) > > are available in the Git

Re: [Qemu-devel] [PATCH] qemu-pr-helper: Actually allow users to specify pidfile

On 03/24/2018 12:14 AM, Michal Privoznik wrote: Due to wrong specification of arguments to getopt_long() any attempt to set pidfile resulted in: 1) the default to be leaked 2) the @pidfile variable to be set to NULL (because optarg is NULL without this patch). Broken in introduction with

Re: [Qemu-devel] [PATCH] ccid-card: include libcacard.h only

Hi On Sat, Mar 24, 2018 at 1:40 PM, Michal Privoznik wrote: > On 03/24/2018 12:01 PM, Marc-André Lureau wrote: >> Hi >> >> On Sat, Mar 24, 2018 at 6:13 AM, Michal Privoznik >> wrote: >>> When trying to build with latest libcacard-2.5.1, I hit the >>>

Re: [Qemu-devel] [PATCH 1/2] hw/sysbus.h: New sysbus_init_child() helper function

Hi, On 02/20/2018 10:23 AM, Igor Mammedov wrote: > On Tue, 20 Feb 2018 13:13:49 +0100 > Paolo Bonzini wrote: > >> On 16/02/2018 18:40, Philippe Mathieu-Daudé wrote: >>> we can keep object_initialize() when no parent, >>> and add object_initialize_child(, const char

Re: [Qemu-devel] [PATCH] monitor: fix expected qmp_capabilities error description regression

On 03/23/2018 08:41 PM, Peter Xu wrote: There have been quite a few patch ideas across multiple threads related to OOB fallout. Hopefully I can keep straight which patches are intended for 2.12 (anything that fixes a bug, like this one, is a good candidate, I'll mark patches with "for-2.12"

Re: [Qemu-devel] [PATCH] ccid-card: include libcacard.h only

Hi On Sat, Mar 24, 2018 at 6:13 AM, Michal Privoznik wrote: > When trying to build with latest libcacard-2.5.1, I hit the > following error: > > In file included from hw/usb/ccid-card-passthru.c:12:0: > /usr/include/cacard/vscard_common.h:26:2: error: #warning "Only > can

[Qemu-devel] [PATCH for-2.12] target/hppa: Include priv level in user-only iaoq

A recent glibc change relies on the fact that the priv level in the iaoq must be 3, and computes an address based on that. QEMU had been ignoring the priv level for user-only, which produced an incorrect address. Reported-by: John David Anglin Signed-off-by: Richard

Re: [Qemu-devel] [PATCH v2 0/5] coccinelle: re-run scripts from scripts/coccinelle

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180323143202.28879-1-lviv...@redhat.com Subject: [Qemu-devel] [PATCH v2 0/5] coccinelle: re-run scripts from scripts/coccinelle === TEST SCRIPT BEGIN === #!/bin/bash

Re: [Qemu-devel] [PATCH] ppc: Fix size of ppc64 xer register (fwd)

On Fri, Feb 23, 2018 at 05:29:56PM +, Michael Matz wrote: > The normal gdb definition of the XER registers is only 32 bit, > and that's what the current version of power64-core.xml also > says (seems copied from gdb's). But qemu's idea of the XER register > is target_ulong (in CPUPPCState,