Re: [Qemu-devel] [RFC 1/3] pci_expander_bridge: reserve enough mcfg space for pxb host

Hi Marcel, Thanks a lot for your feedback. > I don't think we should try to place the MMCFGs before 4G even if there > is enough room. Is better to place them always after 4G. > > "above_4g_mem" PCI hole it is reserved for PCI devices hotplug. We cannot use if for > MMCFGs. What I think we can

Re: [Qemu-devel] [PATCH v2 3/4] sdcard: Implement the UHS-I SWITCH_FUNCTION entries (Spec v3)

On 05/14/2018 12:38 PM, Peter Maydell wrote: > On 9 May 2018 at 07:01, Philippe Mathieu-Daudé wrote: >> [based on a patch from Alistair Francis >> from qemu/xilinx tag xilinx-v2015.2] >> Signed-off-by: Edgar E. Iglesias

Re: [Qemu-devel] [PATCH v2 0/2] error-report: introduce {error|warn}_report_once

On Tue, May 22, 2018 at 11:56:27AM +0800, Peter Xu wrote: > v2: > - for patch 1: replace tabs, add trivial comment [Markus] > (I didn't add much comment otherwise I'll need to duplicate what's >there in error_report()) > - add patch 2 > > Patch 1 introduce the helpers. > > Patch 2 use it

Re: [Qemu-devel] [PATCH 5/8] sdcard: Implement the UHS-I SWITCH_FUNCTION entries (Spec v3)

Hi Peter, On 03/12/2018 10:16 AM, Peter Maydell wrote: > On 12 March 2018 at 13:03, Philippe Mathieu-Daudé wrote: >> On 03/09/2018 06:03 PM, Peter Maydell wrote: >>> I think the spec says that if the guest makes an invalid selection >>> for one function in the group then we must

[Qemu-devel] [PATCH v2 2/2] intel-iommu: start to use error_report_once

Replace existing trace_vtd_err() with error_report_once() then stderr will capture something if any of the error happens, meanwhile we don't suffer from any DDOS. Then remove the trace point. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 34

[Qemu-devel] [PATCH v2 0/2] error-report: introduce {error|warn}_report_once

v2: - for patch 1: replace tabs, add trivial comment [Markus] (I didn't add much comment otherwise I'll need to duplicate what's there in error_report()) - add patch 2 Patch 1 introduce the helpers. Patch 2 use it to replace VT-d trace_vtd_err(). Please review. Thanks. Peter Xu (2):

[Qemu-devel] [PATCH v2 1/2] qemu-error: introduce {error|warn}_report_once

I stole the printk_once() macro. I always wanted to be able to print some error directly if there is a buffer to dump, however we can't use error_report() where the code path can be triggered by DDOS attack. To avoid that, we can introduce a print-once-like function for it. Meanwhile, we also

Re: [Qemu-devel] [PATCH v3] monitor: let cur_mon be per-thread

On Thu, Apr 12, 2018 at 02:11:08PM +0800, Peter Xu wrote: > In the future the monitor iothread may be accessing the cur_mon as > well (via monitor_qmp_dispatch_one()). Before we introduce a real > Out-Of-Band command, let's convert the cur_mon variable to be a > per-thread variable to make sure

Re: [Qemu-devel] [PATCH v6 0/4] qemu-thread: support --enable-debug-mutex

On Wed, Apr 25, 2018 at 10:54:55AM +0800, Peter Xu wrote: > v6: > - rename __QEMU_THREAD_COMMON_H__ to QEMU_THREAD_COMMON_H > - collect r-bs for Emilio Ping. It's fine if we don't really want this, but in case if this falls through the cracks... Regards, -- Peter Xu

Re: [Qemu-devel] [RFC] monitor: turn on Out-Of-Band by default again

On Mon, May 21, 2018 at 09:13:06AM -0500, Eric Blake wrote: > On 05/21/2018 03:42 AM, Peter Xu wrote: > > We turned Out-Of-Band feature of monitors off for 2.12 release. Now we > > try to turn that on again. > > "try to turn" sounds weak, like you aren't sure of this patch. If you > aren't

Re: [Qemu-devel] [PATCH 14/27] iommu: Add IOMMU index concept to IOMMU API

On Mon, May 21, 2018 at 03:03:49PM +0100, Peter Maydell wrote: > If an IOMMU supports mappings that care about the memory > transaction attributes, then it no longer has a unique > address -> output mapping, but more than one. We can > represent these using an IOMMU index, analogous to TCG's > mmu

[Qemu-devel] [PATCH v10 2/5] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D

Add information for cpuid 0x801D leaf. Populate cache topology information for different cache types(Data Cache, Instruction Cache, L2 and L3) supported by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD Family 17h Model for more details. Signed-off-by: Babu Moger

[Qemu-devel] [PATCH v10 0/5] i386: Enable TOPOEXT to support hyperthreading on AMD CPU

This series enables the TOPOEXT feature for AMD CPUs. This is required to support hyperthreading on kvm guests. This addresses the issues reported in these bugs: https://bugzilla.redhat.com/show_bug.cgi?id=1481253 https://bugs.launchpad.net/qemu/+bug/1703506 v10: Based the patches on Eduardo's

[Qemu-devel] [PATCH v10 5/5] i386: Remove generic SMT thread check

Remove generic non-intel check while validating hyperthreading support. Certain AMD CPUs can support hyperthreading now. CPU family with TOPOEXT feature can support hyperthreading now. Signed-off-by: Babu Moger Tested-by: Geoffrey McRae Reviewed-by:

[Qemu-devel] [PATCH v10 4/5] i386: Enable TOPOEXT feature on AMD EPYC CPU

Enable TOPOEXT feature on EPYC CPU. This is required to support hyperthreading on VM guests. Also extend xlevel to 0x801E. Disable TOPOEXT feature for legacy machines and also disable TOPOEXT feature if the config cannot be supported. Signed-off-by: Babu Moger ---

[Qemu-devel] [PATCH v10 1/5] i386: Clean up cache CPUID code

From: Eduardo Habkost Always initialize CPUCaches structs with cache information, even if legacy_cache=true. Use different CPUCaches struct for CPUID[2], CPUID[4], and the AMD CPUID leaves. This will simplify a lot the logic inside cpu_x86_cpuid(). Signed-off-by: Eduardo

[Qemu-devel] [PATCH v10 3/5] i386: Add support for CPUID_8000_001E for AMD

Add support for cpuid leaf CPUID_8000_001E. Build the config that closely match the underlying hardware. Please refer Processor Programming Reference (PPR) for AMD Family 17h Model for more details. Signed-off-by: Babu Moger --- target/i386/cpu.c | 85

Re: [Qemu-devel] [PATCH 02/27] Make tb_invalidate_phys_addr() take a MemTxAttrs argument

On 05/21/2018 07:03 AM, Peter Maydell wrote: > As part of plumbing MemTxAttrs down to the IOMMU translate method, > add MemTxAttrs as an argument to tb_invalidate_phys_addr(). > Its callers either have an attrs value to hand, or don't care > and can use MEMTXATTRS_UNSPECIFIED. > > Signed-off-by:

[Qemu-devel] [PATCH v3 14/17] translate-all: protect TB jumps with a per-destination-TB lock

This applies to both user-mode and !user-mode emulation. Instead of relying on a global lock, protect the list of incoming jumps with tb->jmp_lock. This lock also protects tb->cflags, so update all tb->cflags readers outside tb->jmp_lock to use atomic reads via tb_cflags(). In order to find the

[Qemu-devel] [PATCH v3 10/17] translate-all: use per-page locking in !user-mode

Groundwork for supporting parallel TCG generation. Instead of using a global lock (tb_lock) to protect changes to pages, use fine-grained, per-page locks in !user-mode. User-mode stays with mmap_lock. Sometimes changes need to happen atomically on more than one page (e.g. when a TB that spans

[Qemu-devel] [PATCH v3 11/17] translate-all: add page_locked assertions

This is only compiled under CONFIG_DEBUG_TCG to avoid bloating the binary. In user-mode, assert_page_locked is equivalent to assert_mmap_lock. Note: There are some tb_lock assertions left that will be removed by later patches. Suggested-by: Alex Bennée Signed-off-by:

[Qemu-devel] [PATCH v3 03/17] tcg: track TBs with per-region BST's

This paves the way for enabling scalable parallel generation of TCG code. Instead of tracking TBs with a single binary search tree (BST), use a BST for each TCG region, protecting it with a lock. This is as scalable as it gets, since each TCG thread operates on a separate region. The core of

[Qemu-devel] [PATCH v3 16/17] translate-all: remove tb_lock mention from cpu_restore_state_from_tb

tb_lock was needed when the function did retranslation. However, since fca8a500d519 ("tcg: Save insn data and use it in cpu_restore_state_from_tb") we don't do retranslation. Get rid of the comment. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota

[Qemu-devel] [PATCH v3 02/17] qht: return existing entry when qht_insert fails

The meaning of "existing" is now changed to "matches in hash and ht->cmp result". This is saner than just checking the pointer value. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota

[Qemu-devel] [PATCH v3 13/17] translate-all: discard TB when tb_link_page returns an existing matching TB

Use the recently-gained QHT feature of returning the matching TB if it already exists. This allows us to get rid of the lookup we perform right after acquiring tb_lock. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson

[Qemu-devel] [PATCH v3 08/17] translate-all: work page-by-page in tb_invalidate_phys_range_1

So that we pass a same-page range to tb_invalidate_phys_page_range, instead of always passing an end address that could be on a different page. As discussed with Peter Maydell on the list [1], tb_invalidate_phys_page_range doesn't actually do much with 'end', which explains why we have never hit

[Qemu-devel] [PATCH v3 05/17] translate-all: iterate over TBs in a page with PAGE_FOR_EACH_TB

This commit does several things, but to avoid churn I merged them all into the same commit. To wit: - Use uintptr_t instead of TranslationBlock * for the list of TBs in a page. Just like we did in (c37e6d7e "tcg: Use uintptr_t type for jmp_list_{next|first} fields of TB"), the rationale is

[Qemu-devel] [PATCH v3 15/17] cputlb: remove tb_lock from tlb_flush functions

The acquisition of tb_lock was added when the async tlb_flush was introduced in e3b9ca810 ("cputlb: introduce tlb_flush_* async work.") tb_lock was there to allow us to do memset() on the tb_jmp_cache's. However, since f3ced3c5928 ("tcg: consistently access cpu->tb_jmp_cache atomically") all

[Qemu-devel] [PATCH v3 17/17] tcg: remove tb_lock

Use mmap_lock in user-mode to protect TCG state and the page descriptors. In !user-mode, each vCPU has its own TCG state, so no locks needed. Per-page locks are used to protect the page descriptors. Per-TB locks are used in both modes to protect TB jumps. Some notes: - tb_lock is removed from

[Qemu-devel] [PATCH v3 09/17] translate-all: move tb_invalidate_phys_page_range up in the file

This greatly simplifies next commit's diff. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 77 --- 1 file

[Qemu-devel] [PATCH v3 01/17] qht: require a default comparison function

qht_lookup now uses the default cmp function. qht_lookup_custom is defined to retain the old behaviour, that is a cmp function is explicitly provided. qht_insert will gain use of the default cmp in the next patch. Note that we move qht_lookup_custom's @func to be the last argument, which makes

[Qemu-devel] [PATCH v3 04/17] tcg: move tb_ctx.tb_phys_invalidate_count to tcg_ctx

Thereby making it per-TCGContext. Once we remove tb_lock, this will avoid an atomic increment every time a TB is invalidated. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota ---

[Qemu-devel] [PATCH v3 06/17] translate-all: make l1_map lockless

Groundwork for supporting parallel TCG generation. We never remove entries from the radix tree, so we can use cmpxchg to implement lockless insertions. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota

[Qemu-devel] [PATCH v3 12/17] translate-all: introduce assert_no_pages_locked

The appended adds assertions to make sure we do not longjmp with page locks held. Note that user-mode has nothing to check, since page_locks are !user-mode only. Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 8 accel/tcg/cpu-exec.c | 1 +

[Qemu-devel] [PATCH v3 07/17] translate-all: remove hole in PageDesc

Groundwork for supporting parallel TCG generation. Move the hole to the end of the struct, so that a u32 field can be added there without bloating the struct. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G.

[Qemu-devel] [PATCH v3 00/17] tcg: tb_lock removal redux v3

v2: https://lists.nongnu.org/archive/html/qemu-devel/2018-04/msg00656.html Changes since v2: - rebase onto master, fixing conflicts - add R-b's - add a missing page_lock to page_collection_lock - add a couple of missing assert_page_locked assertions - add page_lock_pair, as suggested by Alex

Re: [Qemu-devel] [PATCH v2 1/1] tests/docker: Add a Avocado Docker test

On 05/21/2018 07:33 PM, Alistair Francis wrote: > On Sun, May 20, 2018 at 8:16 PM, Fam Zheng wrote: >> On Fri, 05/18 11:34, Alistair Francis wrote: >>> Avocado is not trivial to setup on non-Fedora systems. To simplfying >>> future testing add a docker test image that runs

Re: [Qemu-devel] [PATCH v2 1/1] tests/docker: Add a Avocado Docker test

On 05/21/2018 07:37 PM, Alistair Francis wrote: > On Mon, May 21, 2018 at 10:26 AM, Philippe Mathieu-Daudé > wrote: >> Hi Alistair, Fam, >> >> On 05/21/2018 12:16 AM, Fam Zheng wrote: >>> On Fri, 05/18 11:34, Alistair Francis wrote: Avocado is not trivial to setup on

[Qemu-devel] Virtio-net drivers immune to Nethammer?

Hi I'm a privacy distro maintainer investigating the implications of the newly published nethammer attack [0] on KVM guests particularly the virtio-net drivers. The summary of the paper is that rowhammer can be remotely triggered by feeding susceptible* network driver crafted traffic. This

Re: [Qemu-devel] [PATCH v2 1/1] tests/docker: Add a Avocado Docker test

On Mon, May 21, 2018 at 10:26 AM, Philippe Mathieu-Daudé wrote: > Hi Alistair, Fam, > > On 05/21/2018 12:16 AM, Fam Zheng wrote: >> On Fri, 05/18 11:34, Alistair Francis wrote: >>> Avocado is not trivial to setup on non-Fedora systems. To simplfying >>> future testing add a

Re: [Qemu-devel] [PATCH v2 1/1] tests/docker: Add a Avocado Docker test

On Sun, May 20, 2018 at 8:16 PM, Fam Zheng wrote: > On Fri, 05/18 11:34, Alistair Francis wrote: >> Avocado is not trivial to setup on non-Fedora systems. To simplfying >> future testing add a docker test image that runs Avocado tests. >> >> Signed-off-by: Alistair Francis

[Qemu-devel] [PULL 1/3] i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639)

From: Daniel P. Berrangé New microcode introduces the "Speculative Store Bypass Disable" CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: Daniel P. Berrangé Reviewed-by: Konrad

[Qemu-devel] [PULL 3/3] i386: define the AMD 'virt-ssbd' CPUID feature bit (CVE-2018-3639)

From: Konrad Rzeszutek Wilk AMD Zen expose the Intel equivalant to Speculative Store Bypass Disable via the 0x8008_EBX[25] CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: Konrad Rzeszutek Wilk

[Qemu-devel] [PULL 2/3] i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)

From: Konrad Rzeszutek Wilk "Some AMD processors only support a non-architectural means of enabling speculative store bypass disable (SSBD). To allow a simplified view of this to a guest, an architectural definition has been created through a new CPUID bit,

[Qemu-devel] [PULL 0/3] Speculative store buffer bypass mitigation (CVE-2018-3639)

This provides the QEMU part of the mitigations for the speculative store buffer bypass vulnerabilities on the x86 platform[1], and is the companion of the kernel patches merged in:

Re: [Qemu-devel] [PATCH 0/3] i386: speculative store buffer bypass mitigation (CVE-2018-3639)

On Mon, May 21, 2018 at 10:54:21PM +0100, Daniel P. Berrangé wrote: > This provides the QEMU part of the mitigations for the speculative > store buffer bypass vulnerabilities on the x86 platform[1], and is > the companion of the kernel patches merged in: > > >

[Qemu-devel] [PATCH 0/3] i386: speculative store buffer bypass mitigation (CVE-2018-3639)

This provides the QEMU part of the mitigations for the speculative store buffer bypass vulnerabilities on the x86 platform[1], and is the companion of the kernel patches merged in:

[Qemu-devel] [PATCH 1/3] i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639)

New microcode introduces the "Speculative Store Bypass Disable" CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: Daniel P. Berrangé Reviewed-by: Konrad Rzeszutek Wilk

[Qemu-devel] [PATCH 3/3] i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)

From: Konrad Rzeszutek Wilk "Some AMD processors only support a non-architectural means of enabling speculative store bypass disable (SSBD). To allow a simplified view of this to a guest, an architectural definition has been created through a new CPUID bit,

[Qemu-devel] [PATCH 2/3] i386: define the AMD 'virt-ssbd' CPUID feature bit (CVE-2018-3639)

From: Konrad Rzeszutek Wilk AMD Zen expose the Intel equivalant to Speculative Store Bypass Disable via the 0x8008_EBX[25] CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: Konrad Rzeszutek Wilk

Re: [Qemu-devel] storing machine data in qcow images?

On Mon, May 21, 2018 at 09:18:17PM +0100, Daniel P. Berrangé wrote: > On Fri, May 18, 2018 at 02:41:33PM -0300, Eduardo Habkost wrote: > > On Fri, May 18, 2018 at 06:09:56PM +0100, Daniel P. Berrangé wrote: > > > On Fri, May 18, 2018 at 06:30:38PM +0300, Michael S. Tsirkin wrote: > > > > Hi! > > >

Re: [Qemu-devel] [PATCH v7 1/3] qmp: adding 'wakeup-suspend-support' in query-target

On Mon, May 21, 2018 at 04:46:36PM -0300, Daniel Henrique Barboza wrote: > > > On 05/21/2018 03:14 PM, Eduardo Habkost wrote: > > > Issue#2: the flag isn't a property of the target. Due to -no-acpi, it's > > > not even a property of the machine type. If it was, query-machines > > > would be

Re: [Qemu-devel] storing machine data in qcow images?

On Fri, May 18, 2018 at 02:41:33PM -0300, Eduardo Habkost wrote: > On Fri, May 18, 2018 at 06:09:56PM +0100, Daniel P. Berrangé wrote: > > On Fri, May 18, 2018 at 06:30:38PM +0300, Michael S. Tsirkin wrote: > > > Hi! > > > Right now, QEMU supports multiple machine types within > > > a given

Re: [Qemu-devel] [PATCH] target/arm: Honour FPCR.FZ in FRECPX

On 05/21/2018 10:27 AM, Peter Maydell wrote: > The FRECPX instructions should (like most other floating point operations) > honour the FPCR.FZ bit which specifies whether input denormals should > be flushed to zero (or FZ16 for the half-precision version). > We forgot to implement this, which

Re: [Qemu-devel] [PATCH v7 1/3] qmp: adding 'wakeup-suspend-support' in query-target

On 05/21/2018 03:14 PM, Eduardo Habkost wrote: Issue#2: the flag isn't a property of the target. Due to -no-acpi, it's not even a property of the machine type. If it was, query-machines would be the natural owner of the flag. Perhaps query-machines is still the proper owner. The value of

[Qemu-devel] [PULL 12/15] xen_disk: remove use of grant map/unmap

From: Paul Durrant Now that the (native or emulated) xen_be_copy_grant_refs() helper is always available, the xen_disk code can be significantly simplified by removing direct use of grant map and unmap operations. Signed-off-by: Paul Durrant

[Qemu-devel] [PULL 15/15] xen_disk: be consistent with use of xendev and blkdev->xendev

From: Paul Durrant Certain functions in xen_disk are called with a pointer to xendev (struct XenDevice *). They then use container_of() to acces the surrounding blkdev (struct XenBlkDev) but then in various places use >xendev when use of the original xendev pointer is

Re: [Qemu-devel] [PATCH 01/27] memory.h: Improve IOMMU related documentation

On 05/21/2018 07:03 AM, Peter Maydell wrote: > Add more detail to the documentation for memory_region_init_iommu() > and other IOMMU-related functions and data structures. > > Signed-off-by: Peter Maydell > --- > v2->v3 changes: > * minor wording tweaks per Eric's

[Qemu-devel] [PULL 09/15] xen_disk: remove open-coded use of libxengnttab

From: Paul Durrant Now that helpers are present in xen_backend, this patch removes open-coded calls to libxengnttab from the xen_disk code. This patch also fixes one whitspace error in the assignment of the XenDevOps initialise method. Signed-off-by: Paul Durrant

[Qemu-devel] [PULL 03/15] configure: Add explanation for --enable-xen-pci-passthrough

From: Anthony PERARD Signed-off-by: Anthony PERARD Reviewed-by: Markus Armbruster Signed-off-by: Stefano Stabellini --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Qemu-devel] [PULL 10/15] xen: remove other open-coded use of libxengnttab

From: Paul Durrant Now that helpers are available in xen_backend, use them throughout all Xen PV backends. Signed-off-by: Paul Durrant Acked-by: Anthony Perard Signed-off-by: Stefano Stabellini

[Qemu-devel] [PULL 06/15] All the xen stable APIs define handle types of the form:

From: Paul Durrant xen_handle and some define additional handle types of the form: xen__handle Examples of these are xenforeignmemory_handle and xenforeignmemory_resource_handle. Both of these types will be misparsed by checkpatch if they appear as the first token in

[Qemu-devel] [PULL 14/15] xen_disk: use a single entry iovec

From: Paul Durrant Since xen_disk now always copies data to and from a guest there is no need to maintain a vector entry corresponding to every page of a request. This means there is less per-request state to maintain so the ioreq structure can shrink significantly.

[Qemu-devel] [PULL 07/15] xen: add a meaningful declaration of grant_copy_segment into xen_common.h

From: Paul Durrant Currently the xen_disk source has to carry #ifdef exclusions to compile against Xen older then 4.8. This is a bit messy so this patch lifts the definition of struct xengnttab_grant_copy_segment and adds it into the pre-4.8 compat area in xen_common.h,

[Qemu-devel] [PULL 13/15] xen_backend: make the xen_feature_grant_copy flag private

From: Paul Durrant There is no longer any use of this flag outside of the xen_backend code. Signed-off-by: Paul Durrant Acked-by: Anthony Perard Signed-off-by: Stefano Stabellini ---

[Qemu-devel] [PULL 05/15] xen-hvm: create separate function for ioreq server initialization

From: Paul Durrant The code is sufficiently substantial that it improves code readability to put it in a new function called by xen_hvm_init() rather than having it inline. Signed-off-by: Paul Durrant Reviewed-by: Anthony Perard

[Qemu-devel] [PULL 02/15] xen/pt: use address_space_memory object for memory region hooks

From: Igor Druzhinin Commit 99605175c (xen-pt: Fix PCI devices re-attach failed) introduced a subtle bug. As soon as the guest switches off Bus Mastering on the device it immediately causes all the BARs be unmapped due to the DMA address space of the device being

[Qemu-devel] [PULL 11/15] xen_backend: add an emulation of grant copy

From: Paul Durrant Not all Xen environments support the xengnttab_grant_copy() operation. E.g. where the OS is FreeBSD or Xen is older than 4.8.0. This patch introduces an emulation of that operation using xengnttab_map_domain_grant_refs() and memcpy() for those

[Qemu-devel] [PULL 01/15] xen-pvdevice: Introduce a simplistic xen-pvdevice save state

From: Igor Druzhinin This should help to avoid problems with accessing the device after migration/resume without PV drivers by migrating its PCI configuration space state. Without an explicitly defined state record it resets every time a VM migrates which confuses the

[Qemu-devel] [PULL 08/15] xen_backend: add grant table helpers

From: Paul Durrant This patch adds grant table helper functions to the xen_backend code to localize error reporting and use of xen_domid. The patch also defers the call to xengnttab_open() until just before the initialise method in XenDevOps is invoked. This method is

[Qemu-devel] [PULL 04/15] xen_pt: Present the size of 64 bit BARs correctly

From: Ross Lagerwall The full size of the BAR is stored in the lower PCIIORegion.size. The upper PCIIORegion.size is 0. Calculate the size of the upper half correctly from the lower half otherwise the size read by the guest will be incorrect. Signed-off-by: Ross

[Qemu-devel] [PULL 00/15] xen-20180521-tag

/sstabellini/qemu-dm.git tags/xen-20180521-tag for you to fetch changes up to f03df99f09ee0ca27ea2298a1b77438e7999044d: xen_disk: be consistent with use of xendev and blkdev->xendev (2018-05-18 11:13:01 -0700) Xen 2018/05

Re: [Qemu-devel] storing machine data in qcow images?

On Mon, May 21, 2018 at 07:44:40PM +0100, Daniel P. Berrangé wrote: > On Mon, May 21, 2018 at 03:29:28PM -0300, Eduardo Habkost wrote: > > On Sat, May 19, 2018 at 08:05:06AM +0200, Markus Armbruster wrote: > > > Eduardo Habkost writes: > > > > > > [...] > > > > About being

Re: [Qemu-devel] storing machine data in qcow images?

On Mon, May 21, 2018 at 03:29:28PM -0300, Eduardo Habkost wrote: > On Sat, May 19, 2018 at 08:05:06AM +0200, Markus Armbruster wrote: > > Eduardo Habkost writes: > > > > [...] > > > About being more expressive than just a single list of key,value > > > pairs, I don't see any

Re: [Qemu-devel] storing machine data in qcow images?

On Sat, May 19, 2018 at 08:05:06AM +0200, Markus Armbruster wrote: > Eduardo Habkost writes: > > [...] > > About being more expressive than just a single list of key,value > > pairs, I don't see any evidence of that being necessary for the > > problems we're trying to

Re: [Qemu-devel] [qemu PATCH v4 2/4] tests/.gitignore: add entry for generated file

On 05/21/2018 12:32 PM, Philippe Mathieu-Daudé wrote: tests/test-block-backend +test-block-backend   test-blockjob   test-blockjob-txn   test-bufferiszero What about using gitignore negated pattern in tests/? Or, what we've threatened to do in the past: rename all unit tests to

Re: [Qemu-devel] [PATCH v7 1/3] qmp: adding 'wakeup-suspend-support' in query-target

On Fri, May 18, 2018 at 10:48:31AM +0200, Markus Armbruster wrote: > Cc'ing a few more people. > > Daniel Henrique Barboza writes: > > > When issuing the qmp/hmp 'system_wakeup' command, what happens in a > > nutshell is: > > > > - qmp_system_wakeup_request set runstate

Re: [Qemu-devel] [PATCH v3 0/8] linux-user: move socket.h definitions to CPU directories

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180519092956.15134-1-laur...@vivier.eu Subject: [Qemu-devel] [PATCH v3 0/8] linux-user: move socket.h definitions to CPU directories === TEST SCRIPT BEGIN === #!/bin/bash

Re: [Qemu-devel] [qemu PATCH v4 2/4] tests/.gitignore: add entry for generated file

On 05/21/2018 01:41 PM, Eric Blake wrote: > On 05/21/2018 11:32 AM, Ross Zwisler wrote: >> After a "make check" we end up with the following: >> >> $ git status >> On branch master >> Your branch is up-to-date with 'origin/master'. >> >> Untracked files: >>    (use "git add ..." to include in what

[Qemu-devel] [PATCH] target/arm: Honour FPCR.FZ in FRECPX

The FRECPX instructions should (like most other floating point operations) honour the FPCR.FZ bit which specifies whether input denormals should be flushed to zero (or FZ16 for the half-precision version). We forgot to implement this, which doesn't affect the results (since the calculation doesn't

Re: [Qemu-devel] [PATCH v2 1/1] tests/docker: Add a Avocado Docker test

Hi Alistair, Fam, On 05/21/2018 12:16 AM, Fam Zheng wrote: > On Fri, 05/18 11:34, Alistair Francis wrote: >> Avocado is not trivial to setup on non-Fedora systems. To simplfying >> future testing add a docker test image that runs Avocado tests. Can you add an entry in the "make docker" help

Re: [Qemu-devel] [qemu PATCH v4 2/4] tests/.gitignore: add entry for generated file

On 05/21/2018 11:32 AM, Ross Zwisler wrote: After a "make check" we end up with the following: $ git status On branch master Your branch is up-to-date with 'origin/master'. Untracked files: (use "git add ..." to include in what will be committed) tests/test-block-backend nothing

[Qemu-devel] Ping [PATCH RFC v2 0/2] Fix UART serial implementation

Hello, It's been about a week since the last email to my patches, in case anyone would like to review but missed them. Patches are the following on patchwork: http://patchwork.ozlabs.org/patch/912281/ http://patchwork.ozlabs.org/patch/912282/ And the following on patchew:

[Qemu-devel] [qemu PATCH v4 3/4] nvdimm, acpi: support NFIT platform capabilities

Add a machine command line option to allow the user to control the Platform Capabilities Structure in the virtualized NFIT. This Platform Capabilities Structure was added in ACPI 6.2 Errata A. Signed-off-by: Ross Zwisler --- docs/nvdimm.txt | 27

[Qemu-devel] [qemu PATCH v4 2/4] tests/.gitignore: add entry for generated file

After a "make check" we end up with the following: $ git status On branch master Your branch is up-to-date with 'origin/master'. Untracked files: (use "git add ..." to include in what will be committed) tests/test-block-backend nothing added to commit but untracked files present (use

[Qemu-devel] [qemu PATCH v4 1/4] nvdimm: fix typo in label-size definition

Signed-off-by: Ross Zwisler Fixes: commit da6789c27c2e ("nvdimm: add a macro for property "label-size"") Reviewed-by: Stefan Hajnoczi Reviewed-by: Igor Mammedov Cc: Haozhong Zhang Cc: Michael S.

[Qemu-devel] [qemu PATCH v4 4/4] ACPI testing: test NFIT platform capabilities

Add testing for the newly added NFIT Platform Capabilities Structure. Signed-off-by: Ross Zwisler Suggested-by: Igor Mammedov --- tests/acpi-test-data/pc/NFIT.dimmpxm | Bin 224 -> 240 bytes tests/acpi-test-data/q35/NFIT.dimmpxm | Bin 224 ->

[Qemu-devel] [qemu PATCH v4 0/4] support NFIT platform capabilities

Changes since v3: * Updated the text in docs/nvdimm.txt to make it clear that the value being passed in on the command line in an integer made up of various bit fields. (Rob Elliott) * Updated the "Highest Valid Capability" byte to be dynamic based on the highest valid bit in the

[Qemu-devel] [PATCH v2] Delete AF_UNIX socket after close

This is a second attempt at sending this patch: http://lists.nongnu.org/archive/html/qemu-devel/2018-05/msg04697.html Signed-off-by: Pavel Balaev --- io/channel-socket.c | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/io/channel-socket.c

Re: [Qemu-devel] [PATCH 00/27] iommu: support txattrs, support TCG execution, implement TZ MPC

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180521140402.23318-1-peter.mayd...@linaro.org Subject: [Qemu-devel] [PATCH 00/27] iommu: support txattrs, support TCG execution, implement TZ MPC === TEST SCRIPT BEGIN

Re: [Qemu-devel] [qemu PATCH v2 3/4] nvdimm, acpi: support NFIT platform capabilities

On Fri, May 18, 2018 at 04:37:10PM +, Elliott, Robert (Persistent Memory) wrote: > > > ... > > Would it help to show them in hex? > > > > As of ACPI 6.2 Errata A, the following values are valid for the bottom > > two bits: > > > > 0x2 - Memory Controller Flush to NVDIMM Durability

[Qemu-devel] [PULL 1/1] lm32: take BQL before writing IP/IM register

Writing to these registers may raise an interrupt request. Actually, this prevents the milkymist board from starting. Cc: qemu-sta...@nongnu.org Signed-off-by: Michael Walle Tested-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée

[Qemu-devel] [PULL 0/1] target/lm32 BQL patch

The following changes since commit 81e9cbd0ca1131012b058df6804b1f626a6b730c: lm32: take BQL before writing IP/IM register (2018-05-21 13:37:12 +0200) are available in the git repository at: git://github.com/mwalle/qemu.git tags/lm32-queue/20180521 for you to fetch changes up

Re: [Qemu-devel] [PATCH v2 2/2] target/lm32: hold BQL in gdbstub

Am 2018-05-21 14:25, schrieb Peter Maydell: On 21 May 2018 at 13:21, Michael Walle wrote: Changing the IP/IM registers may cause interrupts, so hold the BQL. Cc: qemu-sta...@nongnu.org Signed-off-by: Michael Walle --- target/lm32/gdbstub.c | 5 + 1

[Qemu-devel] [PATCH v3 5/5] qmp: add pmemload command

Adapted patch from Baojun Wang [1] with the following commit message: I found this could be useful to have qemu-softmmu as a cross debugger (launch with -s -S command line option), then if we can have a command to load guest physical memory, we can use cross gdb to do some target

[Qemu-devel] [PATCH v3 2/5] cpus: convert qmp_memsave/qmp_pmemsave to use qemu_open

qemu_open() allows passing file descriptors to qemu which is used in restricted environments like libvirt where open() is prohibited. Suggested-by: Eric Blake Signed-off-by: Simon Ruderich Reviewed-by: Eric Blake --- cpus.c | 20

[Qemu-devel] [PATCH v3 3/5] cpus: use size_t in qmp_memsave/qmp_pmemsave

It's the natural type for object sizes and matches the return value of sizeof(buf). Signed-off-by: Simon Ruderich Reviewed-by: Eric Blake --- cpus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpus.c b/cpus.c index

[Qemu-devel] [PATCH v3 1/5] cpus: correct coding style in qmp_memsave/qmp_pmemsave

Signed-off-by: Simon Ruderich Reviewed-by: Eric Blake --- cpus.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/cpus.c b/cpus.c index d1f16296de..4b1609fe90 100644 --- a/cpus.c +++ b/cpus.c @@ -2316,8 +2316,9 @@ void

[Qemu-devel] [PATCH v3 4/5] hmp: don't truncate size in hmp_memsave/hmp_pmemsave

The called function takes an uint64_t as size parameter and qdict_get_int() returns an uint64_t. Don't truncate it needlessly to an uint32_t. Signed-off-by: Simon Ruderich Reviewed-by: Eric Blake --- hmp.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[Qemu-devel] [PATCH v3 0/5] qmp: add pmemload command

Hello, This is third version of this patch set, rebased on current master. As I've received no answers to [1] (and I'd prefer to keep the patch as is for now if possible) this doesn't include any changes to address the comments to [2]. If there's anything else I can do to get these patches

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