From: "Dr. David Alan Gilbert"
Add a flag to command definitions to allow them to be used in preconfig
and check it.
If users try to use commands that aren't available, tell them to use
the exit_preconfig comand we're adding in a few patches.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: M
From: "Dr. David Alan Gilbert"
Add the exit_preconfig command to return to normality.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Peter Xu
Reviewed-by: Igor Mammedov
---
hmp-commands.hx | 19 +++
hmp.c | 8
hmp.h | 1 +
3 files changed, 2
From: "Dr. David Alan Gilbert"
Reenable HMP in preconfig mode; it's pretty
easy and anyway I want to do a similar thing for OOB eventually.
We'll want to enable more commands in preconfig mode to make it
useful at some point.
Dave
v4
Fixes from Markus' review.
Including enabling some mor
From: "Dr. David Alan Gilbert"
Don't show the commands that aren't available.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Peter Xu
Reviewed-by: Igor Mammedov
---
monitor.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/monitor.c b/monitor.c
index 8ff0e2fc
On 06/12/2018 12:36 AM, Eduardo Habkost wrote:
> CCing libvir-list.
>
> On Mon, Jun 11, 2018 at 11:29:24PM +0200, Igor Mammedov wrote:
>> On Mon, 11 Jun 2018 16:06:07 -0300
>> Eduardo Habkost wrote:
>>
>>> On Mon, Jun 11, 2018 at 03:16:25PM +0200, Igor Mammedov wrote:
On Fri, 8 Jun 2018 10:2
On Tue, 12 Jun 2018 16:45:02 +1000
David Gibson wrote:
> From: Cédric Le Goater
>
> The KVM helpers hide the low level interface used to communicate to
> the XICS KVM device and provide a good cleanup to the XICS KVM models.
>
> Signed-off-by: Cédric Le Goater
> Signed-off-by: David Gibson
>
Describe new pci segments of host bridges in AML. The host bridge list is
replaced by QTAILQ to let q35 host be processed first in every traverse
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c | 69 ++-
hw/pci/pci.c | 9 ---
The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
add a new type TYPE_PXB_PCIE_HOST to better utilize the ECAM of PCIe
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 118 ++--
1 file changed, 114 insertions(+), 4 delet
Hi all, after some delay, here is the v2 version of putting pxb host bridge
into separate pci domain.
Currently only q35 host bridge is allocated an item in MCFG table, all pxb
host bridges stay within pci domain 0. This series of patches put each pxb
host bridge in separate pci domain, allocating
On 12 June 2018 at 07:24, Peter Xu wrote:
> For example, I wanted to compile QEMU once and install it on multiple
> systems. What would be the suggested way to do so?
For this, I would recommend using whatever the packaging
format for those systems is. Eg for Debian use the existing
Debian QEMU
expected_downtime value is not accurate with dirty_pages_rate * page_size,
using ram_bytes_remaining() would yeild it resonable.
consider to read the remaining ram just after having updated the dirty
pages count later migration_bitmap_sync_range() in migration_bitmap_sync()
and reuse the `remainin
V4:
Read the remaining ram after updating dirty pages count and reuse
existing `remaining` field in ram_counters to hold ram_bytes_remaining()
Thank you Laurent for your time and help to investigate and correct my
changes.
V3:
* commit message to be updated with the changes done by the patch si
* Markus Armbruster (arm...@redhat.com) wrote:
> "Dr. David Alan Gilbert" writes:
>
> > * Markus Armbruster (arm...@redhat.com) wrote:
> >> "Dr. David Alan Gilbert (git)" writes:
> >>
> >> > From: "Dr. David Alan Gilbert"
> >> >
> >> > Allow a bunch of the info commands to be used in preconfig
On 12 June 2018 at 06:45, yt zhang wrote:
> Dear technicians，
> Good day.
> I encountered some problems in the process of learning qemu, so I
> would like to ask technical staff.
> QEMU is running User Model mode and enables TCI function. What is the
> workflow of qemu at TCG and TCI sta
On Tue, 06/12 09:28, Daniel P. Berrangé wrote:
> When configure fails in CI systems we must be able to see the contents
> of the config.log file to diagnose the root cause.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> .travis.yml | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>
** Merge proposal unlinked:
https://code.launchpad.net/~paelzer/ubuntu/+source/qemu/+git/qemu/+merge/347801
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Title:
Ability to control phys-
When configure fails in CI systems we must be able to see the contents
of the config.log file to diagnose the root cause.
Signed-off-by: Daniel P. Berrangé
---
.travis.yml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index 814be151f4..fc9a1fe8
Hi,
On 06/08/2018 08:57 AM, Eric Auger wrote:
> From: Jia He
>
> In case the STE's config is "Bypass" we currently don't set the
> IOMMUTLBEntry perm flags and the access does not succeed. Also
> if the config is 0b0xx (Aborted/Reserved), decode_ste and
> smmuv3_decode_config currently returns -
We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256.
It is implemented as a hash table whose key is a combination
of the 16b asid and 48b IOVA (Jenkins hash).
Entries are invalidated on TLB invalidation commands, either
globally, or per asid, or per asid/iova.
Signed-off-by: Eric Auger
---
From: Jia He
In case the STE's config is "Bypass" we currently don't set the
IOMMUTLBEntry perm flags and the access does not succeed. Also
if the config is 0b0xx (Aborted/Reserved), decode_ste and
smmuv3_decode_config currently returns -EINVAL and we don't enter
the expected code path: we record
Let's cache config data to avoid fetching and parsing STE/CD
structures on each translation. We invalidate them on data structure
invalidation commands.
We put in place a per-smmu mutex to protect the config cache. This
will be useful too to protect the IOTLB cache. The caches can be
accessed with
On TLB invalidation commands, let's call registered
IOMMU notifiers. Those can only be UNMAP notifiers.
SMMUv3 does not support notification on MAP (VFIO).
This patch allows vhost use case where IOTLB API is notified
on each guest IOTLB invalidation.
Signed-off-by: Eric Auger
---
hw/arm/smmu-co
On Mon, Jun 11, 2018 at 10:52:03PM +0200, Max Reitz wrote:
> Remove the encrypt.format option from the two blockdev-add test cases
> for encrypted qcow2 images in 087 to explicitly test that this parameter
> is now optional.
>
> Additionally, show that explicitly specifying encrypt.format=auto wor
This series brings translation configuration caching and IOTLB
emulation. The last patch implements VHOST integration and
allows to run VSMMUv3 along with VHOST emulated end points.
The first patch fixes the passthrough mode bug reported by Jia.
It reworks the translate function and this series n
On Mon, Jun 11, 2018 at 10:51:58PM +0200, Max Reitz wrote:
> qcow only supports a single encryption (and there is no reason why that
> would change in the future), so we can make it the default.
>
> Signed-off-by: Max Reitz
> ---
> qapi/block-core.json | 3 ++-
> 1 file changed, 2 insertions(+),
On Mon, Jun 11, 2018 at 10:51:57PM +0200, Max Reitz wrote:
> Currently, you can give no encryption format for a qcow2 file while
> still passing a key-secret. That does not conform to the schema, so
> this patch changes the schema to allow it.
>
> Signed-off-by: Max Reitz
> ---
> qapi/block-cor
** Merge proposal linked:
https://code.launchpad.net/~paelzer/ubuntu/+source/qemu/+git/qemu/+merge/347801
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Title:
Ability to control phys-bi
On Mon, Jun 11, 2018 at 03:01:52PM -0300, Eduardo Habkost wrote:
> The COPYING.PYTHON file was added when we added the compatibility
> argparse.py module, which was licensed under the Python Software
> Foundation License Version 2.
>
> Now the compatibility argparse.py module was removed, and we a
On Mon, Jun 11, 2018 at 11:33:42PM +0200, Igor Mammedov wrote:
> On Mon, 11 Jun 2018 15:40:16 -0300
> Eduardo Habkost wrote:
>
> > On Mon, Jun 11, 2018 at 02:01:52PM +0200, Markus Armbruster wrote:
> > > * Eduardo, why does "info numa" have no QMP equivalent?
> >
> > Nobody ever asked for one, w
On 12 June 2018 at 10:44:09, Peter Xu (pet...@redhat.com) wrote:
> But it'll still be good if we can have a single package to play around
> with. If there is no known way to do, we can try to figure a way out.
you can take a look at:
https://github.com/gnu-mcu-eclipse/qemu-build
the scripts can
On Fri, Jun 08, 2018 at 04:10:41PM +0800, Wei Wang wrote:
> This patch adds a ram save state notifier list, and expose RAMState for
> the notifer callbacks to use.
>
> Signed-off-by: Wei Wang
> CC: Dr. David Alan Gilbert
> CC: Juan Quintela
> CC: Michael S. Tsirkin
> CC: Peter Xu
> ---
> inc
Dear technicians，
Good day.
I encountered some problems in the process of learning qemu, so I
would like to ask technical staff.
QEMU is running User Model mode and enables TCI function. What is the
workflow of qemu at TCG and TCI stages? Is there a related program flow
diagram?
Thanks &
On Tue, Jun 12, 2018 at 03:01:52PM +0800, Fam Zheng wrote:
> On Tue, 06/12 14:52, Peter Xu wrote:
> > On Tue, Jun 12, 2018 at 02:41:19PM +0800, Fam Zheng wrote:
> > > On Tue, 06/12 14:24, Peter Xu wrote:
> > > > Hi,
> > > >
> > > > For example, I wanted to compile QEMU once and install it on multi
On 06/11/2018 07:26 PM, Thomas Huth wrote:
> Add a sanity checks to fix the following two crashes:
>
> $ echo "Insane in the mainframe" > /tmp/test.txt
> $ s390x-softmmu/qemu-system-s390x -kernel /tmp/test.txt -append xyz
> Segmentation fault (core dumped)
> $ s390x-softmmu/qemu-system-s390x -k
** Merge proposal linked:
https://code.launchpad.net/~paelzer/ubuntu/+source/qemu/+git/qemu/+merge/347801
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https://bugs.launchpad.net/bugs/1769053
Title:
Ability to control phys-bi
** Merge proposal linked:
https://code.launchpad.net/~paelzer/ubuntu/+source/qemu/+git/qemu/+merge/347796
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https://bugs.launchpad.net/bugs/1769053
Title:
Ability to control phys-bi
On 06/11/2018 06:16 PM, Thomas Huth wrote:
> On 11.06.2018 15:52, Christian Borntraeger wrote:
>> Right now the IPL device always starts from address 0x1 (the usual
>> Linux entry point). To run other guests (e.g. test programs) it is
>> useful to use the IPL PSW from address 0. We can use t
Igor Mammedov writes:
> On Mon, 11 Jun 2018 15:40:16 -0300
> Eduardo Habkost wrote:
>
>> On Mon, Jun 11, 2018 at 02:01:52PM +0200, Markus Armbruster wrote:
>> > * Eduardo, why does "info numa" have no QMP equivalent?
>>
>> Nobody ever asked for one, which seems to qualify as "only for
>> human
** Merge proposal unlinked:
https://code.launchpad.net/~paelzer/ubuntu/+source/qemu/+git/qemu/+merge/347801
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https://bugs.launchpad.net/bugs/1769053
Title:
Ability to control phys-
"Dr. David Alan Gilbert" writes:
> * Markus Armbruster (arm...@redhat.com) wrote:
>> "Dr. David Alan Gilbert" writes:
>>
>> > * Markus Armbruster (arm...@redhat.com) wrote:
>> >> "Dr. David Alan Gilbert (git)" writes:
>> >>
>> >> > From: "Dr. David Alan Gilbert"
>> >> >
>> >> > Allow the 'he
Hello,
Here is a short series of cleanups and fixes for issues in the Aspeed
SMC controller model discovered when experimenting with the MMIO exec
feature and also from tests under a QEMU PowerNV machine.
Indeed, the OPAL/skiboot firmware accesses the Aspeed SoC address
space using the iLPC->AHB
Also handle the fake transfers for dummy bytes in this setup
routine. It will be useful when we activate MMIO execution.
Signed-off-by: Cédric Le Goater
---
hw/ssi/aspeed_smc.c | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/hw/ssi/aspeed_smc
** Merge proposal unlinked:
https://code.launchpad.net/~paelzer/ubuntu/+source/qemu/+git/qemu/+merge/347796
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Title:
Ability to control phys-
"Dr. David Alan Gilbert" writes:
> * Markus Armbruster (arm...@redhat.com) wrote:
>> "Dr. David Alan Gilbert (git)" writes:
>>
>> > From: Igor Mammedov
>> >
>> > subj commands, are informational and do not depend on machine being
>> > initialized. Make them available early in preconfig runstat
When configured in dual I/O mode, address and data are sent in dual
mode, including the dummy byte cycles in between. Adapt the count to
the IO setting.
Signed-off-by: Cédric Le Goater
---
hw/ssi/aspeed_smc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/aspe
From: Cédric Le Goater
The KVM helpers hide the low level interface used to communicate to
the XICS KVM device and provide a good cleanup to the XICS KVM models.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics_kvm.c | 52 +--
On Tue, 06/12 14:52, Peter Xu wrote:
> On Tue, Jun 12, 2018 at 02:41:19PM +0800, Fam Zheng wrote:
> > On Tue, 06/12 14:24, Peter Xu wrote:
> > > Hi,
> > >
> > > For example, I wanted to compile QEMU once and install it on multiple
> > > systems. What would be the suggested way to do so?
> > >
>
By default, the IOMMU model built into the spapr virtual PCI host bridge
supports 4kiB and 64kiB IOMMU page sizes. However this can be overridden
which may be desirable to allow larger IOMMU page sizes when running a
guest with hugepage backing and passthrough devices. For that reason a
warning w
On Tue, Jun 12, 2018 at 1:00 AM, Eric Blake wrote:
> On 06/11/2018 03:25 PM, Ville Skyttä wrote:
>>
>> Signed-off-by: Ville Skyttä
>> ---
>
[...]
>
>> +++ b/docs/interop/qcow2.txt
>> @@ -326,7 +326,7 @@ in the image file.
>> It contains pointers to the second level structures which are called
>
From: luporl
According to PowerISA, the PIR register should be readable in privileged
mode also, not only in hypervisor privileged mode.
PowerISA 3.0 - 4.3.3 Processor Identification Register
"Read access to the PIR is privileged; write access is not provided."
Figure 18 in section 4.4.4 expli
Only the flash type is strapped by HW. The 4BYTE mode is set by
firmware when the flash device is detected.
Signed-off-by: Cédric Le Goater
---
hw/ssi/aspeed_smc.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index fce126e6e
From: Mark Cave-Ayland
The timers are configured in the mos6522 init function and therefore will
always exist, so the function can never return false.
Peter also pointed out that this is the only remaining user of
VMSTATE_TIMER_PTR_TEST in the codebase, so we might as well just convert it
over t
Keno Fischer writes:
>> Suggest return strchrnul("Hello World", 'W') != 6, to avoid worries
>> about a sufficiently smart compilers optimizing out a call that would
>> otherwise fail to link, say because headers don't match libraries.
>
> I'm happy to do that, but then again, a sufficiently smart
On 11/06/2018 22:37, Eduardo Habkost wrote:
> RFC NOTE: Paolo, Richard, as far as I can see, there's no point
> in enabling OSPKE in user-mode QEMU. Do you confirm that?
>
> OSPKE is not a static feature flag: it changes dynamically at
> runtime depending on CR4, and it was never configurable: KV
On Tue, Jun 12, 2018 at 02:41:19PM +0800, Fam Zheng wrote:
> On Tue, 06/12 14:24, Peter Xu wrote:
> > Hi,
> >
> > For example, I wanted to compile QEMU once and install it on multiple
> > systems. What would be the suggested way to do so?
> >
> > Is there something similar to "make bin-rpmpkg" f
From: David Hildenbrand
Factor out memory unplug into separate function from spapr_lmb_release().
Then use generic hotplug_handler_unplug() to trigger memory unplug,
which will call spapr_machine_device_unplug() -> spapr_memory_unplug()
in the end.
This way unplug operation is not buried in lmb
From: David Hildenbrand
The node property can always be queried and the value has already been
verified in pc_dimm_realize().
Acked-by: David Gibson
Reviewed-by: Greg Kurz
Signed-off-by: David Hildenbrand
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 10 ++
1 file changed, 2 inse
From: Cédric Le Goater
POWER9 introduced a new variant of the eieio instruction using bit 6
as a hint to tell the CPU it is a store-forwarding barrier.
The usage of this eieio extension was recently added in Linux 4.17
which activated the "support for a store forwarding barrier at kernel
entry/e
Signed-off-by: Ville Skyttä
Reviewed-by: Peter Maydell
Reviewed-by: Eric Blake
---
docs/colo-proxy.txt | 2 +-
docs/config/mach-virt-graphical.cfg | 2 +-
docs/config/mach-virt-serial.cfg | 2 +-
docs/config/q35-emulated.cfg | 2 +-
docs/config/q35-virtio-graphical
From: David Hildenbrand
We'll be handling unplug of e.g. CPUs and PCDIMMs via the general
hotplug handler soon, so let's add that handler function.
Acked-by: David Gibson
Reviewed-by: Greg Kurz
Signed-off-by: David Hildenbrand
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 6 ++
1 fi
From: BALATON Zoltan
Make it more readable by converting register indexes to decimal
(avoids lot of superfluous 0x0) and distinguish errors caused by
accessing non-existent vs. unimplemented registers.
No functional change.
Signed-off-by: BALATON Zoltan
Signed-off-by: David Gibson
---
hw/i2c/
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/misc/mos6522.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 6163cea6ab..49166cb8ad 100644
--- a/hw/misc/mos6522.c
+++ b/h
From: David Hildenbrand
Let's finish cleaning up the hotplug handler. This check can be
performed in the pre_plug code as the very first thing.
Signed-off-by: David Hildenbrand
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 13 ++---
1 file changed, 6 inserti
From: Cédric Le Goater
A specific MemoryRegion is required for the LPC HC Firmware address
space.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/pnv_lpc.c | 4 +++-
include/hw/ppc/pnv_lpc.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw
From: Mark Cave-Ayland
This is used in OpenBIOS to define the memory layout of the NVRAM device. Whilst
currently left at its default value, add the missing definition to ensure it is
reserved.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
include/hw/ppc/ppc.h | 1 +
1 file
From: Mark Cave-Ayland
Commits 7b19318bee and 8ce3f743c7 removed the pci_pmac_init() and
pci_pmac_u3_init() functions but missed the header prototypes in mac.h. Remove
them since they are no longer needed.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David
From: Mark Cave-Ayland
Examining the migration stream it can be seen that the mos6522 device state is
being stored separately rather than as part of the CUDA device which is
incorrect (and likely to cause issues if another mos6522 device is added to
the machine).
Resolve this by embedding the mo
From: David Hildenbrand
Let's clean the hotplug handler up by moving lookup of the node into
the function where it is actually being used.
Signed-off-by: David Hildenbrand
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 12 +---
1 file changed, 5 insertions(+)
301 - 368 of 368 matches
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