The fw_cfg value returned from fw_cfg_find() may be NULL, so check it
before using.
Signed-off-by: Hongbo Zhang
---
hw/arm/boot.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index e09201c..43b217f 100644
--- a/hw/arm/boot.c
+++
For the Aarch64, there is one machine 'virt', it is primarily meant to
run on KVM and execute virtualization workloads, but we need an
environment as faithful as possible to physical hardware, for supporting
firmware and OS development for pysical Aarch64 machines.
This patch introduces new
Hi Eric,
>
> On 07/13/2018 02:52 AM, Pankaj Gupta wrote:
> > This patch adds virtio-pmem Qemu device.
> >
> > This device presents memory address range information to guest
> > which is backed by file backend type. It acts like persistent
> > memory device for KVM guest. Guest can
In commit 18a398f6a39df4b08ff86ac0d38384193ca5f4cc, ./configure on
FreeBSD incorrectly detects RDMA support, with the build subsequently
failing with:
/home/bcran/workspace/qemu/hw/rdma/vmw/pvrdma_cmd.c:19:10: fatal error:
'linux/types.h' file not found
#include
^~~
1 error
On Tue, Jul 24, 2018 at 10:54 PM, Dr. David Alan Gilbert <
dgilb...@redhat.com> wrote:
> * Zhang Chen (zhangc...@gmail.com) wrote:
> > On Tue, Jul 24, 2018 at 2:41 AM, Eric Blake wrote:
> >
> > > On 07/22/2018 02:33 PM, Zhang Chen wrote:
> > >
> > >> From: zhanghailiang
> > >>
> > >> If some
Hi QEMU developers,
I'm trying to inject some operations during the emulated device teardown
phase.
For an emulated PCIe device, such as NVMe or IVSHMEM, I notice that QEMU
registers PCIDeviceClass pc->init and pc->exit functions for that device.
->init() (e.g. nvme_init(), or ivshmem_init())
Actually implementing this fix causes a linux boot to crash. So there
may be something more to this. I will investigate more.
[ 892.294463] BUG: soft lockup - CPU#0 stuck for 347s! [swapper/0:1]
[ 892.490416] Modules linked in:
[ 892.635725]
[ 892.790816] CPU: 0 PID: 1 Comm: swapper/0 Not
Public bug reported:
Hello,
If you check the qemu/util/qemu-timer.c you will find the following
function:
597: int64_t qemu_clock_get_ns(QEMUClockType type)
598: {
602:switch (type) {
606:case QEMU_CLOCK_VIRTUAL:
607:if (use_icount) {
608:return
Public bug reported:
Consider the attached C file, which does a read-modify-write of the form
`add [mem], reg`, where `mem` points to a non-present page. In the
resulting page fault, the W/R bit is not set, while real hardware does
set this bit.
% gcc -m32 qemu-bug1.c&& ./a.out && qemu-i386
You have been subscribed to a public bug:
Hello,
If you check the qemu/util/qemu-timer.c you will find the following
function:
597: int64_t qemu_clock_get_ns(QEMUClockType type)
598: {
602:switch (type) {
606:case QEMU_CLOCK_VIRTUAL:
607:if (use_icount) {
608:
Thanks for the review and for the comments, Eric!
One quick remark: I do usually leave blank lines around inline replies,
but this time Thunderbird made it look as if there are blank lines when
I was writing, when apparently there were not. :]
Leonid.
On 07/25/2018 01:44 AM,
On 07/24/2018 05:20 PM, Leonid Bloch wrote:
meta-comment: a hint for more effective emails below
-
Differences from v2:
1) A separate patch for the grammar fix for 3.0
2) A separate patch for existing documentation fixes for 3.0
3) Separated back the iotests patch,
On 07/25/2018 01:17 AM, Leonid Bloch wrote:
This series introduces an option to calculate and allocate
automatically enough qcow2 L2 cache to cover the entire image.
Using cache that covers the entire image can benefit performance,
while having only a small memory overhead (just 1 MB for every
Signed-off-by: Leonid Bloch
---
docs/qcow2-cache.txt | 3 +++
qemu-options.hx | 10 ++
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/docs/qcow2-cache.txt b/docs/qcow2-cache.txt
index 8a09a5cc5f..3673f2be0e 100644
--- a/docs/qcow2-cache.txt
+++
An option "l2-cache-full" is introduced to automatically set the qcow2
L2 cache to a sufficient value for covering the entire image. The memory
overhead when using this option is not big (1 MB for each 8 GB of
virtual image size with the default cluster size) and it can noticeably
improve
Signed-off-by: Leonid Bloch
---
tests/qemu-iotests/103 | 6 ++
tests/qemu-iotests/103.out | 2 ++
tests/qemu-iotests/137 | 2 ++
tests/qemu-iotests/137.out | 2 ++
4 files changed, 12 insertions(+)
diff --git a/tests/qemu-iotests/103 b/tests/qemu-iotests/103
index
Signed-off-by: Leonid Bloch
---
block/qcow2.c | 2 +-
tests/qemu-iotests/103.out | 2 +-
tests/qemu-iotests/137.out | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/block/qcow2.c b/block/qcow2.c
index 6162ed8be2..ec9e6238a0 100644
--- a/block/qcow2.c
+++
This series introduces an option to calculate and allocate
automatically enough qcow2 L2 cache to cover the entire image.
Using cache that covers the entire image can benefit performance,
while having only a small memory overhead (just 1 MB for every 8 GB
of virtual image size with the default
On 23/07/18 00:06, Andrew Randrianasulu wrote:
Hello!
Currently I'm trying pre-releases of qemu, for avoiding situation when release
was too bugged (2.12, for my taste ..qemu-system-alpha was broken,
qemu-system-x86_64 -M q35 was broken ..)
using
qemu-system-ppc --version
QEMU emulator
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
third release candidate for the QEMU 3.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-3.0.0-rc2.tar.xz
Thanks! That was super helpful.
To confirm, support for IOMMU regions in the CPU's memory access path did
NOT exist prior to recent releases, correct? My QEMU version is 2.11, and I
believe you're up to 3.0 now. If that's the case, I may stick with the
"changing priorities" approach, since I know
On 07/24/2018 03:03 PM, Leonid Bloch wrote:
Signed-off-by: Leonid Bloch
---
docs/qcow2-cache.txt | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
I'd probably squash this with 3/5 introducing the option.
diff --git a/docs/qcow2-cache.txt b/docs/qcow2-cache.txt
On 07/24/2018 03:03 PM, Leonid Bloch wrote:
Signed-off-by: Leonid Bloch
---
docs/qcow2-cache.txt | 3 +++
qemu-options.hx | 15 +++
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/docs/qcow2-cache.txt b/docs/qcow2-cache.txt
index 8a09a5cc5f..9d261b7da9
On 24 July 2018 at 19:34, Dr. David Alan Gilbert (git)
wrote:
> From: "Dr. David Alan Gilbert"
>
> The following changes since commit 3bae150448dbd888a480f892ebbf01caec0d8329:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2018-07-24 15:26:01
On 07/24/2018 03:03 PM, Leonid Bloch wrote:
Subject line is rather vague; at a bare minimum, mentioning 'qcow2:'
might be helpful. But the maintainer can improve that. My suggestion:
qcow2: grammar fix for conflicting cache sizing
Signed-off-by: Leonid Bloch
---
block/qcow2.c
It's been a few months since this email thread died off. Has anyone
started working on a potential solution that would allow VCPU hotplug on
KVM/ARM ? Or is this a project that is still waiting for an owner who
has the time and inclination to get started?
Thanks,
-Maran
On 2/27/2018 5:21 AM,
An option "l2-cache-full" is introduced to automatically set the qcow2
L2 cache to a sufficient value for covering the entire image. The memory
overhead when using this option is not big (1 MB for each 8 GB of
virtual image size with the default cluster size) and it can noticeably
improve
Signed-off-by: Leonid Bloch
---
tests/qemu-iotests/103 | 6 ++
tests/qemu-iotests/103.out | 2 ++
tests/qemu-iotests/137 | 2 ++
tests/qemu-iotests/137.out | 2 ++
4 files changed, 12 insertions(+)
diff --git a/tests/qemu-iotests/103 b/tests/qemu-iotests/103
index
Signed-off-by: Leonid Bloch
---
docs/qcow2-cache.txt | 3 +++
qemu-options.hx | 15 +++
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/docs/qcow2-cache.txt b/docs/qcow2-cache.txt
index 8a09a5cc5f..9d261b7da9 100644
--- a/docs/qcow2-cache.txt
+++
Signed-off-by: Leonid Bloch
---
docs/qcow2-cache.txt | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/docs/qcow2-cache.txt b/docs/qcow2-cache.txt
index 9d261b7da9..ea61585a4b 100644
--- a/docs/qcow2-cache.txt
+++ b/docs/qcow2-cache.txt
@@ -110,11 +110,12 @@
This series introduces an option to calculate and allocate
automatically enough qcow2 L2 cache to cover the entire image.
Using cache that covers the entire image can benefit performance,
while having only a small memory overhead (just 1 MB for every 8 GB
of virtual image size with the default
Signed-off-by: Leonid Bloch
---
block/qcow2.c | 2 +-
tests/qemu-iotests/103.out | 2 +-
tests/qemu-iotests/137.out | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/block/qcow2.c b/block/qcow2.c
index 6162ed8be2..ec9e6238a0 100644
--- a/block/qcow2.c
+++
On 24 July 2018 at 16:13, Eric Blake wrote:
> On 07/24/2018 09:25 AM, Stefan Hajnoczi wrote:
>>
>> The following changes since commit
>> 768cef2974fb1fa30dd188b043ea737e13fea477:
>>
>>Merge remote-tracking branch
>> 'remotes/ehabkost/tags/x86-next-pull-request' into staging (2018-07-24
>>
On 07/24/2018 10:29 PM, Yuval Shaia wrote:
On Tue, Jul 24, 2018 at 03:08:10PM +0300, Marcel Apfelbaum wrote:
Hi Yuval,
On 07/16/2018 10:40 AM, Yuval Shaia wrote:
There are certain operations that are well considered as part of device
configuration while others are needed only when "start"
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> +case NM_SB16:
> +{
> +int rt = decode_gpr_gpr3_src_store(
> + NANOMIPS_EXTRACT_RD(ctx->opcode));
Shadowed variable.
> +case NM_SH16:
> +
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> +case NM_ADDIUPC:
> +if (rt != 0) {
> +int32_t offset = sextract32(ctx->opcode, 0, 1) << 21
> +| extract32(ctx->opcode, 1, 20) << 1;
> +target_long addr = addr_add(ctx,
On Tue, Jul 24, 2018 at 03:08:10PM +0300, Marcel Apfelbaum wrote:
> Hi Yuval,
>
> On 07/16/2018 10:40 AM, Yuval Shaia wrote:
> > There are certain operations that are well considered as part of device
> > configuration while others are needed only when "start" command is
> > triggered by the
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> +/* make sure instructions are on a halfword boundary */
> +if (ctx->base.pc_next & 0x1) {
> +TCGv tmp = tcg_const_tl(ctx->base.pc_next);
> +tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
> +
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add some basic utility functions and macros for nanoMIPS decoding
> engine.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add empty body and invocation of decode_nanomips_opc() if the bit
> ISA_NANOMIPS32 is set in ctx->insn_flags.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
Hi Cornelia,
> > >
> > > Would you be able to do an s390 BIOS build for this one as well?
> >
> > Sure, will do a build for 2.12-stable.
>
> Here we go:
>
> The following changes since commit e8488edcb3768f08cda7c3cc00def6b1b2f6c615:
>
>
On 24 July 2018 at 17:44, Daniel P. Berrangé wrote:
> The following changes since commit 3bae150448dbd888a480f892ebbf01caec0d8329:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2018-07-24 15:26:01 +0100)
>
> are available in the Git repository at:
On 24 July 2018 at 18:38, Aleksandar Markovic wrote:
>> From: Peter Maydell
>> Sent: Tuesday, July 24, 2018 7:21 PM
>
>> On 24 July 2018 at 18:04, Aleksandar Markovic
>> wrote:
>> > From: Aleksandar Markovic
>>
>> Are you trying to get these into 3.0 or aiming for 3.1?
>> Time is running out
On 07/24/2018 04:59 AM, Peter Maydell wrote:
> Whene we raise a synchronous exception, if HCR_EL2.TGE is set then
> exceptions targeting NS EL1 must be redirected to EL2. Implement
> this in raise_exception() -- all synchronous exceptions go through
> this function.
>
> (Asynchronous exceptions
On 07/24/2018 04:59 AM, Peter Maydell wrote:
> The IMO, FMO and AMO bits in HCR_EL2 are defined to "behave as
> 1 for all purposes other than direct reads" if HCR_EL2.TGE
> is set and HCR_EL2.E2H is 0, and to "behave as 0 for all
> purposes other than direct reads" if HCR_EL2.TGE is set
> and
On 07/24/2018 04:59 AM, Peter Maydell wrote:
> Some debug registers can be trapped via MDCR_EL2 bits TDRA, TDOSA,
> and TDA, which we implement in the functions access_tdra(),
> access_tdosa() and access_tda(). If MDCR_EL2.TDE or HCR_EL2.TGE
> are 1, the TDRA, TDOSA and TDA bits should behave as
On 07/24/2018 04:59 AM, Peter Maydell wrote:
> One of the required effects of setting HCR_EL2.TGE is that when
> SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for
> all purposes except direct reads. That is, it effectively disables
> the MMU for the NS EL0/EL1 translation regime.
>
From: Peter Xu
The only possible change of last_byte is when it reaches the edge.
Setting it every time might let last_byte contain an invalid data when
memory corruption is detected, then the check of the next byte will be
incorrect. For example, a single page corruption at address 0x14ad000
From: "Dr. David Alan Gilbert"
The following changes since commit 3bae150448dbd888a480f892ebbf01caec0d8329:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into
staging (2018-07-24 15:26:01 +0100)
are available in the Git repository at:
On 07/24/2018 04:59 AM, Peter Maydell wrote:
> If the "trap general exceptions" bit HCR_EL2.TGE is set, we
> must mask all virtual interrupts (as per DDI0487C.a D1.14.3).
> Implement this in arm_excp_unmasked().
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/cpu.h | 6 --
> 1 file
From: Lidong Chen
migrate_fd_connect duplicate initialize expected_downtime and cleanup_bh.
Signed-off-by: Lidong Chen
Message-Id: <1532434585-14732-2-git-send-email-lidongc...@tencent.com>
Reviewed-by: Juan Quintela
Signed-off-by: Dr. David Alan Gilbert
---
migration/migration.c | 2 --
1
On 07/24/2018 10:04 AM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add ability to target platforms to individually include user-mode
> support for system calls from "stat" group of system calls.
>
> This change is related to new nanoMIPS platform in the sense that
> it supports
From: "Dr. David Alan Gilbert"
Fix outgoing migration which was crashing in
vmstate_hda_audio_stream_buf_needed, I think the problem
is that we have room for upto 4 streams in the array but only
use 2, when we come to try and save the state of the unused
streams we hit st->state == NULL.
Fixes:
From: Peter Xu
Postcopy recovery won't work well with release-ram capability since
release-ram will drop the page buffer as long as the page is put into
the send buffer. So if there is a network failure happened, any page
buffers that have not yet reached the destination VM but have already
From: Peter Xu
We shouldn't update the received bitmap if we're the source VM. This
fixes a breakage when release-ram is enabled on postcopy.
Signed-off-by: Peter Xu
Message-Id: <20180723123305.24792-2-pet...@redhat.com>
Reviewed-by: Juan Quintela
Signed-off-by: Dr. David Alan Gilbert
---
From: "Dr. David Alan Gilbert"
We've been getting the warning:
migration_iteration_finish: Unknown ending state 2
on a cancel.
I think that's originally due to 39b9e17905c; although
I've only seen the warning, I think that in some cases
that we could find the VM stays paused after a cancel
From: Peter Xu
I would guess it won't happen normally, but this should ease Coverity.
>>> CID 1394385: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
>>> Potentially overflowing expression "pages->used * 8192U" with type
>>> "unsigned int" (32 bits, unsigned) is evaluated using
From: Stefan Markovic
Add new linux user mode configuration for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
configure | 13 -
default-configs/nanomips-linux-user.mak | 1 +
2
From: Dimitrije Nikolic
Add target_cpu.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_cpu.h | 21 +
1 file changed, 21 insertions(+)
create mode 100644
From: Aleksandar Rikalo
Add fcntl-related constants and structures for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_fcntl.h | 38 ++
1 file changed, 38
From: Aleksandar Rikalo
Add termbits.h header for nanoMIPS. Reuse MIPS' termbits.h as
the functionalities are almost identical.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/termbits.h | 4
On Tue, Jul 24, 2018 at 05:28:44PM +0200, Igor Mammedov wrote:
> On Tue, 24 Jul 2018 09:39:16 -0300
> Eduardo Habkost wrote:
>
> > On Tue, Jul 24, 2018 at 02:29:49PM +0200, Igor Mammedov wrote:
> > > On Mon, 23 Jul 2018 16:31:45 -0300
> > > Eduardo Habkost wrote:
> > >
> > > > The ACPI
From: Stefan Markovic
Add definition of the first nanoMIPS processor in QEMU.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate_init.inc.c | 40
1 file changed, 40 insertions(+)
From: Aleksandar Rikalo
Amend sigaction syscall support for nanoMIPS. This must be done
since nanoMIPS' signal handling is different than MIPS' signal
handling.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/syscall.c | 2 +-
From: Dimitrije Nikolic
This header includes common elf header, and adds cpu_get_model()
function.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_elf.h | 14 ++
1 file changed, 14 insertions(+)
From: James Hogan
nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit
of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being
read as e.g. 0xbfc1, and prevents writing to the PC clearing
MIPS_HFLAG_M16.
Signed-off-by: James Hogan
Signed-off-by: Yongbok
From: Dimitrije Nikolic
Amend regular MIPS' cpu_loop.c to include nanoMIPS support.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 8 +++-
linux-user/nanomips/cpu_loop.c | 1 +
2 files changed, 8
From: Dimitrije Nikolic
Add target_structs.h header for nanoMIPS, that redirects to the
corresponding MIPS header.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_structs.h | 1 +
1 file changed, 1
From: Dimitrije Nikolic
Add signal.c as a dredirection of regular mips' signal.c, but also
amend regular mips' signal.c. this is done to avoid the duplication
of large pieces of code.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
From: Yongbok Kim
Fix ERET/ERETNC so that ADEL exception can be raised.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/op_helper.c | 11 ++-
1 file changed, 10 insertions(+), 1
From: Aleksandar Rikalo
Add sockbits.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/sockbits.h | 1 +
1 file changed, 1 insertion(+)
create mode 100644 linux-user/nanomips/sockbits.h
diff
From: Yongbok Kim
Config3.ISAOnExc is read only in nanoMIPS.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/op_helper.c
On 07/24/2018 04:47 AM, Fam Zheng wrote:
> Something has locked /dev/null on my system (I still don't know what to do
> with
> the annoying incapability of lslocks, or more precisely /proc/locks, on
> inspecting OFD lock information), and as a result 226 cannot pass due to the
> unexpected
From: Aleksandar Rikalo
Update constants and structures related to syscall support in
nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/syscall_defs.h | 57 ++-
1 file
From: Aleksandar Markovic
Update BadInstr, BadInstrP,and BadInstrX registers for nanoMIPS.
The same support for pre-nanoMIPS remains unimplemented.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c | 25
From: Stefan Markovic
Add XML support files for GDB for nanoMIPS.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
MAINTAINERS| 3 ++-
gdb-xml/nanomips-cp0.xml | 13 +
gdb-xml/nanomips-cpu.xml | 44
From: Paul Burton
Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that
they are setup in the MIPS32 bootloader. This is necessary for Linux to
be able to access peripherals, including the UART.
Signed-off-by: Paul Burton
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar
From: Yongbok Kim
Implement nanoMIPS LLWP and SCWP instruction pair.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 25 ---
target/mips/cpu.h | 2 +
target/mips/helper.h | 2 +
From: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
hw/mips/mips_malta.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index d1a7c1f..8bb1686 100644
---
From: Matthew Fortune
Added very very basic nanoMIPS boot code but this is hacked in
unconditionally currently.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
hw/mips/mips_malta.c | 75 +++-
1
From: Aleksandar Rikalo
Add target_syscall.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_syscall.h | 30 ++
1 file changed, 30 insertions(+)
create mode
From: Yongbok Kim
Add emulation of various nanoMIPS load and store instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 271
From: Aleksandar Markovic
nanoMIPS is always NaN2008 compliant, and rules for checking
FCR31's NAN2008 bit are obsoleted.
Reviewed-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 3 +++
1 file changed, 3 insertions(+)
From: Aleksandar Markovic
Starting from nanoMIPS introduction, machine variant can be
EM_MIPS or EM_NANOMIPS.
Reviewed-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Aleksandar Rikalo
nanoMIPS signal handling is much closer to the signal handling in
other mainstream platforms that to the signal handling in preceding
MIPS platforms.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
From: James Hogan
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction
is similar to the MIPS r6 ALIGN instruction, except that it counts
the other way and in bits instead of bytes. We therefore generalise
gen_align() function into a new gen_align_bits() function (which
counts in
From: James Hogan
ERET and ERETNC shouldn't clear MIPS_HFLAG_M16 for nanoMIPS since there
is no ISA bit, so fix set_pc() to skip the hflags update.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar
From: Matthew Fortune
ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition. The flag has_isa_mode has the
key role in the implementation.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
From: Aleksandar Rikalo
Add syscall numbers for nanoMIPS. nanoMIPS redefines its ABI
compared to preceding MIPS architectures, and its set of
supported system calls is significantly different.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
From: Yongbok Kim
Add emulation of nanoMIPS instructions that are situated in pool32a0.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 190
From: James Hogan
We shouldn't set the ISA bit in CP0_EPC for nanoMIPS.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 3.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 751
1 file changed, 751 insertions(+)
diff --git
From: Aleksandar Markovic
Add nanoMIPS-related values in ELF header fields as specified in
nanoMIPS' "ELF ABI Supplement".
Acked-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 20
1 file changed, 20
From: Yongbok Kim
Add emulation of basic floating point arithmetic for nanoMIPS.
Reviewed-by: Richard Henderson
Reviewed-by: Aleksandar Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 300
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 1.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 525
1 file changed, 525 insertions(+)
diff --git
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 2.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
From: James Hogan
We shouldn't clear M16 mode when entering an interrupt on nanoMIPS,
otherwise we'll start interpreting the code as normal MIPS code.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
From: Yongbok Kim
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 66
From: Yongbok Kim
Add emulation of various flavors of nanoMIPS branch instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 277
From: Stefan Markovic
Add testing Config0.WR bit into watch exception handling logic.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c| 12 +++-
target/mips/translate.c | 22 --
2 files changed, 27 insertions(+), 7
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