On Sun, Aug 19, 2018 at 12:35:09AM -0400, John Arbuckle wrote:
> When the user moves the mouse and moves the scroll wheel at the same
> time, the mouse cursor's movement becomes erratic in Windows 3.1. With
> this patch if the mouse is in ps/2 mode and the scroll wheel is used,
> the command queue
Hi,
> > We don't copy any state. It is rather pointless, even for save/resume on
> > the
> > same machine we don't know what state the usb device has and whenever it is
> > still in the state the guest has left it.
> I have tried stop/cont a vm with host-usb device during coping large
>
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1470481
Title:
qemu-img
Failed memory transactions should raise exceptions 14 (for fetch) or 15
(for load/store) with XEA2.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile| 1 +
tests/tcg/xtensa/test_phys_mem.S | 68
2 files changed, 69 insertions(+)
create
On Fri, Aug 10, 2018 at 04:41:54PM +1000, David Gibson wrote:
> On Fri, Aug 10, 2018 at 07:37:12AM +0200, Hervé Poussineau wrote:
> > OpenBIOS gained 40p support in 5b20e4cacecb62fb2bdc6867c11d44cddd77c4ff
> > Use it, instead of relying on an unmaintained and very limited firmware.
> >
> >
Hi Marcel,
On 8/18/2018 12:10 AM, Marcel Apfelbaum wrote:
Hi Jing,
On 08/16/2018 12:28 PM, Jing Liu wrote:
Clean up the PCI config space of resource reserve capability.
Signed-off-by: Jing Liu
---
hw/pci/pci_bridge.c | 9 +
include/hw/pci/pci_bridge.h | 1 +
2 files
On Fri, Aug 17, 2018 at 03:52:20PM +0200, Marc-André Lureau wrote:
> Hi,
>
> In commit 25679e5d58e "chardev: tcp: postpone async connection setup"
> (and its follow up 99f2f54174a59), Peter moved chardev socket
> connection to machine_done event. However, chardev created later will
> no longer
Hi Marcel,
On 8/18/2018 12:18 AM, Marcel Apfelbaum wrote:
Hi Jing,
On 08/16/2018 12:28 PM, Jing Liu wrote:
This patch serial is about PCI resource reserve capability.
First patch refactors the resource reserve fields in GenPCIERoorPort
structure out to another new structure, called
Signed-off-by: Max Filippov
---
target/xtensa/cpu.c | 2 +-
target/xtensa/cpu.h | 7 ---
target/xtensa/op_helper.c | 12 +++-
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 590813d4f7b9..a54dbe42602d
> -Original Message-
> From: gerd hoffmann [mailto:kra...@redhat.com]
> Sent: Friday, August 17, 2018 2:08 PM
> To: CheneyLin
> Cc: linzhecheng ; wangxin (U)
> ; qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH] usb-host: insert usb device into hostdevs to
> be scaned
>
> > >
On Thu, 08/16 04:20, Max Reitz wrote:
> No, the real issue is that dd is still not implemented just as a
> frontend to convert. Which it should be. I'm not sure dd was a very
> good idea from the start, and now it should ideally be a frontend to
> convert.
>
> (My full opinion on the matter: dd
- move register counting to xtensa/gdbstub.c
- add symbolic names for register types and flags from GDB and use them
in register counting and access functions.
Signed-off-by: Max Filippov
---
Changes v1->v2:
- add missing dereference to the n_regs/n_core_regs in xtensa_count_regs
Signed-off-by: Laurent Vivier
Message-Id: <20180814161904.12216-4-laur...@vivier.eu>
---
linux-user/syscall.c | 48
1 file changed, 48 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index da1fcaf4ca..424296d1a1 100644
---
This fixes java in a linux-user chroot:
$ java --version
qemu-sh4: .../accel/tcg/cpu-exec.c:634: cpu_loop_exec_tb: Assertion
`use_icount' failed.
qemu: uncaught target signal 6 (Aborted) - core dumped
Aborted (core dumped)
In gen_conditional_jump() in the GUSA_EXCLUSIVE part, we must
If recvmsg()/recvfrom() are used with the MSG_TRUNC flag, they return the
real length even if it was longer than the passed buffer.
So when we translate the buffer we must check we don't go beyond the
end of the buffer.
Bug: https://github.com/vivier/qemu-m68k/issues/33
Reported-by: John Paul
The following changes since commit 0abaa41d936becd914a16ee1fe2a981d96d19428:
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request'
into staging (2018-08-17 09:46:00 +0100)
are available in the Git repository at:
git://github.com/vivier/qemu.git
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Message-Id: <20180801102944.23457-1-laur...@vivier.eu>
---
scripts/qemu-binfmt-conf.sh | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/scripts/qemu-binfmt-conf.sh
Add RTA_PREF and RTA_CACHEINFO.
Fix following errors when we start gedit:
Unknown host RTA type: 12
Unknown host RTA type: 20
Signed-off-by: Laurent Vivier
Message-Id: <20180814161904.12216-3-laur...@vivier.eu>
---
linux-user/syscall.c | 19 +++
1 file changed, 19
sparc32plus has 64bit long type but only 32bit virtual address space.
For instance, "apt-get upgrade" failed because of a mmap()/msync()
sequence.
mmap() returned 0xff252000 but msync() used g2h(0xff252000)
to find the host address. The "(target_ulong)" in g2h() doesn't fix the
address
On 2018-08-16 20:58, Laurent Vivier wrote:
> Le 11/08/2018 à 17:26, Richard Henderson a écrit :
> > On 08/11/2018 01:23 AM, Laurent Vivier wrote:
> >> This fixes java in a linux-user chroot:
> >> $ java --version
> >> qemu-sh4: .../accel/tcg/cpu-exec.c:634: cpu_loop_exec_tb: Assertion
> >>
On 19 August 2018 at 18:44, Richard Henderson
wrote:
> On 08/19/2018 03:19 AM, Peter Maydell wrote:
>> Hi; I've been playing around this weekend with writing a QEMU
>> model for a music player I have (an XDuoo X3). This has a MIPS
>> SoC, and its boot process is that the SoC's boot rom loads the
From: Andrew Oates
Currently call gates are always treated as 32-bit gates. In IA-32e mode
(either compatibility or 64-bit submode), system segment descriptors are
always 64-bit. Treating them as 32-bit has the expected unfortunate
effect: only the lower 32 bits of the offset are loaded, the
On 08/19/2018 03:19 AM, Peter Maydell wrote:
> Hi; I've been playing around this weekend with writing a QEMU
> model for a music player I have (an XDuoo X3). This has a MIPS
> SoC, and its boot process is that the SoC's boot rom loads the
> guest binary into the CPU's icache and dcache (by playing
Hello, could you tell me how to run Linux on QEMU Mainstone II machine? I
took kernel from there:
http://ftp.arm.linux.org.uk/pub/armlinux/people/xscale/mainstone/, but I do
not know what to do with rootfs (it is jffs2). How to add it into memory
bank to be visible to Linux inside QEMU? As for now
On 08/14/2018 09:56 PM, Eric Blake wrote:
I was trying to test NBD fleecing by copying subsets of one
file to another, and had the idea to use:
$ export NBD drive to be fleeced on port 10809
$ qemu-img create -f qcow2 copy $size
$ qemu-nbd -f qcow2 -p 10810 copy
$ qemu-img dd -f raw -O raw
On 19 August 2018 at 13:54, Martin Schroeder via Qemu-devel
wrote:
> Is it possible to instantiate multiple CPUs of different architectures
> and simuate them with different images at the same time? Some examples
> include ARM socs with m3/m4 coprocessor core but also boards with
> multiple
Is it possible to instantiate multiple CPUs of different architectures
and simuate them with different images at the same time? Some examples
include ARM socs with m3/m4 coprocessor core but also boards with
multiple processors where it is desirable to connect the chips over
for example virtual
Hi; I've been playing around this weekend with writing a QEMU
model for a music player I have (an XDuoo X3). This has a MIPS
SoC, and its boot process is that the SoC's boot rom loads the
guest binary into the CPU's icache and dcache (by playing tricks
with the cache tag bits so that it appears to
v1: https://lists.gnu.org/archive/html/qemu-devel/2018-08/msg02179.html
Changes since v1:
- Rebase on master
- Add David's Acked-by tag to the spapr patch
- Add 2 patches on QLIST_{EMPTY,REMOVE}_RCU
- Add some fixes for test-rcu-list. I wanted to be able to get no
races with ThreadSanitizer,
Signed-off-by: Emilio G. Cota
---
tests/test-rcu-list.c | 15 +++
tests/test-rcu-tailq.c | 2 ++
tests/Makefile.include | 4
3 files changed, 21 insertions(+)
create mode 100644 tests/test-rcu-tailq.c
diff --git a/tests/test-rcu-list.c b/tests/test-rcu-list.c
index
Signed-off-by: Emilio G. Cota
---
include/qemu/rcu_queue.h | 66
1 file changed, 66 insertions(+)
diff --git a/include/qemu/rcu_queue.h b/include/qemu/rcu_queue.h
index e0395c989a..904b3372dc 100644
--- a/include/qemu/rcu_queue.h
+++
Signed-off-by: Emilio G. Cota
---
tests/test-rcu-list.c| 17 +
tests/test-rcu-simpleq.c | 2 ++
tests/Makefile.include | 4
3 files changed, 23 insertions(+)
create mode 100644 tests/test-rcu-simpleq.c
diff --git a/tests/test-rcu-list.c b/tests/test-rcu-list.c
So that we can test other implementations.
Signed-off-by: Emilio G. Cota
---
tests/test-rcu-list.c | 42 ++
1 file changed, 30 insertions(+), 12 deletions(-)
diff --git a/tests/test-rcu-list.c b/tests/test-rcu-list.c
index dc58091996..9bd11367a0 100644
Instead of declaring it volatile.
Signed-off-by: Emilio G. Cota
---
tests/test-rcu-list.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tests/test-rcu-list.c b/tests/test-rcu-list.c
index 1514d7ec97..b4ed130081 100644
--- a/tests/test-rcu-list.c
+++
Signed-off-by: Emilio G. Cota
---
tests/test-rcu-list.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/tests/test-rcu-list.c b/tests/test-rcu-list.c
index b4ed130081..dc58091996 100644
--- a/tests/test-rcu-list.c
+++ b/tests/test-rcu-list.c
@@ -93,7 +93,7 @@
This paves the way for implementing the CPU list with an RCU list,
which cannot be traversed in reverse order.
Note that this is the only caller of CPU_FOREACH_REVERSE.
Acked-by: David Gibson
Signed-off-by: Emilio G. Cota
---
hw/ppc/spapr.c | 16 +++-
1 file changed, 15
Signed-off-by: Emilio G. Cota
---
include/qemu/rcu_queue.h | 65
1 file changed, 65 insertions(+)
diff --git a/include/qemu/rcu_queue.h b/include/qemu/rcu_queue.h
index 6881ea5274..e0395c989a 100644
--- a/include/qemu/rcu_queue.h
+++
It's unnecessary because the pointer isn't dereferenced.
Signed-off-by: Emilio G. Cota
---
include/qemu/rcu_queue.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/qemu/rcu_queue.h b/include/qemu/rcu_queue.h
index dd7b3be043..6881ea5274 100644
---
To avoid undefined behaviour.
Signed-off-by: Emilio G. Cota
---
include/qemu/rcu_queue.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/qemu/rcu_queue.h b/include/qemu/rcu_queue.h
index 01be77407b..dd7b3be043 100644
--- a/include/qemu/rcu_queue.h
+++
Iterating over the list without using atomics is undefined behaviour,
since the list can be modified concurrently by other threads (e.g.
every time a new thread is created in user-mode).
Fix it by implementing the CPU list as an RCU QTAILQ. This requires
a little bit of extra work to traverse
On Fri, Aug 17, 2018 at 19:53:40 +0200, Paolo Bonzini wrote:
> On 15/08/2018 02:34, Emilio G. Cota wrote:
> > On Tue, Aug 14, 2018 at 08:26:54 +0200, Paolo Bonzini wrote:
> >> On 13/08/2018 18:38, Emilio G. Cota wrote:
> >>> Fix it by implementing the CPU list as an RCU QLIST. This requires
> >>>
Am 18.08.2018 um 22:51 schrieb Howard Spoelstra:
> On Sat, Aug 18, 2018 at 9:09 PM, Stefan Weil wrote:
>> Am 17.08.2018 um 09:32 schrieb David Hildenbrand:
>>> No being a win32/mingw expert, Stefan any idea?
>>
>>
>> I'd try a debug build (configure [...] --enable-debug).
>>
>> My installers
I tried it according to your method, but I have some problems. My host is
centos 7.2 with the TPM 2.0 hardware and qemu v2.10.2. The driver for the TPM
2.0 hardware is crb device，Execute lsmod to view the tpm 2.0 driver information
as follows：
[root@localhost BUILD]# lsmod | grep tpm
tpm_crb
On 18/08/18 21:21, Mark Cave-Ayland wrote:
> Hi all,
>
> As part of testing my OpenBIOS virtio-blk implementation, I've been
> trying to use it under the 40p machine and have some questions related
> to how address spaces are interpreted.
>
> The 40p PCI address space is aliased onto the CPU
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