This kind of ELF for the R5900 relies on an IEEE 754-1985 compliant FPU.
The R5900 FPU hardware is noncompliant and it is therefore emulated in
software by the Linux kernel. QEMU emulates a compliant FPU accordingly.
Signed-off-by: Fredrik Noring
---
linux-user/mips/target_elf.h | 3 +++
1 file
Sources [1][2] indicate that the Emotion Engine was designed by Toshiba
and licensed to Sony. Others [3][4][5] claim it was a joint effort. It
therefore makes sense to refer to the CPU as "Toshiba/Sony R5900".
[1]
http://cs.nyu.edu/courses/spring02/V22.0480-002/projects/aldrich/emotionengine.ppt
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c
The primary purpose of this change is to support programs compiled by
GCC for the R5900 target and thereby run R5900 Linux distributions, for
example Gentoo.
GCC in version 7.3, by itself, by inspection of the GCC source code
and inspection of the generated machine code, for the R5900 target,
The Linux kernel traps certain reserved instruction exceptions to
emulate the corresponding instructions. QEMU is the kernel in user
mode, so those traps are emulated by accepting the instructions.
This change adds the function check_insn_opc_user_only to signal a
reserved instruction exception
The three-operand MULT and MULTU are the only R5900 specific
instructions emitted by GCC 7.3. The R5900 also implements the three-
operand MADD and MADDU instructions, but they are omitted in QEMU for
now since they are absent in programs compiled by current GCC versions.
Likewise, the R5900
The primary purpose of these changes is to support programs compiled
by GCC for the R5900 target and thereby run R5900 Linux distributions,
for example Gentoo.
GCC in version 7.3, by itself, by inspection of the GCC source code
and inspection of the generated machine code, for the R5900 target,
The R5900 implements the 64-bit MIPS III instruction set except DMULT,
DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV instructions MOVN,
MOVZ and PREF are implemented. It has the R5900 specific three-operand
instructions MADD, MADDU, MULT and MULTU as well as pipeline 1 versions
MULT1,
Public bug reported:
When running OpenBSD-current as a guest, the following assertion is hit
after a few seconds, resulting in the virtual machine to crash:
```
qemu-system-x86_64:
/build/qemu/src/qemu-3.0.0/include/exec/memory_ldst_cached.inc.h:85:
address_space_stw_le_cached: Assertion `addr
On 09/28/18 19:07, Philippe Mathieu-Daudé wrote:
> On 28/09/2018 12:51, Laszlo Ersek wrote:
>> Figuring out the options is complicated enough (for management tools
>> as well) that Daniel made us define a metadata schema for describing
>> firmware packages. Please see:
>>
>>
Fixing cache-clean-interval documentation following the recent change to
a default of 600 seconds on supported plarforms (only Linux currently).
Signed-off-by: Leonid Bloch
---
docs/qcow2-cache.txt | 19 +--
qapi/block-core.json | 3 ++-
qemu-options.hx | 3 ++-
3 files
Hi Philippe,
> We could manage to build a docker mips-r5900 cross-compiler image, such:
> https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg06908.html
>
> But we'll need your patches.
The attached patches for GAS and GCC are provisional and intended to enable
and simplify the use of a
On 27 September 2018 at 18:30, Peter Maydell wrote:
> On 27 September 2018 at 11:23, Hongbo Zhang wrote:
>> I would mention that there are some issues in the base qemu tree to
>> boot this (and also 'virt') machine.
>>
>> The MPIDR isn't emulated well, currently only 4 cores on one cluster
>>
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