Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20181031121443.605-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PATCH v2 0/3] decodetree improvments
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
> On Thu, Nov1, 2018 at 09:45 AM, Jim Mattson wrote:
>> On Thu, Nov 1, 2018 at 8:56 AM, Dr. David Alan Gilbert
>> wrote:
>> So if I have matching host kernels it should always work?
>> What happens if I upgrade the source kernel to increase it's maximum
>> nested size, can I force it to keep
On Fri, Nov 02, 2018 at 11:00:24AM +0800, Fei Li wrote:
>
>
> On 11/02/2018 10:37 AM, Peter Xu wrote:
> > On Thu, Nov 01, 2018 at 06:17:11PM +0800, Fei Li wrote:
> > > Set the migration state to "failed" instead of "setup" when failing
> > > to send packet via some channel.
> > Could you please
On 11/02/2018 10:37 AM, Peter Xu wrote:
On Thu, Nov 01, 2018 at 06:17:11PM +0800, Fei Li wrote:
Set the migration state to "failed" instead of "setup" when failing
to send packet via some channel.
Could you please provide more information in the commit message?
E.g., what will happen if
On 11/1/18 5:12 PM, Philippe Mathieu-Daudé wrote:
Hi,
This series is a mix of a previous work I had for the raspi, and a patch from
Guenter: https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg03153.html
The final patch keep Guenter ideas and comments, but is mostly a rewrite.
I dropped
On Thu, Nov 01, 2018 at 06:17:12PM +0800, Fei Li wrote:
[...]
> @@ -1339,7 +1339,7 @@ bool multifd_recv_all_channels_created(void)
> }
>
> /* Return true if multifd is ready for the migration, otherwise false */
> -bool multifd_recv_new_channel(QIOChannel *ioc)
> +bool
On Thu, Nov 01, 2018 at 06:17:10PM +0800, Fei Li wrote:
> When multifd is used during migration, a segmentaion fault will
> occur in the source when multifd_save_cleanup() is called again if
> the multifd_send_state has been freed in earlier error handling. This
> can happen when
On Thu, Nov 01, 2018 at 06:17:11PM +0800, Fei Li wrote:
> Set the migration state to "failed" instead of "setup" when failing
> to send packet via some channel.
Could you please provide more information in the commit message?
E.g., what will happen if without this patch? Will it crash the
source
On 2018/10/31 上午8:50, Zhang Chen wrote:
The original code just follow the TCP state diagram,
but in this case, we can skip the TCPS_TIME_WAIT state to simplify
the implementation.
Signed-off-by: Zhang Chen
---
net/filter-rewriter.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20181031141925.30026-1-mdr...@linux.vnet.ibm.com
Subject: [Qemu-devel] [PULL v3 00/24] qemu-ga patch queue for soft-freeze
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
Currently, the nvme_cmb_ops mr doesn't check the addr and size.
This can lead an oob access issue. This is triggerable in the guest.
Add check to avoid this issue.
Fixes CVE-2018-16847.
Reported-by: Li Qiang
Reviewed-by: Paolo Bonzini
Signed-off-by: Li Qiang
---
hw/block/nvme.c | 7 +++
On 2018-10-30 13:39, Laurent Vivier wrote:
> Le 30/10/2018 à 14:12, Mark Cave-Ayland a écrit :
>> On 30/10/2018 12:49, Laurent Vivier wrote:
>>
>>> Le 30/10/2018 à 12:48, Mark Cave-Ayland a écrit :
On 30/10/2018 08:15, Richard Henderson wrote:
> On 10/29/18 1:39 PM, Mark Cave-Ayland
After this patch elf2dmp can be built by mingw64 for Windows hosts.
Signed-off-by: Viktor Prutyanov
---
Makefile | 4 ++--
contrib/elf2dmp/kdbg.h | 12
contrib/elf2dmp/main.c | 27 +++
contrib/elf2dmp/pdb.c | 4 +++-
contrib/elf2dmp/pdb.h |
Replace POSIX mmap with GLib g_mapped_file_new to make elf2dmp
cross-paltform. After this patch there are no direct POSIX calls.
Signed-off-by: Viktor Prutyanov
---
Makefile | 2 +-
contrib/elf2dmp/Makefile.objs | 2 +-
contrib/elf2dmp/addrspace.c | 7 ---
In most cases, it is more convenient to convert a dump on the same machine
on which the analysis is performed. Because of WinDbg, the analysis of guest
Windows problems needs Windows host anyway, so it is useful to have dump
convertion tool near the debugger.
After these patches elf2dmp can be
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c41ea5ed3f..a76d047659 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -684,6 +684,7 @@ F: hw/arm/microbit.c
F: include/hw/arm/nrf51_soc.h
Raspberry Pi
+R:
On 1/11/18 22:57, Richard Henderson wrote:
When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, aa32_arm_div will not be supported either.
Signed-off-by: Richard Henderson
---
"Tested" on an APM Mustang, which does support AArch32. I'm not
sure, off
Add basic support for BCM283x CPRMAN. Provide support for reading and
writing CPRMAN registers and initialize registers with sensible default
values. During runtime retain any written values.
Basic CPRMAN support is necessary and sufficient to boot Linux on raspi2
and raspi3 systems.
Without
Base addresses and sizes taken from the "BCM2835 ARM Peripherals"
datasheet from February 06 2012:
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/bcm2835_peripherals.c | 26 ++
Hi,
This series is a mix of a previous work I had for the raspi, and a patch from
Guenter: https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg03153.html
The final patch keep Guenter ideas and comments, but is mostly a rewrite.
I dropped the A2W code from this work, it doesn't seems
The UART1 is part of the AUX peripheral,
the PCM_CLOCK (yet unimplemented) is part of the CPRMAN.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/bcm2835_peripherals.c| 2 +-
include/hw/arm/raspi_platform.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/bcm2835_property.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
index 145427ae0f..5d332324bd 100644
--- a/hw/misc/bcm2835_property.c
+++ b/hw/misc/bcm2835_property.c
@@ -121,6
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/bcm2835_aux.c | 2 +-
hw/intc/bcm2836_control.c | 4 ++--
hw/misc/bcm2835_property.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c
index 0364596c55..9632e8972c 100644
So far the Raspi machines use the BCM2836 SoC which includes
a BCM2835 for the peripherals.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f2360efe3e..c41ea5ed3f 100644
--- a/MAINTAINERS
+++
From: Dayeol Lee
pmp_read_cfg() returns 8-bit value, which is combined together to form a single
pmpcfg CSR.
The default promotion rules will result in an integer here ("i*8" is integer,
which
flows through) resulting in a 32-bit signed value on most hosts.
That's bogus on RV64I, with the high
We now have a RISC-V specific QEMU development list.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
Merge remote-tracking branch
'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging
(2018-10-30 15:49:55 +)
are available in the Git repository at:
git://github.com/riscv/riscv-qemu.git
Alistair has been contributing to the RISC-V QEMU port for a while now
so I'd like him to be officially listed as a maintainer. I've checked
with the other RISC-V maintainers and there are no objections, and I've
also checked with Alistair so he knows I'm volunteering him.
Signed-off-by: Palmer
On 01/11/2018 21:26, Richard Henderson wrote:
> The divdeu instruction was added to ISA 2.06 (Power7).
> Exclude this block from older cpus.
>
> Fixes: 27ae5109a2ba (softfloat: Specialize udiv_qrnnd for ppc64)
> Reported-by: Laurent Vivier
> Signed-off-by: Richard Henderson
> ---
>
When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, aa32_arm_div will not be supported either.
Signed-off-by: Richard Henderson
---
"Tested" on an APM Mustang, which does support AArch32. I'm not
sure, off hand, which cpu(s) don't have it, and Alex didn't
Hi all,
I have an odd situation which occurs very infrequently and I'm hoping to
get some advice on how to debug. Apologies for the length of this
message, I tried to include as much potentially useful information as
possible.
In the context of an OpenStack compute node I have a qemu guest
The divdeu instruction was added to ISA 2.06 (Power7).
Exclude this block from older cpus.
Fixes: 27ae5109a2ba (softfloat: Specialize udiv_qrnnd for ppc64)
Reported-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
include/fpu/softfloat-macros.h | 4 ++--
1 file changed, 2 insertions(+),
On 11/1/18 5:38 PM, Laurent Vivier wrote:
> commit 27ae5109a2 has introduced an assembly instruction only supported
> by ISA 3.0B and it fails to execute on previous versions of the POWER
> CPU (like PowerPC G5).
>
> This patch fixes that by checking the ISA level, and falls back to
> the default
On Thu, Nov 1, 2018 at 12:07 PM, Dr. David Alan Gilbert
wrote:
> OK; the tricky thing is when you upgrade one host in a small cluster as
> you start doing an upgrade, and then once it's got it's first VM you
> can't migrate away from it until others are updated; that gets messy.
One must always
* Liran Alon (liran.a...@oracle.com) wrote:
>
>
> > On 1 Nov 2018, at 17:56, Dr. David Alan Gilbert wrote:
> >
> > * Liran Alon (liran.a...@oracle.com) wrote:
> >>
> >>
> >>> On 1 Nov 2018, at 15:10, Dr. David Alan Gilbert
> >>> wrote:
> >>>
> >>> * Liran Alon (liran.a...@oracle.com)
> On 1 Nov 2018, at 17:56, Dr. David Alan Gilbert wrote:
>
> * Liran Alon (liran.a...@oracle.com) wrote:
>>
>>
>>> On 1 Nov 2018, at 15:10, Dr. David Alan Gilbert wrote:
>>>
>>> * Liran Alon (liran.a...@oracle.com) wrote:
> On 31 Oct 2018, at 20:59, Dr. David Alan Gilbert
The Debian Sid repository is not garanteed to be stable, as his
'unstable' name suggest :)
To allow quick testing, packages are pushed various time a day,
which my be annoying when trying to use it for stable development
(which is not recommended, but Sid provides edge packages we use
for
On Thu, Nov 01, 2018 at 05:24:15PM +, Peter Maydell wrote:
> On 30 October 2018 at 19:30, Philippe Mathieu-Daudé wrote:
> > From: Guenter Roeck
> >
> > QEMU already supports pl330. Instantiate it for smdkc210.
>
> Reviewed-by: Peter Maydell
>
> I don't suppose anybody has the SoC
- make it look more like a pair of qcow2_compress - rename the function
and its parameters
- drop extra out_len variable, check filling of output buffer by strm
structure itself
- fix code style
- add some documentation
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2.c | 56
Compression is done in threads in qcow2.c. We want to do decompression
in the same way, so, firstly, move it to the same file.
The only change is braces around if-body in decompress_buffer, to
satisfy checkpatch.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2-cluster.c | 70
On 31 October 2018 at 14:19, Michael Roth wrote:
> The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging
> (2018-10-30 15:49:55 +)
>
> are available in the Git
Do decompression in threads, like it is already done for compression.
This improves asynchronous compressed reads performance.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2.c | 35 ---
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git
Allocate buffers locally and release qcow2 lock. Than, reads inside
qcow2_co_preadv_compressed may be done in parallel, however all
decompression is still done synchronously. Let's improve it in the
following commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2.h | 4 ---
Hi all!
The series brings threads to qcow2 decompression path, like it is
already done for compression.
Performance gain is illustrated by the following test:
[]# cat gen.sh
#!/bin/bash
echo 'create pattern-file /ssd/t_pat'
./qemu-img create -f raw /ssd/t_pat 10g
for i in {0..9}; do
Give explicit size both for source and destination buffers, to make it
similar with decompression path and than cleanly reuse parameter
structure for decompression threads.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2.c | 30 ++
1 file changed, 18
Use appropriate macro, corresponding to deflateInit2 spec.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/qcow2.c b/block/qcow2.c
index 30689b7688..3e9367c449 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
We are gradually moving away from sector-based interfaces, towards
byte-based. Get rid of it here too.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/block/qcow2.c b/block/qcow2.c
index
Respected Sir,
I followed https://wiki.qemu.org/Hosts/Linux to build qemu from source
code. Its installed successfully with Ubuntu 16.04 VM created using VNC
server.
*Now, Could you please suggest me how to migrate VM from one host to
another?.*
I goggled lot but not getting any solution.
--
Public bug reported:
For qemu-3.0.0 I see with GCC 9 compiler a new warning:
$ make -j1 -C roms pxerom VERBOSE=1 V=1
make: Entering directory '/home/abuild/rpmbuild/BUILD/qemu-3.0.0/roms'
make -C ipxe/src CONFIG=qemu \
PACKAGING_TIMESTAMP=1534273834 \
CROSS_COMPILE= \
On 1 November 2018 at 17:30, Peter Maydell wrote:
> On 1 November 2018 at 17:26, Alex Bennée wrote:
>> I think the problem is the we trip over the assert because:
>>
>> /* Some features automatically imply others: */
>> if (arm_feature(env, ARM_FEATURE_V8)) {
>> if
Fredrik, please do not include handling of any opcode other than those
currently in the tree.
There are good and bad patterns in the code, and not every pattern is OK to
follow.
Thanks,
Aleksandar
From: Fredrik Noring
Sent: Thursday, November 1, 2018
On 01/11/2018 18:49, Peter Maydell wrote:
> On 1 November 2018 at 17:38, Laurent Vivier wrote:
>> commit 27ae5109a2 has introduced an assembly instruction only supported
>> by ISA 3.0B and it fails to execute on previous versions of the POWER
>> CPU (like PowerPC G5).
>>
>> This patch fixes that
Hey Samuel,
On 1/11/18 11:22, Samuel Ortiz wrote:
The hardware-reduced API will need to build RSDP as well, so we should
export this routine. While doing so, we also slightly change the
function prototype. Since no caller needs it, and to make it more
consistent with the rest of the AML build
On 1 November 2018 at 17:38, Laurent Vivier wrote:
> commit 27ae5109a2 has introduced an assembly instruction only supported
> by ISA 3.0B and it fails to execute on previous versions of the POWER
> CPU (like PowerPC G5).
>
> This patch fixes that by checking the ISA level, and falls back to
>
On 1/11/18 17:17, Peter Maydell wrote:
In ppc_core99_init(), we allocate an openpic_irqs array, which
we then use to collect up the various qemu_irqs which we're
going to connect to the interrupt controller. Once we've
called sysbus_connect_irq() to connect them all up, the
array is no longer
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/madd.c | 43 +
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
index 9ad2ea6dbb..f6f215e1c3 100644
---
commit 27ae5109a2 has introduced an assembly instruction only supported
by ISA 3.0B and it fails to execute on previous versions of the POWER
CPU (like PowerPC G5).
This patch fixes that by checking the ISA level, and falls back to
the default C function if the instruction is not supported.
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/madd.c | 45 +++
2 files changed, 46 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/madd.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
Signed-off-by: Fredrik Noring
---
disas/mips.c | 8
1 file changed, 8 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index d73d4094d8..9f01fda8bd 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -611,6 +611,9 @@ struct mips_opcode
/* ST Microelectronics Loongson 2F. */
From: Philippe Mathieu-Daudé
The three-operand MADD and MADDU are specific to the
Toshiba TX19/TX39/TX79 cores.
The "32-Bit TX System RISC TX39 Family Architecture manual"
is available at https://wiki.qemu.org/File:DSAE0022432.pdf
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Fredrik
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/maddu.c | 37 ++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/maddu.c b/tests/tcg/mips/mipsr5900/maddu.c
index e4e552102d..30936fb2b4 100644
---
From: Philippe Mathieu-Daudé
Increase the size of 'membership' holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.
This change is related to commit f9c9cd63e3 "target/mips: Increase
'supported ISAs/ASEs' flag holder size".
Signed-off-by:
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4808cb49c3..57b17ad8f6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5021,7
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/maddu.c | 37 +++
2 files changed, 38 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/maddu.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
Disassemble the R5900 instructions DIV1, DIVU1, MFLO1, MTLO1, MFHI1,
MTHI1, MULT1 and MULTU1. The opcodes for MADD1 and MADDU1 clash with
the opcodes for CLZ and CLO, resulting in incorrect disassembly. They
are therefore omitted here.
Signed-off-by: Fredrik Noring
---
disas/mips.c | 12
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 65 +
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6e5a8a2565..624e53644d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -27992,7
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 67 ++---
1 file changed, 56 insertions(+), 11 deletions(-)
diff --git a/target/mips/translate.c
This series amends the R5900 support with the following noncritical
features:
- R5900 MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79.
- R5900 DIV1 and DIVU1 are generated in gen_div1_tx79.
- The R5900 LQ and SQ instructions are now also covered by the Toshiba
MMI ASE, as per
On 1 November 2018 at 17:26, Alex Bennée wrote:
>
> Richard Henderson writes:
>
>> My previous patch set for replacing feature bits with id registers
>> failed to consider that these id registers are beginning to control
>> migration, and thus we must fill them in for KVM as well.
>>
>> Thus, we
Richard Henderson writes:
> My previous patch set for replacing feature bits with id registers
> failed to consider that these id registers are beginning to control
> migration, and thus we must fill them in for KVM as well.
>
> Thus, we want to initialize these values within CPU from the
On 1 November 2018 at 17:12, Daniel P. Berrangé wrote:
> [1] Maybe we should in fact create the changelog pages at the very start
> of each release cycle.
Yes, that would be a good idea.
thanks
-- PMM
On 31 October 2018 at 14:07, Eduardo Habkost wrote:
> Peter, my S-o-b line was missing on some commits, I have just pushed a new
> x86-next-pull-request tag, with exactly the same tree. Sorry for the noise.
>
> Thanks to Eric Blake for reporting the issue.
>
> The following changes since commit
On 30 October 2018 at 19:30, Philippe Mathieu-Daudé wrote:
> From: Guenter Roeck
>
> QEMU already supports pl330. Instantiate it for smdkc210.
Reviewed-by: Peter Maydell
I don't suppose anybody has the SoC datasheet to crosscheck
the irq/address values (and maybe see if it lists any of
the
[ Philippe and Emilio -- thank you for cc-ing me. Good catch, since I'm
not subscribed to the QEMU mailing list. Changes to the R5900 emulation
are certainly of interest. ]
Hi Aleksandar, Philippe,
On Thu, Nov 01, 2018 at 03:31:54PM +0100, Philippe Mathieu-Daudé wrote:
> Cc'ing Fredrik.
>
> On
On 31 October 2018 at 16:00, Philippe Mathieu-Daudé wrote:
>
> The following patch fixes this crash, but I'm not sure this is the correct
> fix:
>
> -- >8 --
> --- a/hw/intc/exynos4210_gic.c
> +++ b/hw/intc/exynos4210_gic.c
> @@ -213,6 +213,8 @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
>
It is that time[1] of the release cycle when maintainers can make a start
on filling in the release changelog info for 3.1. I created the basic
page structure copying from 3.0 :
https://wiki.qemu.org/ChangeLog/3.1
Anyone who has sent a pull request in this dev cycle should fill in the
info
On 31/10/2018 19:46, Laurent Vivier wrote:
> On 05/10/2018 20:02, Richard Henderson wrote:
>> The ISA has a 128/64-bit division instruction, though it assumes the
>> low 64-bits of the numerator are 0, and so requires a bit more fixup
>> than a full 128-bit division insn.
>>
>> Reviewed-by: David
On Thu, Nov 1, 2018 at 8:56 AM, Dr. David Alan Gilbert
wrote:
> So if I have matching host kernels it should always work?
> What happens if I upgrade the source kernel to increase it's maximum
> nested size, can I force it to keep things small for some VMs?
Any change to the format of the
On 01.11.18 15:55, Igor Mammedov wrote:
> On Wed, 31 Oct 2018 18:31:30 +0100
> David Hildenbrand wrote:
>
>> On 24.10.18 12:19, David Hildenbrand wrote:
>>> This series reworks some pci hotplug handlers (except for s390, that will
>>> require more work but is not required for now).
>>>
>>> 1.
On Thu 01 Nov 2018 05:30:37 PM CET, Peter Maydell wrote:
> In the function external_snapshot_prepare() we have a
> BlockdevSnapshotSync struct, which has the usual combination
> of has_snapshot_node_name and snapshot_node_name fields for an
> optional field. We set up a local variable
>
On 31 October 2018 at 12:21, Richard Henderson
wrote:
> The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging
> (2018-10-30 15:49:55 +)
>
> are available in the
In the function external_snapshot_prepare() we have a
BlockdevSnapshotSync struct, which has the usual combination
of has_snapshot_node_name and snapshot_node_name fields for an
optional field. We set up a local variable
const char *snapshot_node_name =
In ppc_core99_init(), we allocate an openpic_irqs array, which
we then use to collect up the various qemu_irqs which we're
going to connect to the interrupt controller. Once we've
called sysbus_connect_irq() to connect them all up, the
array is no longer required, but we forgot to free it.
Since
On Wed, 31 Oct 2018 15:38:08 PDT (-0700), richard.hender...@linaro.org wrote:
On 10/31/18 1:20 PM, Bastian Koppelmann wrote:
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
-gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
+TCGv source1 = tcg_temp_new();
+TCGv source2 =
On Thu, 1 Nov 2018 12:27:45 -0300
Eduardo Habkost wrote:
> On Thu, Nov 01, 2018 at 11:18:42AM +0100, Igor Mammedov wrote:
> > On Wed, 31 Oct 2018 17:12:56 -0300
> > Eduardo Habkost wrote:
> >
> > > On Tue, Oct 30, 2018 at 07:04:48PM +0400, Marc-André Lureau wrote:
> > > > Handle calls of
* Liran Alon (liran.a...@oracle.com) wrote:
>
>
> > On 1 Nov 2018, at 15:10, Dr. David Alan Gilbert wrote:
> >
> > * Liran Alon (liran.a...@oracle.com) wrote:
> >>
> >>
> >>> On 31 Oct 2018, at 20:59, Dr. David Alan Gilbert
> >>> wrote:
> >>>
> >>> * Liran Alon (liran.a...@oracle.com)
Hello,
On Mon, 2018-10-22 at 13:46 +0200, Lukáš Hrázký wrote:
> Hello,
>
> On Thu, 2018-10-18 at 03:16 -0400, Frediano Ziglio wrote:
> > >
> > > Adds two functions to let QEMU provide information to identify graphics
> > > devices and their monitors in the guest:
> > >
> > > * device address -
On Thu, 1 Nov 2018 12:02:03 -0300
Eduardo Habkost wrote:
> On Thu, Nov 01, 2018 at 01:16:37PM +0100, Igor Mammedov wrote:
> > On Tue, 30 Oct 2018 20:07:17 -0300
> > Eduardo Habkost wrote:
> >
> > > On Tue, Oct 30, 2018 at 03:22:43PM +0100, Igor Mammedov wrote:
> > > > On Tue, 30 Oct 2018
On Thu, Nov 01, 2018 at 04:16:12PM +0100, Igor Mammedov wrote:
> On Wed, 31 Oct 2018 17:27:57 -0300
> Eduardo Habkost wrote:
>
> > On Tue, Oct 30, 2018 at 07:04:53PM +0400, Marc-André Lureau wrote:
> > > hostmem-file and hostmem-memfd use the whole object path for the
> > > memory region name,
On 1/11/18 11:22, Samuel Ortiz wrote:
From: Sebastien Boeuf
The ACPI hotplug support for PCI devices APIs are not x86 or even
machine type specific. In order for future machine types to be able to
re-use that code, we export it through the architecture agnostic
hw/acpi folder.
Reviewed-by:
On Thu, Nov 01, 2018 at 11:18:42AM +0100, Igor Mammedov wrote:
> On Wed, 31 Oct 2018 17:12:56 -0300
> Eduardo Habkost wrote:
>
> > On Tue, Oct 30, 2018 at 07:04:48PM +0400, Marc-André Lureau wrote:
> > > Handle calls of object_property_set_globals() with any object type,
> > > but only apply
On 1/11/18 16:12, Philippe Mathieu-Daudé wrote:
Hi Samuel,
On 1/11/18 11:22, Samuel Ortiz wrote:
It is going to be used by the PC machine type as the MADT table builder
method and thus needs to be exported outside of acpi-build.c
Also, now that the generic build_madt() API is exported, we
> On 1 Nov 2018, at 15:10, Dr. David Alan Gilbert wrote:
>
> * Liran Alon (liran.a...@oracle.com) wrote:
>>
>>
>>> On 31 Oct 2018, at 20:59, Dr. David Alan Gilbert
>>> wrote:
>>>
>>> * Liran Alon (liran.a...@oracle.com) wrote:
> On 31 Oct 2018, at 20:19, Paolo Bonzini
On Thu, 1 Nov 2018 15:27:02 +0100
Philippe Mathieu-Daudé wrote:
> On 1/11/18 11:44, Igor Mammedov wrote:
> > object_new() returns a new backend with refcount == 1 and
> > then later object_property_add_child() increases refcount to 2
> > So when ivshmem is desroyed, the backend it has created
object_new() returns a new backend with refcount == 1 and
then later object_property_add_child() increases refcount to 2
So when ivshmem is destroyed, the backend it has created isn't
destroyed along with it as children cleanup will bring
backend's refcount only to 1, which leaks backend including
On Wed, 31 Oct 2018 17:27:57 -0300
Eduardo Habkost wrote:
> On Tue, Oct 30, 2018 at 07:04:53PM +0400, Marc-André Lureau wrote:
> > hostmem-file and hostmem-memfd use the whole object path for the
> > memory region name, and hostname-ram uses only the path component (the
> > object id, or
Hi Samuel,
On 1/11/18 11:22, Samuel Ortiz wrote:
It is going to be used by the PC machine type as the MADT table builder
method and thus needs to be exported outside of acpi-build.c
Also, now that the generic build_madt() API is exported, we have to
rename the ARM static one in order to avoid
This fixes wrong interfacing between virtio serial port and bus
models, and corresponding chardev backends, caused extra and incorrect
activity during guest boot process (when virtserialport device used).
Signed-off-by: Artem Pisarenko
---
Notes:
Although this doesn't trigger any issue/bug
On 31 October 2018 at 11:36, Daniel P. Berrangé wrote:
> The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging
> (2018-10-30 15:49:55 +)
>
> are available in the
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