On Thu, Dec 13, 2018 at 10:37:06PM +, Michael Hanselmann wrote:
> The filename length in MTP metadata is specified by the guest. By
> trusting it directly it'd theoretically be possible to get the host to
> write memory parts outside the filename buffer into a filename. In
> practice though
> -Original Message-
> From: Juan Quintela [mailto:quint...@redhat.com]
> Sent: Friday, December 14, 2018 5:01 AM
> To: qemu-devel@nongnu.org
> Cc: Michael S. Tsirkin ; Thomas Huth ;
> Gerd Hoffmann ; Gonglei (Arei)
> ; Juan Quintela
> Subject: [PATCH v3 00/16] Virtio devices split from
On 12/13/2018 11:45 PM, Dr. David Alan Gilbert wrote:
* Wei Wang (wei.w.w...@intel.com) wrote:
The new feature enables the virtio-balloon device to receive hints of
guest free pages from the free page vq.
A notifier is registered to the migration precopy notifier chain. The
notifier calls
On 12/13/2018 10:28 PM, Dr. David Alan Gilbert wrote:
* Wei Wang (wei.w.w...@intel.com) wrote:
BITMAP_LAST_WORD_MASK(nbits) returns 0x when "nbits=0", which
makes bitmap_count_one fail to handle the "nbits=0" case. It appears to be
preferred to remain BITMAP_LAST_WORD_MASK identical to
Paolo Bonzini writes:
> On 13/12/18 19:21, Peter Maydell wrote:
>> On Thu, 13 Dec 2018 at 18:07, Paolo Bonzini wrote:
>>> On 13/12/18 19:01, Peter Maydell wrote:
I sent a patch to do this a little while back:
https://patchwork.kernel.org/patch/10561557/
It didn't get
Paolo Bonzini writes:
> There are not many, and they are all simple mistakes that ended up
> being committed. Remove them.
>
> Signed-off-by: Paolo Bonzini
The cover letter states "I am not touching space-tab in the middle of
the line, many of which are in #define lines." I think the actual
Eric Blake writes:
> On 12/13/18 12:43 PM, Markus Armbruster wrote:
>> From: Marc-André Lureau
>>
>> Wrap generated enum and struct members and their supporting code with
>>
>
> Git ate the line because it started with #. Not sure if you can sneak
> in a v2 pull request that puts something
From: Marc-André Lureau
Wrap generated enum and struct members and their supporting code with
#if/#endif, using the .ifcond members added in the previous patches.
We do enum and struct in a single patch because union tag enum and the
associated variants tie them together, and dealing with that
git-request-pull master public pull-qapi-2018-12-13-v2
The following changes since commit c3ec0fa1a8e815ecfec9eabb9c20ee206c313e07:
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2018-12-12'
into staging (2018-12-13 13:41:44 +)
are available in the Git repository at:
We can perform this with fewer operations.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 65 ++
1 file changed, 23 insertions(+), 42 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
We need to reuse this from helper-a64.c. Provide a stub
definition for CONFIG_USER_ONLY. This matches the stub
definitions that we removed for arm_regime_tbi{0,1} before.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 17 +
target/arm/helper.c| 4 ++--
2
Stripping out the authentication data does not require any crypto,
it merely requires the virtual address parameters.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper-a64.c
The arm_regime_tbi{0,1} functions are replacable with the new function
by giving the lowest and highest address.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 35 --
target/arm/helper.c | 61 -
2 files changed, 16
This is not really functional yet, because the crypto is not yet
implemented. This, however follows the AddPAC pseudo function.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 40 +++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff
Split out functions to extract the virtual address parameters.
Let the functions choose T0 or T1 address space half, if present.
Extract (most of) the control bits that vary between EL or Tx.
Signed-off-by: Richard Henderson
v2: Incorporate feedback wrt VTCR, HTCR, and more.
---
This will enable PAuth decode in a subsequent patch.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 47 +-
1 file changed, 36 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
This is the main crypto routine, an implementation of QARMA.
This matches, as much as possible, ARM pseudocode.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 241 +++-
1 file changed, 240 insertions(+), 1 deletion(-)
diff --git
This is not really functional yet, because the crypto is not yet
implemented. This, however follows the Auth pseudo function.
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git
This function is only used by AArch64. Code movement only.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h | 2 +
target/arm/helper.h | 1 -
target/arm/helper-a64.c | 155
target/arm/op_helper.c | 155
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 70 +
1 file changed, 70 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b9ffc07fbc..f1e9254c9a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5061,6
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 146 +
1 file changed, 146 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c5ec430b42..7ba4c996cf 100644
--- a/target/arm/translate-a64.c
+++
The pattern
ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
is computing the full ARMMMUIdx, stripping off the ARM bits,
and then putting them back.
Avoid the extra two steps with the appropriate helper function.
Reviewed-by: Peter Maydell
Signed-off-by: Richard
NAK, expect v2 to correct the commit message accident pointed out by
Eric.
FIXME: We should have an attribute that controls the EL1 enable bits.
We may not always want to turn on pointer authentication with -cpu max.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index
While we could expose stage_1_mmu_idx, the combination is
probably going to be more useful.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 15 +++
target/arm/helper.c| 7 +++
2 files changed, 22 insertions(+)
diff --git a/target/arm/internals.h
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7ba4c996cf..d034a5edf3 100644
--- a/target/arm/translate-a64.c
+++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 2 +-
target/arm/helper-a64.c| 10 +-
target/arm/translate-a64.c | 7 ++-
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper-a64.h
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1d57be0c91..84f70b2a24 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -316,6 +316,10 @@ static void aarch64_max_initfn(Object
This function is, or will shortly become, too big to inline.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 48 +
target/arm/helper.c | 44 +
2 files changed, 49
There are 5 bits of state that could be added, but to save
space within tbflags, add only a single enable bit.
Helpers will determine the rest of the state at runtime.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
v2: Fix whitespace, comment grammar.
---
target/arm/cpu.h
The cryptographic internals are stubbed out for now,
but the enable and trap bits are checked.
Signed-off-by: Richard Henderson
v2: Remove trap from xpac* helpers; these are now side-effect free.
Use struct ARMPACKey.
---
target/arm/helper-a64.h | 12 +++
target/arm/internals.h | 6
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 82 +-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 30086a5d7f..e62d248894 100644
--- a/target/arm/translate-a64.c
Post v8.4 bits taken from SysReg_v85_xml-00bet8.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
v2: Review fixups from Peter.
---
target/arm/cpu.h | 45 +
1 file changed, 33 insertions(+), 12 deletions(-)
diff --git
Now properly signals unallocated for REV64 with SF=0.
Allows for the opcode2 field to be decoded shortly.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff
Add storage space for the 5 encryption keys.
Signed-off-by: Richard Henderson
v2: Remove pointless double migration.
Use a struct to make it clear which half is which.
---
target/arm/cpu.h | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 93 +-
1 file changed, 81 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7c1cc1ce8e..0df344f9e8 100644
---
Lots of little changes since v1, but many of which are noted
within each patch. This version works in system mode, using
https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=for-next/core
r~
Richard Henderson (27):
target/arm: Add state for the ARMv8.3-PAuth extension
Not that there are any stores involved, but why argue with ARM's
naming convention.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
On 2018/12/13 下午10:56, Michael S. Tsirkin wrote:
On Thu, Dec 13, 2018 at 11:41:06AM +0800, Yongji Xie wrote:
On Thu, 13 Dec 2018 at 10:58, Jason Wang wrote:
On 2018/12/12 下午5:18, Yongji Xie wrote:
Ok, then we can simply forbid increasing the avail_idx in this case?
Basically, it's a
When deciding about the huge DMA window, the typical Linux pseries guest
uses the maximum allowed RAM size as the upper limit. We did the same
on QEMU side to match that logic. Now we are going to support a GPU RAM
pass through which is not available at the guest boot time as it requires
the guest
On Thu, 2018-12-13 at 21:01 -0600, Richard Henderson wrote:
> On 12/13/18 5:58 PM, Benjamin Herrenschmidt wrote:
> > +#ifdef CONFIG_ATOMIC64
> > +/* This is meant to be used for atomic PTE updates under MT-TCG */
> > +uint32_t glue(address_space_cmpxchgq_notdirty, SUFFIX)(ARG1_DECL,
> > +
On 12/13/18 9:18 PM, Richard Henderson wrote:
> I didn't get this fix pushed back into the patch set that I actually
> sent last week. The patch is in target-arm.next, and I'm sure you
> would have eventually seen the error in testing.
>
>
> r~
> ---
> target/arm/kvm64.c | 4 ++--
> 1 file
On 21/11/2018 05:27, Alistair Francis wrote:
> On Tue, Nov 13, 2018 at 12:42 AM Alexey Kardashevskiy wrote:
>>
>> sPAPR code will use it too so move it from VFIO to the common code.
>>
>> Signed-off-by: Alexey Kardashevskiy
>
> Reviewed-by: Alistair Francis
Aand who is taking this? I
From: Alistair Francis
Instead of hard coding 31 for the shift right use TCG_TARGET_REG_BITS - 1.
Signed-off-by: Alistair Francis
Message-Id:
<7dfbddf7014a595150aa79011ddb342c3cc17ec3.1544648105.git.alistair.fran...@wdc.com>
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
From: "Emilio G. Cota"
Change the order in which we extract a/b and c/d to
match the output of the upstream xxhash32.
Tested with:
https://github.com/cota/xxhash/tree/qemu
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
Somehow we forgot these operations, once upon a time.
This will allow immediate stores to have their bswap
optimized away.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 12
1 file changed, 12 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index
For now, defined universally as true, since we previously required
backends to implement swapped memory operations. Future patches
may now remove that support where it is onerous.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 +
tcg/arm/tcg-target.h | 1 +
From: "Emilio G. Cota"
It's unused since 75e8b9b7aa0b95a761b9add7e2f09248b101a392.
Signed-off-by: Emilio G. Cota
Message-Id: <20181209193749.12277-9-c...@braap.org>
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 4 ++--
tcg/optimize.c | 4 ++--
From: "Emilio G. Cota"
Before moving them all to include/qemu/xxhash.h.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
include/exec/tb-hash-xx.h | 41 +--
include/exec/tb-hash.h| 2 +-
tests/qht-bench.c
This does require an extra two checks within the slow paths
to replace the assert that we're moving.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 5c88f1f36b..28192f4608 100644
--- a/tcg/i386/tcg-target.inc.c
+++
These values are constant between all qemu_ld/st invocations;
there is no need to figure this out each time. If we cannot
use a segment or an offset directly for guest_base, load the
value into a register in the prologue.
Reviewed-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
Based on the only current user, Sparc:
New code uses 1 constant that takes 2 insns to create, plus 8.
Old code used 2 constants that took 2 insns to create, plus 9.
The result is a new total of 10 vs an old total of 13.
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 54
There is no longer a need for preserving branch offset operands,
as we no longer re-translate.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/s390/tcg-target.inc.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/tcg/s390/tcg-target.inc.c
From: "Emilio G. Cota"
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
include/exec/tb-hash.h | 2 +-
include/{exec/tb-hash-xx.h => qemu/xxhash.h} | 6 +++---
tests/qht-bench.c| 2 +-
util/qsp.c
This helps preserve the invariant that all TCG_TYPE_I32 values
are stored zero-extended in the 64-bit host registers.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.inc.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/tcg/i386/tcg-target.inc.c
Based on the only current user, Sparc:
New code uses 2 constants that take 2 insns to load from constant pool,
plus 13. Old code used 6 constants that took 1 or 2 insns to create,
plus 21. The result is a new total of 17 vs an old total of 29.
Signed-off-by: Richard Henderson
---
This does require an extra two checks within the slow paths
to replace the assert that we're moving. Also add two checks
within existing functions that lacked any kind of assert for
out of range branch.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/s390/tcg-target.inc.c |
We now have an invariant that all TCG_TYPE_I32 values are
zero-extended, which means that we do not need to extend
them again during qemu_ld/st, either explicitly via a separate
tcg_out_ext32u or implicitly via P_ADDR32.
Reviewed-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
Reviewed-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.inc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 3fb2f4b971..c21c3272f2 100644
--- a/tcg/i386/tcg-target.inc.c
+++
There are one use apiece for these. There is no longer a need for
preserving branch offset operands, as we no longer re-translate.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 22 +++---
1 file changed, 3 insertions(+), 19
From: "Emilio G. Cota"
Which we forgot to do in bd224fce60 ("qht-bench: add -p flag
to precompute hash values", 2018-09-26).
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
tests/qht-bench.c | 1 +
1 file changed, 1 insertion(+)
diff --git
There are one use apiece for these. There is no longer a need for
preserving branch offset operands, as we no longer re-translate.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 21 ++---
1 file changed, 2 insertions(+), 19
The reloc_pc{14,24}_val routines retain their asserts.
Use these directly within the slow paths.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git
This preserves the invariant that all TCG_TYPE_I32 values are
zero-extended in the 64-bit host register.
Reviewed-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 5 +++--
tcg/i386/tcg-target.inc.c | 6 ++
2 files changed, 9 insertions(+), 2 deletions(-)
This will move the assert for success from within (subroutines of)
patch_reloc into the callers. It will also let new code do something
different when a relocation is out of range.
For the moment, all backends are trivially converted to return true.
Reviewed-by: Alex Bennée
Signed-off-by:
The following changes since commit 2d894e48362ad2a576fca929dcca1787f43a8af6:
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request'
into staging (2018-12-13 17:50:45 +)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-tcg-20181213
This helps preserve the invariant that all TCG_TYPE_I32 values
are stored zero-extended in the 64-bit host registers.
Reviewed-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.inc.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git
This does require an extra two checks within the slow paths
to replace the assert that we're moving.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 37
1 file changed, 21 insertions(+), 16 deletions(-)
diff
There is no longer a need for preserving branch offset operands,
as we no longer re-translate.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target.inc.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/tcg/sparc/tcg-target.inc.c
There is no longer a need for preserving branch offset operands,
as we no longer re-translate.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 25 +++--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git
It is unused since 3fb53fb4d12f2e7833bd1659e6013237b130ef20.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 8
1 file changed, 8 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index e1fbf465cb..1142eb13ad 100644
I didn't get this fix pushed back into the patch set that I actually
sent last week. The patch is in target-arm.next, and I'm sure you
would have eventually seen the error in testing.
r~
---
target/arm/kvm64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
There is no longer a need for preserving branch offset operands,
as we no longer re-translate.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.inc.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c
Reviewed-by: Alex Bennée
Reviewed-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 7488c3d869..2441658865 100644
--- a/tcg/i386/tcg-target.h
+++
For x86_64, this can remove a REX prefix resulting in smaller code
when manipulating globals of type i32, as we move them between backing
store via cpu_env, aka TCG_AREG0.
Reviewed-by: Alex Bennée
Reviewed-by: Emilio G. Cota
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 8
It is unused since b68686bd4bfeb70040b4099df993dfa0b4f37b03.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 12
1 file changed, 12 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index
On 12/13/18 5:58 PM, Benjamin Herrenschmidt wrote:
> +#ifdef CONFIG_ATOMIC64
> +/* This is meant to be used for atomic PTE updates under MT-TCG */
> +uint32_t glue(address_space_cmpxchgq_notdirty, SUFFIX)(ARG1_DECL,
> +hwaddr addr, uint64_t old, uint64_t new, MemTxAttrs attrs, MemTxResult
>
This adds an accelerator name to the "into mtree -f" to tell the user if
a particular memory section is registered with the accelerator;
the primary user for this is KVM and such information is useful
for debugging purposes.
This adds a has_memory() callback to the accelerator class allowing any
On Fri, 14 Dec 2018 at 10:20, Michael S. Tsirkin wrote:
>
> On Fri, Dec 14, 2018 at 09:56:41AM +0800, Yongji Xie wrote:
> > On Thu, 13 Dec 2018 at 22:45, Michael S. Tsirkin wrote:
> > >
> > > On Thu, Dec 06, 2018 at 02:35:46PM +0800, elohi...@gmail.com wrote:
> > > > From: Xie Yongji
> > > >
>
On Fri, Dec 14, 2018 at 09:56:41AM +0800, Yongji Xie wrote:
> On Thu, 13 Dec 2018 at 22:45, Michael S. Tsirkin wrote:
> >
> > On Thu, Dec 06, 2018 at 02:35:46PM +0800, elohi...@gmail.com wrote:
> > > From: Xie Yongji
> > >
> > > This patchset is aimed at supporting qemu to reconnect
> > >
On Thu, 13 Dec 2018 at 22:45, Michael S. Tsirkin wrote:
>
> On Thu, Dec 06, 2018 at 02:35:46PM +0800, elohi...@gmail.com wrote:
> > From: Xie Yongji
> >
> > This patchset is aimed at supporting qemu to reconnect
> > vhost-user-blk backend after vhost-user-blk backend crash or
> > restart.
> >
>
SLOF receives a device tree and updates it with various properties
before switching to the guest kernel and QEMU is not aware of any changes
made by SLOF. Since there is no real RTAS (QEMU implements it), it makes
sense to pass the SLOF final device tree to QEMU to let it implement
RTAS related
Hi all,
Here is the error.
GTESTER check-qtest-x86_64
Unable to get file status flag on fd 21860: Bad file descriptor(errno=9)
GTESTER check-qtest-aarch64
Broken pipe
GTester: last random seed: R02S3f0d6981dd97231d06e0b2966baf94b9
Unable to get file status flag on fd 21965: Bad file
On Thu, Dec 13, 2018 at 11:37:37PM +0100, Paolo Bonzini wrote:
> Most files that have TABs only contain a handful of them. Change
> them to spaces so that we don't confuse people.
>
> disas, standard-headers, linux-headers and libdecnumber are imported
> from other projects and probably should
On 11/23/18 5:02 PM, Emilio G. Cota wrote:
> (Plus a qht-bench trivial patch.)
>
> Note that these apply on top of rth's tcg-next-for-4.0.
>
> Thanks,
Queued, thanks.
r~
On Thu, 13 Dec 2018 08:26:48 +0100
Markus Armbruster wrote:
> There's a question for David Gibson inline. Please search for /ppc/.
>
> Fei Li writes:
>
> > Make qemu_thread_create() return a Boolean to indicate if it succeeds
> > rather than failing with an error. And add an Error parameter
From: Nathaniel Graff
The watermark bits are set in the interrupt pending register according
to the configuration of txcnt and rxcnt in the txctrl and rxctrl
registers.
Since the UART TX does not implement a FIFO, the txwm bit is set as long
as the TX watermark level is greater than zero.
From: Michael Clark
Previously the second UARTs on the sifive_e and sifive_u machines
where disabled due to check-qtest-riscv32 and check-qtest-riscv64
failures. Recent changes in the QEMU core serial code have
resolved these failures so the second UARTs can be instantiated.
Cc: Palmer Dabbelt
From: Michael Clark
A missing shift made updates to the low order bits
of timecmp erroneously copy the old low order bits
into the high order bits of the 64-bit timecmp
register. Add the missing shift and rename timecmp
local variables to timecmp_hi and timecmp_lo.
This bug didn't show up as
From: Michael Clark
The address calculation for the pending bitfield had
a copy paste bug. This bug went unnoticed because the Linux
PLIC driver does not read the pending bitfield, rather it
reads pending interrupt numbers from the claim register
and writes acknowledgements back to the claim
From: Michael Clark
Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair
This series is another go at reducing the diff between the RISC-V fork
(https://github.com/riscv/riscv-qemu/) and mainline QEMU.
This is a small series with only a handful of changes as I don't want to
have to deal with too many conflicts all at once and I don't want to
create too much conflict
On 12/9/18 1:37 PM, Emilio G. Cota wrote:
> It's unused.
>
> Signed-off-by: Emilio G. Cota
> ---
> tcg/tcg.h | 4 ++--
> tcg/optimize.c | 4 ++--
> tcg/tcg.c | 10 --
> 3 files changed, 8 insertions(+), 10 deletions(-)
Cherry-picked this into tcg-next.
The nargs argument is
Note to RiscV folks: You may want to adapt your code to do the same as
this, esp. afaik, what you do today is endian-broken if host and guest
endian are different.
Cheers,
Ben.
On Fri, 2018-12-14 at 10:58 +1100, Benjamin Herrenschmidt wrote:
> Afaik, this isn't well documented (at least it
On Fri, 2018-12-14 at 10:58 +1100, Benjamin Herrenschmidt wrote:
> They should be atomic for MTTCG. Note: a real POWER9 core doesn't actually
> implement atomic PTE updates, it always fault for SW to handle it. Only
> the nest MMU (used by some accelerator devices and GPUs) implements
> those HW
They should be atomic for MTTCG. Note: a real POWER9 core doesn't actually
implement atomic PTE updates, it always fault for SW to handle it. Only
the nest MMU (used by some accelerator devices and GPUs) implements
those HW updates.
However, the architecture does allow the core to do it, and
On some architectures, PTE updates for dirty and changed bits need
to be performed atomically. This adds a couple of address_space_cmpxchg*
helpers for that purpose.
Signed-off-by: Benjamin Herrenschmidt
---
include/exec/memory_ldst.inc.h | 6 +++
memory_ldst.inc.c | 78
Afaik, this isn't well documented (at least it wasn't when I last looked)
but OSes such as Linux rely on this behaviour:
The HW updates to the page tables need to be done atomically with the
checking of the present bit (and other permissions).
This is what allows Linux to do simple xchg of PTEs
On Thu, Dec 13, 2018 at 11:37:37PM +0100, Paolo Bonzini wrote:
> Most files that have TABs only contain a handful of them. Change
> them to spaces so that we don't confuse people.
>
> disas, standard-headers, linux-headers and libdecnumber are imported
> from other projects and probably should
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