From: Bastian Koppelmann
during the refactor to decodetree we removed the manual decoding that is
necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
and c.fsw/c.sd. This reintroduces the manual parsing and the
omited implementation.
Signed-off-by: Bastian Koppelmann
The following changes since commit d4e65539e570d5872003710b5a1064489911d33d:
Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190316' into
staging (2019-03-17 14:10:52 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-4.0-rc0
On Mon, Mar 18, 2019 at 11:09:04AM +0800, Alex Williamson wrote:
> On Sun, 17 Mar 2019 22:51:27 -0400
> Zhao Yan wrote:
>
> > On Fri, Mar 15, 2019 at 10:24:02AM +0800, Alex Williamson wrote:
> > > On Thu, 14 Mar 2019 19:05:06 -0400
> > > Zhao Yan wrote:
> > >
> > > > On Fri, Mar 15, 2019 at
On Sun, 17 Mar 2019 22:51:27 -0400
Zhao Yan wrote:
> On Fri, Mar 15, 2019 at 10:24:02AM +0800, Alex Williamson wrote:
> > On Thu, 14 Mar 2019 19:05:06 -0400
> > Zhao Yan wrote:
> >
> > > On Fri, Mar 15, 2019 at 06:44:58AM +0800, Alex Williamson wrote:
> > > > On Wed, 13 Mar 2019 21:12:22
On Sunday, March 17, 2019, Richard Henderson
wrote:
> This patch merely changes the interface, aborting on all failures,
> of which there are currently none.
>
>
Why is this necessary?
Aleksandar
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.inc.c | 5 +++--
>
On Fri, Mar 15, 2019 at 10:24:02AM +0800, Alex Williamson wrote:
> On Thu, 14 Mar 2019 19:05:06 -0400
> Zhao Yan wrote:
>
> > On Fri, Mar 15, 2019 at 06:44:58AM +0800, Alex Williamson wrote:
> > > On Wed, 13 Mar 2019 21:12:22 -0400
> > > Zhao Yan wrote:
> > >
> > > > On Thu, Mar 14, 2019 at
On Fri, 15 Mar 2019 at 18:41, Ard Biesheuvel wrote:
>
> On Fri, 15 Mar 2019 at 11:08, Hongbo Zhang wrote:
> >
> > For the Aarch64, there is one machine 'virt', it is primarily meant to
> > run on KVM and execute virtualization workloads, but we need an
> > environment as faithful as possible to
On Sun, Mar 17, 2019 at 09:33:42PM +0100, Cédric Le Goater wrote:
> There is no need to propose the 'dual' interrupt mode interrupt device
> on POWER7/8 machines and the XIVE mode will not operate. Simply force
> XICS in this case.
>
> This makes the check in spapr_machine_init() redundant on
On Sun, Mar 17, 2019 at 02:08:23AM -0700, Richard Henderson wrote:
> This patch merely changes the interface, aborting on all failures,
> of which there are currently none.
>
> Signed-off-by: Richard Henderson
Reviewed-by: David Gibson
> ---
> tcg/aarch64/tcg-target.inc.c | 5 +++--
>
Hi Michael,
Could you pls apply this patch in your tree?
Thanks,
-Gonglei
> -Original Message-
> From: Li Qiang [mailto:liq...@163.com]
> Sent: Monday, March 18, 2019 9:12 AM
> To: Gonglei (Arei)
> Cc: qemu-devel@nongnu.org; Li Qiang
> Subject: [PATCH] backends: cryptodev: fix oob
The 'queue_index' of create/close_session function
is from guest and can be exceed 'MAX_CRYPTO_QUEUE_NUM'.
This leads oob access. This patch avoid this.
Signed-off-by: Li Qiang
---
backends/cryptodev-builtin.c| 4
backends/cryptodev-vhost-user.c | 4
2 files changed, 8
When adding '-fsanitize=undefined' in compiling configuration
and connect VM with vnc, it reports following error:
ui/vnc-enc-tight.c:910:13: runtime error: load of
misaligned address 0x621000466513 for type 'uint32_t',
which requires 4 byte alignment
This patch fix this issue.
Signed-off-by:
Hi,
> -Original Message-
> From: Li Qiang [mailto:liq...@163.com]
> Sent: Sunday, March 17, 2019 5:10 PM
> To: Gonglei (Arei)
> Cc: qemu-devel@nongnu.org; Li Qiang
> Subject: [PATCH] cryptodev-vhost-user: fix a oob access
>
> The 'queue_index' of create/close_session function
> is from
On Sat, Mar 16, 2019 at 09:08:12PM +0100, Philippe Mathieu-Daudé wrote:
> This fixes when configuring with --without-default-devices:
>
> $ qemu-system-ppc64 -bios /dev/null -M bamboo
> qemu-system-ppc64: Unsupported NIC model: e1000
>
> Fixes: 7c28b925b7e
> Signed-off-by: Philippe
On Sat, Mar 16, 2019 at 09:08:13PM +0100, Philippe Mathieu-Daudé wrote:
> This fixes when configuring with --without-default-devices:
>
> $ qemu-system-ppc64 -bios /dev/null -M ppce500
> qemu-system-ppc64: Unsupported NIC model: virtio-net-pci
>
> And:
>
> $ qemu-system-ppc64 -bios
On Sun, 17 Mar 2019 at 20:29, Peter Maydell wrote:
>
> On Sat, 16 Mar 2019 at 22:25, Philippe Mathieu-Daudé
> wrote:
> >
> > The following changes since commit 8b088d3f8ab5642020d28fa0c2a8d938bc5f3592:
> >
> > Merge remote-tracking branch
> > 'remotes/pmaydell/tags/pull-target-arm-20190315'
There is no need to propose the 'dual' interrupt mode interrupt device
on POWER7/8 machines and the XIVE mode will not operate. Simply force
XICS in this case.
This makes the check in spapr_machine_init() redundant on XIVE-only
machines.
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr_irq.c |
On Sat, 16 Mar 2019 at 22:25, Philippe Mathieu-Daudé wrote:
>
> The following changes since commit 8b088d3f8ab5642020d28fa0c2a8d938bc5f3592:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20190315' into staging (2019-03-15
> 11:39:42 +)
>
> are available in the
Hi Bin,
On Fri, 2019-03-15 at 09:54 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Fri, Mar 15, 2019 at 5:01 AM Auer, Lukas
> wrote:
> > Hi Bin,
> >
> > On Wed, 2019-03-13 at 09:51 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> > > On Tue, Mar 12, 2019 at 10:39 PM Auer, Lukas
> > > wrote:
> > > >
Hi Peter,
On 3/15/19 3:30 PM, Peter Maydell wrote:
> At the moment the Arm implementations of kvm_arch_{get,put}_registers()
> don't support having QEMU change the values of system registers
> (aka coprocessor registers for AArch32). This is because although
> kvm_arch_get_registers() calls
On Sat, 16 Mar 2019 at 16:24, Richard Henderson
wrote:
>
> The following changes since commit 8b088d3f8ab5642020d28fa0c2a8d938bc5f3592:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20190315' into staging (2019-03-15
> 11:39:42 +)
>
> are available in the Git
Peter Maydell 于2019年3月17日周日 下午10:10写道：
> On Sun, 17 Mar 2019 at 12:09, Li Qiang wrote:
> >
> > When adding '-fsanitize=undefined' in compiling configuration
> > and connect VM with vnc, it reports following error:
> >
> > ui/vnc-enc-tight.c:910:13: runtime error: load of
> > misaligned address
Some drivers do I2C bitbanging by keeping the output to 0 and flipping
the GPIO direction between input and output (see for example in Linux
gpio_set_open_drain_value_commit, in drivers/gpio/gpiolib.c).
When the GPIO is set to input, the pull-up resistor brings the output
to 1, while when the GPIO
On Sat, 16 Mar 2019 at 14:34, Marcel Apfelbaum
wrote:
>
> The following changes since commit 8b088d3f8ab5642020d28fa0c2a8d938bc5f3592:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20190315' into staging (2019-03-15
> 11:39:42 +)
>
> are available in the Git
On Sun, 17 Mar 2019 at 12:09, Li Qiang wrote:
>
> When adding '-fsanitize=undefined' in compiling configuration
> and connect VM with vnc, it reports following error:
>
> ui/vnc-enc-tight.c:910:13: runtime error: load of
> misaligned address 0x621000466513 for type 'uint32_t',
> which requires 4
When adding '-fsanitize=undefined' in compiling configuration
and connect VM with vnc, it reports following error:
ui/vnc-enc-tight.c:910:13: runtime error: load of
misaligned address 0x621000466513 for type 'uint32_t',
which requires 4 byte alignment
This patch fix this issue.
Signed-off-by:
Patchew URL:
https://patchew.org/QEMU/20190317090834.5552-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH for-4.1 v2 00/13] tcg/ppc: Add vector opcodes
Type: series
Message-id:
This includes vector load/store with immediate offset, some extra
move and splat insns, compare ne, and negate.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 115 +--
2 files changed, 89 insertions(+), 29
This includes single-word loads and stores, lots of double-word
arithmetic, and a few extra logical operations.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 155 +--
2 files changed, 134 insertions(+), 24
The 'queue_index' of create/close_session function
is from guest and can be exceed 'MAX_CRYPTO_QUEUE_NUM'.
This leads oob access. This patch avoid this.
Signed-off-by: Li Qiang
---
backends/cryptodev-vhost-user.c | 4
1 file changed, 4 insertions(+)
diff --git
For Altivec, this is always an expansion.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.opc.h | 8 +++
tcg/ppc/tcg-target.inc.c | 112 ++-
2 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.opc.h
This includes double-word loads and stores, double-word load and splat,
and double-word permute. All of which require multiple operations in
the base Altivec instruction set.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 34 ++
1 file changed,
There are a few missing operations yet, like expansion of
multiply and shifts. But this has move, load, store, and
basic arithmetic.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 31 +-
tcg/ppc/tcg-target.opc.h | 3 +
tcg/ppc/tcg-target.inc.c | 609
This saves a round trip through an integer register and back to memory.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 57 +++-
2 files changed, 57 insertions(+), 2 deletions(-)
diff --git
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 58 ++--
2 files changed, 57 insertions(+), 3 deletions(-)
diff
Signed-off-by: Richard Henderson
---
tcg/tcg-op-vec.c | 49
1 file changed, 33 insertions(+), 16 deletions(-)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 27f65600c3..cfb18682b1 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@
PowerPC Altivec does not support direct moves between vector registers
and general registers. So when tcg_out_mov fails, we can use the
backing memory for the temporary to perform the move.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 25 ++---
1 file changed, 22
This allows us to fall back to integers if the tcg backend
does not support comparisons in the given vece.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
The only fixed_reg is cpu_env, and it should not be modified
during any TB. Therefore code that tries to special-case moves
into a fixed_reg is dead. Remove it.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 85 +--
1 file changed, 38
Allow the backend to expand dup from memory directly, instead of
forcing the value into a temp first. This is especially important
if integer/vector register moves do not exist.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 1 +
This patch merely changes the interface, aborting on all failures,
of which there are currently none.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 5 +++--
tcg/arm/tcg-target.inc.c | 7 +--
tcg/i386/tcg-target.inc.c| 5 +++--
tcg/mips/tcg-target.inc.c|
Version 2 does not require VSX, and works with just Altivec.
But the last 3 patches incrementally add Power7/8/9 instructions.
I've tested this vs aa64 risu on power7 big-endian and power9
little-endian, so all of the easy bugs are out. ;-)
r~
Richard Henderson (13):
tcg: Assert fixed_reg
At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.
Note the TX fifo is still unimplemented.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_uart.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
The UART0's interrupt vector is wrongly set to 1 in the device tree.
Use SIFIVE_U_UART0_IRQ instead.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bc2582..57741c2 100644
---
> On Mar 15, 2019, at 01:31, Sergio Lopez wrote:
>
> Hi,
>
> Our current AIO path does a great job at unloading the work from the VM,
> and combined with IOThreads provides a good performance in most
> scenarios. But it also comes with its costs, in both a longer execution
> path and the
> On Mar 15, 2019, at 23:12, Stefan Hajnoczi wrote:
>
> On Thu, Mar 14, 2019 at 03:57:06PM +, Alex Bennée wrote:
>> As we approach stabilisation for 4.0 I thought it would be worth doing a
>> review of the current state of CI and stimulate some discussion of where
>> it is working for us
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