On 13/02/2019 16.59, Thomas Huth wrote:
> It's either "GNU *Library* General Public License version 2" or "GNU
> Lesser General Public License version *2.1*", but there was no "version
> 2.0" of the "Lesser" license. So assume that version 2.1 is meant here.
>
> Signed-off-by: Thomas Huth
> ---
On 29/03/2019 09.42, Thomas Huth wrote:
> On 06/02/2019 17.43, Thomas Huth wrote:
>> The license information in this file is rather confusing. The text
>> declares LGPL first, but then says that contributions after Jan 2012
>> are licensed under the GPL instead. How should the average user who
>>
I recently noticed that test-obj-y contains a file called
tests/check-block-qtest.o which simply does not belong to any .c
file and thus wondered why this is not causing any trouble.
Well, if I get the Makefile magic right, test-obj-y is not really
used for anything - and "make check" still works
On Tue, Apr 30, 2019 at 10:35:32AM +, Vladimir Sementsov-Ogievskiy wrote:
> 28.04.2019 13:01, Liang Li wrote:
> > If the backup target is a slow device like ceph rbd, the backup
> > process will affect guest BLK write IO performance seriously,
> > it's cause by the drawback of COW mechanism,
On 05/05/2019 20.07, Philippe Mathieu-Daudé wrote:
> All these devices do not contain any target-specific code. While
> most of them are arch-specific, they are shared between different
> targets of the same arch family (ARM and AArch64, MIPS32/MIPS64,
> multiple endianess, ...).
> Put them into
On 06/05/2019 00.56, Philippe Mathieu-Daudé wrote:
> Commit ce3cf70edaaf split the ISA device out of the PCI one,
> but forgot to remove the "hw/loader.h" header inclusion (the ISA
> device calls rom_add_vga()). Remove the now unused include.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
On 06/05/2019 00.47, Philippe Mathieu-Daudé wrote:
> Step in to maintain it, since I have some familiarity with
> the technology.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTAINERS | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index
On 26/04/2019 18.26, Stephen Checkoway wrote:
> Test the AMD command set for parallel flash chips. This test uses an
> ARM musicpal board with a pflash drive to test the following list of
> currently-supported commands.
> - Autoselect
> - CFI
> - Sector erase
> - Chip erase
> - Program
> - Unlock
On Thu, May 02, 2019 at 01:47:32PM +1000, Alexey Kardashevskiy wrote:
>
>
> On 02/05/2019 10:43, David Gibson wrote:
> > On Wed, May 01, 2019 at 07:48:48PM +1000, Alexey Kardashevskiy wrote:
> >>
> >>
> >> On 01/05/2019 15:35, Suraj Jitindar Singh wrote:
> >>> The monitor function dump-stack is
On 05/05/2019 20.32, Greg Kurz wrote:
> Hi Thomas,
>
> Thanks for the janitoring :)
>
> On Sun, 5 May 2019 16:45:27 +0200
> Thomas Huth wrote:
>
>> ... and remove the square brackets from "path" and "security_model",
>> since these parameters are not optional.
>>
>
> Well this is only true
On Sun, May 05, 2019 at 05:28:36PM +0200, Philippe Mathieu-Daudé wrote:
> Hi,
>
> This series is to properly do the fix sent by Artyom here:
> https://lists.gnu.org/archive/html/qemu-devel/2019-04/msg02264.html
>
> There is no RTC on the i82378, move it to the board code,
> set the base year
On Mon, May 06, 2019 at 11:48:03AM +1000, Suraj Jitindar Singh wrote:
> The ibm,purr and ibm,spurr device tree properties are used to indicate
> that the processor implements the Processor Utilisation of Resources
> Register (PURR) and Scaled Processor Utilisation of Resources Registers
> (SPURR),
On Sun, May 05, 2019 at 05:28:37PM +0200, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Certainly a good fix, but looks like there's places in
hw/timer/mc146818rtc.c itself and in vl.c which could also do with
this.
> ---
> hw/ppc/prep.c | 2 +-
> 1 file changed, 1
On 2019.05.05 21:51:02 -0400, Yan Zhao wrote:
> This feature implements the version attribute for Intel's vGPU mdev
> devices.
>
> version attribute is rw.
> It's used to check device compatibility for two mdev devices.
> version string format and length are private for vendor driver. vendor
>
On 2019/5/5 23:37, Peter Maydell wrote:
> On Sun, 5 May 2019 at 08:02, Xiang Zheng wrote:
>>
>> Currently we fill the memory space with two 64MB NOR images when
>> using persistent UEFI variables on virt board. Actually we only use
>> a very small(non-zero) part of the memory while the rest
This feature implements the version attribute for Intel's vGPU mdev
devices.
version attribute is rw.
It's used to check device compatibility for two mdev devices.
version string format and length are private for vendor driver. vendor
driver is able to define them freely.
For Intel vGPU of gen8
version attribute is used to check two mdev devices' compatibility.
The key point of this version attribute is that it's rw.
User space has no need to understand internal of device version and no
need to compare versions by itself.
Compared to reading version strings from both two mdev devices
This patchset introduces a version attribute under sysfs of VFIO Mediated
devices.
This version attribute is used to check whether two mdev devices are
compatible.
user space software can take advantage of this version attribute to
determine whether to launch live migration between two mdev
The ibm,purr and ibm,spurr device tree properties are used to indicate
that the processor implements the Processor Utilisation of Resources
Register (PURR) and Scaled Processor Utilisation of Resources Registers
(SPURR), respectively. Each property has a single value which represents
the level of
On Sun, May 05, 2019 at 10:06:02PM +0200, Philippe Mathieu-Daudé wrote:
>The pflash device is a child of TYPE_DEVICE, so it can implement
>the DeviceReset handler. Actually it has to implement it, else
>on machine reset it might stay in an incoherent state, as it has
>been reported in the buglink
On Sun, May 05, 2019 at 10:06:01PM +0200, Philippe Mathieu-Daudé wrote:
>The reset() code is used in various places, refactor it.
>
>Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Wei Yang
>---
> hw/block/pflash_cfi02.c | 25 +++--
> 1 file changed, 15 insertions(+), 10
On Sun, May 05, 2019 at 10:06:00PM +0200, Philippe Mathieu-Daudé wrote:
>The pflash device is a child of TYPE_DEVICE, so it can implement
>the DeviceReset handler. Actually it has to implement it, else
>on machine reset it might stay in an incoherent state, as it has
>been reported in the buglink
On Sun, May 05, 2019 at 10:05:59PM +0200, Philippe Mathieu-Daudé wrote:
>The reset() code is used in various places, refactor it.
>
>Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Wei Yang
>---
> hw/block/pflash_cfi01.c | 21 -
> 1 file changed, 12 insertions(+), 9
On Sun, May 05, 2019 at 10:05:58PM +0200, Philippe Mathieu-Daudé wrote:
>The 'CFI01' NOR flash was introduced in commit 29133e9a0fff, with
>timing modelled. One year later, the CFI02 model was introduced
>(commit 05ee37ebf630) based on the CFI01 model. As noted in the
>header, "It does not support
We already define SDCardModes/SDCardStates as enums. Declare
the mode/state as enums too, this make gdb debugging sessions
friendlier: instead of numbers, the mode/state name is displayed.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 6 +++---
1 file changed, 3 insertions(+), 3
Commit ce3cf70edaaf split the ISA device out of the PCI one,
but forgot to remove the "hw/loader.h" header inclusion (the ISA
device calls rom_add_vga()). Remove the now unused include.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/cirrus_vga.c | 1 -
1 file changed, 1 deletion(-)
diff
Step in to maintain it, since I have some familiarity with
the technology.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 66ddbda9c95..633f6315536 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@
The parallel NOR flash models don't have a specific maintainer and
default to the 'Block layer core' section.
Step in to maintain them.
The section still get covered by the Block layer team, but the idea
is to offload them.
The two devices are very similar (same technology), the difference
is
From: Stephen Checkoway
Most AMD commands only examine 11 bits of the address. This masks the
addresses used in the comparison to 11 bits. The exceptions are word or
sector addresses which use offset directly rather than the shifted
offset, boff.
Signed-off-by: Stephen Checkoway
Acked-by:
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 6 +++---
1 file
From: Stephen Checkoway
When erasing the chip, use the typical time specified in the CFI table
rather than arbitrarily selecting 5 seconds.
Since the currently unconfigurable value set in the table is 12, this
means a chip erase takes 4096 ms so this isn't a big change in behavior.
Using IEC binary prefixes in order to make the code more readable.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/pflash-cfi02-test.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c
index ff775618c02..3c37465499a
From: Stephen Checkoway
Test the AMD command set for parallel flash chips. This test uses an
ARM musicpal board with a pflash drive to test the following list of
currently-supported commands.
- Autoselect
- CFI
- Sector erase
- Chip erase
- Program
- Unlock bypass
- Reset
Signed-off-by: Stephen
The load/store API eases code review.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
Pull out all of the code to modify the status into simple helper
functions. Status handling becomes more complex once multiple
chips are interleaved to produce a single device.
No change in functionality is intended with this commit.
Signed-off-by: Stephen Checkoway
Message-Id:
The pflash_read()/pflash_write() can check the device endianess
via the pfl->be variable, so remove the 'int be' argument.
Since the big/little MemoryRegionOps are now identical, it is
pointless to declare them both. Unify them.
Signed-off-by: Stephen Checkoway
Message-Id:
Always compile the debug code to prevent format string to bitrot.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, use PRIx32]
The load/store API eases code review.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
No change in functionality is intended with this commit.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe
Extract the code block in a new function, remove a goto statement.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, remove the XXX tracing
Signed-off-by: Philippe Mathieu-Daudé
---
tests/pflash-cfi02-test.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c
index 40af1bb523e..ff775618c02 100644
--- a/tests/pflash-cfi02-test.c
+++
Hi,
While reviewing Stephen Checkoway's v4 "Implement missing AMD
pflash functionality" [*] I found it hard (for me) to digest,
so I took step by step notes. This series is the result of
those notes.
Regarding Stephen's series, this series only contains the
generic code movement and trivial
Richard Henderson writes:
> On 5/3/19 8:27 AM, Alex Bennée wrote:
>>
>> Yoshinori Sato writes:
>>
>>> Some RX peripheral using 8bit and 16bit registers.
>>> Added 8bit and 16bit APIs.
>>
>> Doesn't this mean the build breaks at some point? Features used by other
>> patches should be
Hi Richard.
I can maintain it
Sent from my cell phone, please ignore typos
On Sun, May 5, 2019, 8:57 AM Richard Henderson
wrote:
> On 5/4/19 1:36 AM, Sarah Harris wrote:
> > Signed-off-by: Sarah Harris
> ...
> >
> > +AVR
> > +M: Michael Rolnik
> > +S: Odd Fixes
> > +F: target-avr/
> > +F:
** Patch added: "disas.patch"
https://bugs.launchpad.net/qemu/+bug/1774830/+attachment/5261663/+files/disas.patch
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1774830
Title:
qemu monitor
The pflash device is a child of TYPE_DEVICE, so it can implement
the DeviceReset handler. Actually it has to implement it, else
on machine reset it might stay in an incoherent state, as it has
been reported in the buglink listed below.
Add the DeviceReset handler and remove its call from the
The reset() code is used in various places, refactor it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index
The reset() code is used in various places, refactor it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 6dc04f156a7..073cd14978f
The pflash device is a child of TYPE_DEVICE, so it can implement
the DeviceReset handler. Actually it has to implement it, else
on machine reset it might stay in an incoherent state, as it has
been reported in the buglink listed below.
Add the DeviceReset handler and remove its call from the
The 'CFI01' NOR flash was introduced in commit 29133e9a0fff, with
timing modelled. One year later, the CFI02 model was introduced
(commit 05ee37ebf630) based on the CFI01 model. As noted in the
header, "It does not support timings". 12 years later, we never
had to model the device timings. Time to
The pflash device lacks a reset() function.
When a machine is resetted, the flash might be in an
inconsistent state, leading to unexpected behavior:
https://bugzilla.redhat.com/show_bug.cgi?id=1678713
Resolve this issue by adding a DeviceReset() handler.
Both CFI01/CFI02 devices are fixed by
On 4/26/19 6:26 PM, Stephen Checkoway wrote:
> When erasing the chip, use the typical time specified in the CFI table
> rather than arbitrarily selecting 5 seconds.
>
> Since the currently unconfigurable value set in the table is 12, this
> means a chip erase takes 4096 ms so this isn't a big
Hi Thomas,
Thanks for the janitoring :)
On Sun, 5 May 2019 16:45:27 +0200
Thomas Huth wrote:
> ... and remove the square brackets from "path" and "security_model",
> since these parameters are not optional.
>
Well this is only true when fsdriver == local, but the other fs drivers,
ie. proxy
All these devices do not contain any target-specific code. While
most of them are arch-specific, they are shared between different
targets of the same arch family (ARM and AArch64, MIPS32/MIPS64,
multiple endianess, ...).
Put them into common-obj-y to compile them once for all targets.
On 5/4/19 5:05 AM, Paolo Bonzini wrote:
> Add endbr annotations before indirect branch targets. This lets QEMU enable
> IBT even for TCG-enabled builds.
>
> Signed-off-by: Paolo Bonzini
> ---
> Makefile.target | 2 ++
> configure | 9 +
>
On 5/4/19 5:05 AM, Paolo Bonzini wrote:
> + "bras %%r3, 1f\n"/* source PC will be after the BR */ \
> + "1: aghi %%r3, 12\n" /* 4 */ \
> + "stg %%r3, %[SCRATCH](%%r1)\n" /* 6 save switch-back PC */ \
> + "br %%r4\n"
On 5/4/19 5:05 AM, Paolo Bonzini wrote:
> The speedup is similar to x86, 120 ns vs 180 ns on an APM Mustang.
>
> Signed-off-by: Paolo Bonzini
> ---
> configure| 2 +-
> scripts/qemugdb/coroutine_asm.py | 6 -
> util/Makefile.objs | 2 ++
>
On 5/4/19 5:05 AM, Paolo Bonzini wrote:
> This backend is faster (100ns vs 150ns per switch on my laptop), but
> especially it will be possible to add CET support to it. Most of the
> code is actually not architecture specific.
>
> Signed-off-by: Paolo Bonzini
> ---
> configure
On Sat, 04 May 2019 00:22:44 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
>
> nit: typo in subject (serical->serial)
>
> > This module supported only non FIFO type.
> > Hardware manual.
> > https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
On Sat, 04 May 2019 01:11:48 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > Hello.
> > This patch series is added Renesas RX target emulation.
>
> I think the series is almost there - it's mostly just nits and clean
> build fixes to sort out now. If you run the branch through CI
On Sat, 04 May 2019 00:27:29 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > Some RX peripheral using 8bit and 16bit registers.
> > Added 8bit and 16bit APIs.
>
> Doesn't this mean the build breaks at some point? Features used by other
> patches should be introduced first so the
On Sat, 04 May 2019 03:43:23 +0900,
Richard Henderson wrote:
>
> On 5/2/19 7:33 AM, Yoshinori Sato wrote:
> > +/* conditional branch helper */
> > +static void rx_bcnd_main(DisasContext *ctx, int cd, int dst)
> > +{
> > +DisasCompare dc;
> > +TCGLabel *t, *done;
> > +
> > +switch (cd)
On Sat, 04 May 2019 01:06:44 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > Signed-off-by: Yoshinori Sato
> > ---
> > target/rx/gdbstub.c | 112
> >
> > target/rx/monitor.c | 38
> >
On Sat, 04 May 2019 00:38:38 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > rx62n - RX62N cpu.
> > rxqemu - QEMU virtual target.
> >
> > Signed-off-by: Yoshinori Sato
> > ---
> > include/hw/rx/rx.h| 7 ++
> > include/hw/rx/rx62n.h | 54
> > hw/rx/rx62n.c
On Sat, 04 May 2019 00:20:47 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > renesas_tmr: 8bit timer modules.
> > renesas_cmt: 16bit compare match timer modules.
> > This part use many renesas's CPU.
> > Hardware manual.
> >
On 03/05/2019 16.39, Alex Bennée wrote:
> This attempts to clean-up the output to better match the output of the
> rest of the QEMU check system. This includes:
>
> - formatting as " TESTiotest: nnn"
> - calculating time diff at the end
> - only dumping config on failure
>
>
On 5/5/19 8:49 AM, Mark Cave-Ayland wrote:
> Okay in that case I'll leave it as-is. So just to satisfy my curiosity here:
> is the
> problem here the mixing and matching of offsets and TCG globals, rather than
> the use
> of offsets as done for the VMX/VSX registers?
Correct.
r~
On 5/4/19 1:36 AM, Sarah Harris wrote:
> Signed-off-by: Sarah Harris
...
>
> +AVR
> +M: Michael Rolnik
> +S: Odd Fixes
> +F: target-avr/
> +F: hw/avr/
> +
This is not how things work. Michael wasn't up to maintaining the code 2 years
ago; that's why it was never committed.
You would need to
On 03/05/2019 18.15, Alex Bennée wrote:
>
> Thomas Huth writes:
>
>> On 03/05/2019 16.39, Alex Bennée wrote:
>>> This attempts to clean-up the output to better match the output of the
>>> rest of the QEMU check system. This includes:
>>>
>>> - formatting as " TESTiotest: nnn"
>>> -
On 05/05/2019 16:17, Richard Henderson wrote:
> On 5/5/19 3:20 AM, Mark Cave-Ayland wrote:
>>> The afrm argument is no longer used.
>>> This also means that e.g.
>>>
>>> VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
>>> VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
On 05/05/2019 15:34, Richard Henderson wrote:
> On 5/5/19 2:34 AM, Mark Cave-Ayland wrote:
EA = tcg_temp_new();\
-xt = tcg_const_tl(xT(ctx->opcode)); \
gen_set_access_type(ctx, ACCESS_INT);
On 5/4/19 1:36 AM, Sarah Harris wrote:
> This utility module builds a decision tree to decode instructions, starting
> from a human readable list of instruction bit patterns.
> Automatic tree generation will hopefully be more efficient and more
> maintainable than a hand-designed opcode parser.
On 05/05/2019 15:31, Richard Henderson wrote:
> On 5/5/19 2:27 AM, Mark Cave-Ayland wrote:
>> I've spent a bit of time today going through the functions and it seems that
>> all
>> functions which have an xt parameter, minus a couple of the TEST macros,
>> require the
>> result to be calculated
Paolo Bonzini writes:
> *** BLURB HERE ***
I assume there was going to be a bit more background here?
--
Alex Bennée
On Sun, 5 May 2019 at 08:02, Xiang Zheng wrote:
>
> Currently we fill the memory space with two 64MB NOR images when
> using persistent UEFI variables on virt board. Actually we only use
> a very small(non-zero) part of the memory while the rest significant
> large(zero) part of memory is wasted.
On Sat, 4 May 2019 at 06:26, Alistair Francis wrote:
> Ah, it seems like -device loader doesn't work, it looks like not
> setting the thumb register causes this core dump:
>
> qemu: fatal: Lockup: can't escalate 3 to HardFault (current priority -1)
>
> R00=2000 R01=0574 R02=200015d0
The MC146818 RTC was incorrectly added to the i82378 chipset in
commit a04ff940974a. In the next commit (506b7ddf8893) the PReP
machine use the i82378.
Since the MC146818 is specific to the PReP machine, move its use
there.
Fixes: a04ff940974a
Signed-off-by: Philippe Mathieu-Daudé
---
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/prep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index b7f459d4754..ebee3211480 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -601,7 +601,7 @@ static int
From: Artyom Tarasenko
AIX 5.1 expects the base year to be 1900. Adjust accordingly.
Signed-off-by: Artyom Tarasenko
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/prep.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index
Hi,
This series is to properly do the fix sent by Artyom here:
https://lists.gnu.org/archive/html/qemu-devel/2019-04/msg02264.html
There is no RTC on the i82378, move it to the board code,
set the base year there.
Regards,
Phil.
Artyom Tarasenko (1):
hw/ppc/40p: use 1900 as a base year
Hi Mark, Artyom.
On 5/5/19 12:46 PM, Mark Cave-Ayland wrote:
> On 04/05/2019 22:02, Artyom Tarasenko wrote:
>
>> AIX 5.1 expects the base year to be 1900. Adjust accordingly.
>>
>> Signed-off-by: Artyom Tarasenko
>> Reviewed-by: Hervé Poussineau
>> ---
>> hw/isa/i82378.c | 4 +++-
>> 1 file
On 5/5/19 3:20 AM, Mark Cave-Ayland wrote:
>> The afrm argument is no longer used.
>> This also means that e.g.
>>
>> VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
>> VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
>>
>> are redundant. Similarly with all of the other
Philippe Mathieu-Daudé writes:
> Install optional dependencies of QEMU to get better coverage.
>
> The following components are now enabled:
>
> $ ./configure
> ...
> Multipath support yes
> VNC SASL support yes
> RDMA support yes
> PVRDMA supportyes
> libiscsi support
Which version of QEMU did you use here? Does it still reproduce with the
latest version of QEMU?
** Changed in: qemu
Status: New => Incomplete
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On 5/5/19 2:57 AM, Mark Cave-Ayland wrote:
> For reference the culprits here is helper_xscvqpdp(). But again if you agree
> that it
> makes sense to create separate gen/helper functions then I can remove the
> opcode
> later on in the series.
Yes. Or indeed in a completely separate series.
Patchew URL: https://patchew.org/QEMU/20190430100802.15368-1-be...@igalia.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
** Changed in: qemu
Importance: Undecided => Wishlist
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https://bugs.launchpad.net/bugs/1583421
Title:
Please provide an option to print the default hardware configuration
as
On 5/5/19 2:52 AM, Mark Cave-Ayland wrote:
> Right, it looks like VSX_CMP is the culprit here. Am I right in thinking that
> it's
> best to remove the opc parameter from GEN_VSX_HELPER_X3 above, and then have a
> separate gen and helper function for just the VSX_CMP instructions?
> Presumably
... and remove the square brackets from "path" and "security_model",
since these parameters are not optional.
Buglink: https://bugs.launchpad.net/qemu/+bug/1581976
Signed-off-by: Thomas Huth
---
qemu-options.hx | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-options.hx
On 5/5/19 2:34 AM, Mark Cave-Ayland wrote:
>>> EA = tcg_temp_new();\
>>> -xt = tcg_const_tl(xT(ctx->opcode)); \
>>> gen_set_access_type(ctx, ACCESS_INT); \
>>> gen_addr_register(ctx, EA);
On 5/5/19 2:27 AM, Mark Cave-Ayland wrote:
> I've spent a bit of time today going through the functions and it seems that
> all
> functions which have an xt parameter, minus a couple of the TEST macros,
> require the
> result to be calculated in a local variable first.
>
> I think the best
IMX25, IMX7 and IMX6UL were still missing the Kconfig dependencies.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 2 --
hw/arm/Kconfig | 19 +++
2 files changed, 19
Dependencies have been determined with trial-and-error and by
looking at the musca.c source file.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
hw/arm/Kconfig | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
This cleans up most settings in default-configs/aarch64-softmmu.mak.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/aarch64-softmmu.mak | 4
hw/arm/Kconfig | 11
The PCI devices should be pulled in by default if PCI_DEVICES
is set, so there is no need anymore to enforce them in the configs
file.
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 8
1 file changed, 8 deletions(-)
diff --git
Add Kconfig dependencies for the NRF51 / microbit machine.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 3 +--
hw/arm/Kconfig | 6 ++
Add Kconfig dependencies for the emcraft-sf2 machine - we also
distinguish between the machine (CONFIG_EMCRAFT_SF2) and the SoC
(CONFIG_MSF2) now.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 3 +--
Dependencies have been determined with trial-and-error and by
looking at the xlnx-versal.c source file.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
hw/arm/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/Kconfig
Add Kconfig dependencies for the Sabrelite / iMX6 machine.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 4 +---
hw/arm/Kconfig | 9 +
hw/arm/Makefile.objs| 3 ++-
3
Add Kconfig dependencies for the DIGIC / canon-a1100 machine.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 2 +-
hw/arm/Kconfig | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
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