On Thu, Jul 25, 2019 at 09:30:30AM -0400, Jason Dillaman wrote:
> On Thu, Jul 25, 2019 at 4:13 AM Stefano Garzarella
> wrote:
> >
> > On Wed, Jul 24, 2019 at 01:48:42PM -0400, Jason Dillaman wrote:
> > > On Tue, Jul 23, 2019 at 3:13 AM Stefano Garzarella
> > > wrote:
> > > >
> > > > This patch
On Fri, Jul 26, 2019 at 10:40:44AM +0200, Cédric Le Goater wrote:
> On 26/07/2019 09:18, sathn...@linux.vnet.ibm.com wrote:
> > From: Satheesh Rajendran
> >
> > Add pseries linux boot console test
> >
> > $avocado --show=console run -t arch:ppc64le boot_linux_console.py
> > console: SLOF
> >
On Fri, Jul 26, 2019 at 10:37:35AM +0200, Cédric Le Goater wrote:
> On 26/07/2019 09:17, sathn...@linux.vnet.ibm.com wrote:
> > From: Satheesh Rajendran
> >
> > This series attempt to add support for avocado acceptance
> > test for powerpc and adds linux console boot test.
> >
> > avocado run
On Fri, 26 Jul 2019 at 08:37, Laurent Desnogues
wrote:
> On Fri, Jul 26, 2019 at 9:24 AM Alex Bennée wrote:
> > Peter Maydell writes:
> > > I wonder if we should put 0x51 (ascii 'Q') in the PARTNUM field;
> > > then if somebody really needs to distinguish QEMU from random
> > > other
On 26/07/2019 09:18, sathn...@linux.vnet.ibm.com wrote:
> From: Satheesh Rajendran
>
> Add pseries linux boot console test
>
> $avocado --show=console run -t arch:ppc64le boot_linux_console.py
> console: SLOF
> **
> console:
On 26/07/2019 09:17, sathn...@linux.vnet.ibm.com wrote:
> From: Satheesh Rajendran
>
> This series attempt to add support for avocado acceptance
> test for powerpc and adds linux console boot test.
>
> avocado run boot_linux_console.py:BootLinuxConsole.test_ppc64le_pseries
> version.py vnc.py
On 26/07/2019 09:18, sathn...@linux.vnet.ibm.com wrote:
> From: Satheesh Rajendran
>
> Current acceptance test will not run in powerpc Little endian
> environment due the arch name does not match the qemu binary path,
> let's handle it.
>
> Signed-off-by: Satheesh Rajendran
Reviewed-by:
This new FUSE_INIT field communicates the alignment constraint for
FUSE_SETUPMAPPING/FUSE_REMOVEMAPPING.
This feature will be implemented in the next commit.
Signed-off-by: Stefan Hajnoczi
---
contrib/virtiofsd/fuse_kernel.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff
Communicate the host page size to the FUSE client so that
FUSE_SETUPMAPPING/FUSE_REMOVEMAPPING requests are aware of our alignment
constraints.
Signed-off-by: Stefan Hajnoczi
---
contrib/virtiofsd/fuse_lowlevel.c | 8
1 file changed, 8 insertions(+)
diff --git
Signed-off-by: Stefan Hajnoczi
---
contrib/virtiofsd/fuse_kernel.h | 51 ++---
1 file changed, 34 insertions(+), 17 deletions(-)
diff --git a/contrib/virtiofsd/fuse_kernel.h b/contrib/virtiofsd/fuse_kernel.h
index 3186efbed6..7722e0ac23 100644
---
The client must know the server's alignment constraints for FUSE_SETUPMAPPING
and FUSE_REMOVEMAPPING. This is necessary because mmap(2)/munmap(2) have
alignment constraints and the guest may have a different page size from the
host. The new FUSE_INIT map_alignment field communicates this
On Fri, Jul 26, 2019 at 06:43:27AM +, tony.ngu...@bt.com wrote:
> Preparation for collapsing the two byte swaps, adjust_endianness and
> handle_bswap, along the I/O path.
>
> Target dependant attributes are conditionalize upon NEED_CPU_H.
>
> Signed-off-by: Tony Nguyen
ppc parts
Acked-by:
On Thu, Jul 25, 2019 at 01:36:38PM +0200, David Hildenbrand wrote:
> As ramblocks cannot get removed/readded while we are processing a bulk
> of inflation requests, there is no more need to track the page size
> in form of the number of subpages.
>
> Suggested-by: David Gibson
> Signed-off-by:
On Thu, Jul 25, 2019 at 09:15:08AM -0500, Shivaprasad G Bhat wrote:
> The logic is broken for multiple vcpu guests, also causing memory leak.
> The logic is in place to handle kvm not having KVM_CAP_PPC_IRQ_LEVEL,
> which is part of the kernel now since 2.6.37. Instead of fixing the
> leak, drop
On Thu, Jul 25, 2019 at 01:36:36PM +0200, David Hildenbrand wrote:
> Using the address of a RAMBlock to test for a matching pbp is not really
> safe. Instead, let's use the guest physical address of the base page
> along with the page size (via the number of subpages).
>
> Also, let's allocate
On 7/23/2019 10:59 PM, Igor Mammedov wrote:
On Tue, 16 Jul 2019 22:51:11 +0800
Tao Xu wrote:
In struct arm_boot_info, kernel_filename, initrd_filename and
kernel_cmdline are copied from from MachineState. This patch add
MachineState as a parameter into arm_load_dtb() and move the copy chunk
On 7/25/19 7:59 PM, Peter Maydell wrote:
> On Thu, 25 Jul 2019 at 18:02, Dr. David Alan Gilbert
> wrote:
>>
>> * Peter Maydell (peter.mayd...@linaro.org) wrote:
>>> gamepad_state::buttons is a pointer to an array of structs,
>>> not an array of structs, so should be declared in the vmstate
>>>
On 25/07/19 22:30, Michael S. Tsirkin wrote:
> On Thu, Jul 25, 2019 at 05:35:01PM +0200, Paolo Bonzini wrote:
>> On 25/07/19 16:46, Michael S. Tsirkin wrote:
>>> Actually, I think I have a better idea.
>>> At the moment we just get an exit on these reads and return all-ones.
>>> Yes, in theory
On 25.07.19 19:00, Eric Blake wrote:
> On 7/25/19 10:57 AM, Max Reitz wrote:
>> Several vmdk subformats do not work with iotest 126, so disable them.
>>
>> (twoGbMaxExtentSparse actually should work, but fixing that is a bit
>> difficult. The problem is that the vmdk descriptor file will contain
On Fri, Jul 26, 2019 at 9:24 AM Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Tue, 23 Jul 2019 at 12:33, Alex Bennée wrote:
[...]
> > /*
> > * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
> > * one and try to apply errata workarounds or use impdef
On Wed, Jul 24, 2019 at 07:47:45AM -0500, Shivaprasad G Bhat wrote:
> The KVM_CAP_PPC_IRQ_LEVEL is part of the kernel now since 2.6.37.
> Drop the redundant logic which is not excercised on new the kernels anymore.
> Exit with error on older kernels.
>
> Signed-off-by: Shivaprasad G Bhat
On Wed, Jul 24, 2019 at 11:32:00AM +0200, Cédric Le Goater wrote:
> On 23/07/2019 08:37, David Gibson wrote:
> > On Tue, Jul 23, 2019 at 08:00:27AM +0200, Cédric Le Goater wrote:
> >> On 23/07/2019 03:38, David Gibson wrote:
> >>> On Mon, Jul 22, 2019 at 08:23:47PM +0200, Cédric Le Goater wrote:
>
On Wed, Jul 24, 2019 at 08:25:04PM +0530, Amol Surati wrote:
> On Wed, Jul 24, 2019 at 06:57:30PM +1000, David Gibson wrote:
> > On Wed, Jul 24, 2019 at 09:11:54AM +0200, Cédric Le Goater wrote:
> > > On 24/07/2019 05:23, David Gibson wrote:
> > > > On Tue, Jul 23, 2019 at 11:01:38AM +0200, Cédric
On Wed, Jul 24, 2019 at 11:33:06AM +0200, Auger Eric wrote:
> Hi Yi, David,
>
> On 7/24/19 6:57 AM, Liu, Yi L wrote:
> >> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On
> >> Behalf
> >> Of David Gibson
> >> Sent: Tuesday, July 23, 2019 11:58 AM
> >> To: Liu, Yi L
> >>
On Wed, Jul 24, 2019 at 06:57:09PM +0200, Greg Kurz wrote:
> KVM on POWER9 doesn't use the XIVE VP space optimally. This currently
> limits the number of VMs we can start to 127. Starting with the 128th
> one, KVM fails to create the XIVE or the XICS-on-XIVE device and we
> go through the fallback
On Wed, Jul 24, 2019 at 10:50:17AM -0300, Eduardo Habkost wrote:
> On Wed, Jul 24, 2019 at 12:35:24PM +0200, Cornelia Huck wrote:
> > Add 4.2 machine types for arm/i440fx/q35/s390x/spapr.
> >
> > For i440fx and q35, unversioned cpu models are still translated
> > to -v1, as 0788a56bd1ae ("i386:
Peter Maydell writes:
> On Tue, 23 Jul 2019 at 12:33, Alex Bennée wrote:
>>
>> While most features are now detected by probing the ID_* registers
>> kernels can (and do) use MIDR_EL1 for working out of they have to
>> apply errata. This can trip up warnings in the kernel as it tries to
>>
From: Satheesh Rajendran
Current acceptance test will not run in powerpc Little endian
environment due the arch name does not match the qemu binary path,
let's handle it.
Signed-off-by: Satheesh Rajendran
---
tests/acceptance/avocado_qemu/__init__.py | 4
1 file changed, 4 insertions(+)
From: Satheesh Rajendran
Add pseries linux boot console test
$avocado --show=console run -t arch:ppc64le boot_linux_console.py
console: SLOF
**
console: QEMU Starting
console: Build Date = Jul 3 2019 12:26:14
console: FW
From: Satheesh Rajendran
This series attempt to add support for avocado acceptance
test for powerpc and adds linux console boot test.
avocado run boot_linux_console.py:BootLinuxConsole.test_ppc64le_pseries
version.py vnc.py
JOB ID : 918ed65e5e8bc1370c84c166a2c41936a700571e
JOB LOG:
This bit configures endianness of PCI MMIO devices. It is used by
Solaris and OpenBSD sunhme drivers.
Tested working on OpenBSD.
Unfortunately Solaris 10 had a unrelated keyboard issue blocking
testing... another inch towards Solaris 10 on SPARC64 =)
Signed-off-by: Tony Nguyen
---
Notice new attribute, byte swap, and force the transaction through the
memory slow path.
Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.
Signed-off-by: Tony Nguyen
---
accel/tcg/cputlb.c | 11 +++
Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.
Signed-off-by: Tony Nguyen
---
target/sparc/mmu_helper.c | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/sparc/mmu_helper.c
The fast path is taken when TLB_FLAGS_MASK is all zero.
TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path,
there are no other side effects.
Signed-off-by: Tony Nguyen
---
include/exec/cpu-all.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git
Now that MemOp has been pushed down into the memory API, we can
collapse the two byte swaps adjust_endianness and handle_bswap into
the former.
Collapsing byte swaps along the I/O path enables additional endian
inversion logic, e.g. SPARC64 Invert Endian TTE bit, with redundant
byte swaps
To convert interfaces of MemoryRegion access, MEMOP_SIZE and
SIZE_MEMOP no-op stubs were introduced to change syntax while keeping
the existing semantics.
Now with interfaces converted, we fill the stubs and use MemOp
semantics.
Signed-off-by: Tony Nguyen
---
include/exec/memop.h | 5 ++---
No-op SIZE_MEMOP macro allows us to later easily convert
memory_region_dispatch_{read|write} paramter "unsigned size" into a
size+sign+endianness encoded "MemOp op".
Being a no-op macro, this patch does not introduce any logical change.
Signed-off-by: Tony Nguyen
Reviewed-by: Philippe
No-op MEMOP_SIZE and SIZE_MEMOP macros allows us to later easily
convert memory_region_dispatch_{read|write} paramter "unsigned size"
into a size+sign+endianness encoded "MemOp op".
Being a no-op macro, this patch does not introduce any logical change.
Signed-off-by: Tony Nguyen
---
No-op SIZE_MEMOP macro allows us to later easily convert
memory_region_dispatch_{read|write} paramter "unsigned size" into a
size+sign+endianness encoded "MemOp op".
Being a no-op macro, this patch does not introduce any logical change.
Signed-off-by: Tony Nguyen
---
hw/vfio/pci-quirks.c | 5
No-op SIZE_MEMOP macro allows us to later easily convert
memory_region_dispatch_{read|write} paramter "unsigned size" into a
size+sign+endianness encoded "MemOp op".
Being a no-op macro, this patch does not introduce any logical change.
Signed-off-by: Tony Nguyen
---
hw/virtio/virtio-pci.c | 7
No-op SIZE_MEMOP macro allows us to later easily convert
memory_region_dispatch_{read|write} paramter "unsigned size" into a
size+sign+endianness encoded "MemOp op".
Being a no-op macro, this patch does not introduce any logical change.
Signed-off-by: Tony Nguyen
Reviewed-by: Philippe
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.
Target dependant attributes are conditionalize upon NEED_CPU_H.
Signed-off-by: Tony Nguyen
---
MAINTAINERS | 1 +
accel/tcg/cputlb.c | 2
No-op SIZE_MEMOP macro allows us to later easily convert
memory_region_dispatch_{read|write} paramter "unsigned size" into a
size+sign+endianness encoded "MemOp op".
Being a no-op macro, this patch does not introduce any logical change.
Signed-off-by: Tony Nguyen
---
hw/s390x/s390-pci-inst.c |
No-op SIZE_MEMOP macro allows us to later easily convert
memory_region_dispatch_{read|write} paramter "unsigned size" into a
size+sign+endianness encoded "MemOp op".
Being a no-op macro, this patch does not introduce any logical change.
Signed-off-by: Tony Nguyen
Reviewed-by: Philippe
Change memory_region_dispatch_{read|write} parameter "unsigned size"
to "MemOp op".
The endianness encoded in MemOp will enable the collapse of two byte
swaps, adjust_endianness and handle_bswap, along the I/O path.
Interfaces will be converted in two steps: first syntactically then
This patchset implements the IE (Invert Endian) bit in SPARCv9 MMU TTE.
It is an attempt of the instructions outlined by Richard Henderson to Mark
Cave-Ayland.
Tested with OpenBSD on sun4u. Solaris 10 is my actual goal, but unfortunately a
separate keyboard issue remains in the way.
On 01/11/17
On 7/26/19 8:03 AM, tony.ngu...@bt.com wrote:
> On 7/25/19 9:45 PM, Philippe Mathieu-Daudé wrote:
>>On 7/25/19 11:52 AM, tony.ngu...@bt.com wrote:
>>> Replacing size with size+sign+endianness (MemOp) will enable us to
>>> collapse the two byte swaps, adjust_endianness and handle_bswap, along
>>>
On 7/25/19 9:45 PM, Philippe Mathieu-Daudé wrote:
>On 7/25/19 11:52 AM, tony.ngu...@bt.com wrote:
>> Replacing size with size+sign+endianness (MemOp) will enable us to
>> collapse the two byte swaps, adjust_endianness and handle_bswap, along
>> the I/O path.
>>
>> While interfaces are converted,
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