On Fri, Aug 02, 2019 at 11:03:48AM +1000, Daniel Black wrote:
> On Thu, 1 Aug 2019 12:41:59 +0200
> Greg Kurz wrote:
>
> > On Thu, 1 Aug 2019 13:38:19 +1000
> > Daniel Black wrote:
> >
> > > Its not immediately obvious how cap-X=Y setting need to be applied
> > > to the command line so, for
On 8/3/19 3:22 PM, Jan Kiszka wrote:
> From: Jan Kiszka
>
> Allows to shutdown a foreground session via ctrl-c.
>
> Signed-off-by: Jan Kiszka
> ---
>
> Changes in v2:
> - adjust error message
>
> contrib/ivshmem-server/main.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
Patchew URL:
https://patchew.org/QEMU/20190803210803.5701-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v7 0/6] target/arm: Implement ARMv8.5-BTI for
linux-user
The kernel will return -EINVAL for bits set in the prot argument
that are unknown or invalid. Previously we were simply cropping
out the bits that we care about.
Introduce validate_prot_to_pageflags to perform this check in a
single place between the two syscalls. Differentiate between
the
This will build with older toolchains, without the upstream support
for -mbranch-protection. Such a toolchain will produce a warning
in such cases,
ld: warning: /tmp/ccyZt0kq.o: unsupported GNU_PROPERTY_TYPE (5) \
type: 0xc000
but the still places the note at the correct location in the
For aarch64, this includes the GNU_PROPERTY_AARCH64_FEATURE_1_BTI bit,
which indicates that the image should be mapped with guarded pages.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 94
1 file changed, 86 insertions(+), 8
Transform the prot bit to a qemu internal page bit, and save
it in the page tables.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 2 ++
linux-user/syscall_defs.h | 4
linux-user/mmap.c | 16
target/arm/translate-a64.c | 6 +++---
4 files
The kernel sets btype for the signal handler as if for a call.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index cd521ee42d..2c596a7088
Changes since v6:
* Rebased on the ARMv8.1-VHE patch set.
* Review from Dave Martin:
+ Remove PSTATE.BTYPE adjustment on syscall entry.
+ Rely on PT_GNU_PROPERTY to find the NT_GNU_PROPERTY_TYPE_0 note.
+ For the test case, add a linker script to create the PHDR.
Changes since v5:
These are all of the defines required to parse
GNU_PROPERTY_AARCH64_FEATURE_1_AND, copied from binutils.
Other missing defines related to other GNU program headers
and notes are elided for now.
Signed-off-by: Richard Henderson
---
include/elf.h | 22 ++
1 file changed, 22
From: Alex Bennée
According to ARM ARM we should only trap from EL0
when TCG or E2H are 0.
Signed-off-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/pauth_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/pauth_helper.c
From: Alex Bennée
While most features are now detected by probing the ID_* registers
kernels can (and do) use MIDR_EL1 for working out of they have to
apply errata. This can trip up warnings in the kernel as it tries to
work out if it should apply workarounds to features that don't
actually
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1901997a06..b1bb394c6d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -337,6 +337,7 @@ static void aarch64_max_initfn(Object
The comment that we don't support EL2 is somewhat out of date.
Update to include checks against HCR_EL2.TDZ.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c
The TGE bit routes all asynchronous exceptions to EL2.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 984a441cc4..a0969b78bf 100644
--- a/target/arm/helper.c
+++
When clearing HCR_E2H, this involves re-installing the EL1&0 asid.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 38 ++
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index
Use the correct sctlr for EL2&0 regime. Due to header ordering,
and where arm_mmu_idx is declared, we need to move the function
out of line. Use the function in many more places in order to
select the correct control.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v5: Use
Update to include checks against HCR_EL2.TID2.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 37c881baab..b8c45eb484 100644
---
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 16
target/arm/helper.c| 22 +-
target/arm/translate-a64.c | 3 +--
3 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
When TGE+E2H are both set, CPACR_EL1 is ignored.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 53 -
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d481716b97..2939454c8a
Return the indexes for the EL2&0 regime when the appropriate bits
are set within HCR_EL2. This happens for initial generation in
arm_mmu_idx, and reconstruction in core_to_arm_mmu_idx.
In order to make this reliable, we also need a bit in TBFLAGS.
Reviewed-by: Alex Bennée
Signed-off-by:
Prepare for, but do not yet implement, the EL2&0 regime
and the Secure EL2 regime.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 173 -
target/arm/internals.h | 44 +--
target/arm/helper.c| 60 --
This is part of a reorganization to the set of mmu_idx.
The EL3 regime only has a single stage translation, and
is always secure.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 2 +-
target/arm/helper.c| 18 +-
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a0969b78bf..d481716b97 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8936,6 +8936,7 @@ static inline bool
This is part of a reorganization to the set of mmu_idx.
The Secure regimes all have a single stage translation;
there is no point in pointing out that the idx is for stage1.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8
target/arm/internals.h | 4 ++--
This is part of a reorganization to the set of mmu_idx.
The non-secure EL2 regime only has a single stage translation;
there is no point in pointing out that the idx is for stage1.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 2 +-
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9d74162bbd..984a441cc4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@
This is part of a reorganization to the set of mmu_idx.
The EL1&0 regime is the only one that uses 2-stage translation.
Spelling out Stage avoids confusion with Secure.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 6 +++---
target/arm/helper.c
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 1 +
target/arm/cpu.h | 11 +
target/arm/cpu.c | 2 ++
target/arm/helper.c | 57
4 files changed, 66 insertions(+), 5 deletions(-)
diff --git
Several of the EL1/0 registers are redirected to the EL2 version when in
EL2 and HCR_EL2.E2H is set. Many of these registers have side effects.
Link together the two ARMCPRegInfo structures after they have been
properly instantiated. Install common dispatch routines to all of the
relevant
The EL1&0 regime is the only one that uses 2-stage translation.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 +--
target/arm/internals.h | 2 +-
target/arm/helper.c| 54 +++---
target/arm/translate-a64.c | 2 +-
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the EL1&0 regime.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8 +++
target/arm/internals.h | 4 ++--
target/arm/helper.c| 44 +++---
The virtual offset may be 0 depending on EL, E2H and TGE.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 40 +---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
Not all of the breakpoint types are supported, but those that
only examine contextidr are extended to support the new register.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 50 +--
target/arm/helper.c | 11
At the same time, add writefn to TTBR0_EL2 and TCR_EL2.
A later patch will update any ASID therein.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c
Rather than call to a separate function and re-compute any
parameters for the flush, simply use the correct flush
function directly.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 52 +
1 file changed, 24
No functional change, but unify code sequences.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 118 ++--
1 file changed, 37 insertions(+), 81 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 7 ---
target/arm/helper.c | 6 +-
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e6a76d14c6..e37008a4f7 100644
--- a/target/arm/cpu.h
+++
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 94c990cddb..e6a76d14c6 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3573,6 +3573,11 @@ static inline bool
This is less complex than the LPAE case, but still we now avoid the
flush in case it is only the PROCID field that is changing.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 34 --
1 file changed, 24 insertions(+), 10
In addition to providing the core with the current ASID, this minimizes
both the number of flushes due to non-changing ASID as well as the set
of mmu_idx that are affected by each flush.
In particular, updates to the secure mode registers flushes only the
relevant secure mode mmu_idx's, and
Although we can't do much with ASIDs except remember them, this
will allow cleanups within target/ that should make things clearer.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v2: Assert cpu_is_self; only flush idx w/ asid mismatch.
v3: Improve asid comment.
---
Since we have remembered ASIDs, we can further minimize flushing
by comparing against the one we want to flush.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 16
include/qom/cpu.h | 2 ++
accel/tcg/cputlb.c | 55
The VMID is the ASID for the 2nd stage page lookup.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index
About half of this patch set is cleanup of the qemu tlb handling
leading up to the actual implementation of VHE, and the biggest
piece of that: The EL2&0 translation regime.
Changes since v2:
* arm_mmu_idx was incomplete; test TGE+E2H not just E2H.
* arm_sctlr was incomplete; now uses
From: Jan Kiszka
Allows to shutdown a foreground session via ctrl-c.
Signed-off-by: Jan Kiszka
---
Changes in v2:
- adjust error message
contrib/ivshmem-server/main.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/contrib/ivshmem-server/main.c
Hi
On Fri, Aug 2, 2019 at 5:12 PM Tomáš Golembiovský wrote:
>
> Hi,
>
> I would like to add version reporting of Windows virtio drivers to qemu-ga.
> Obviously this is specific to Windows as for POSIX systems it corelates with
> the version of kernel. I would appreciate your ideas on a few
On 8/3/19 1:48 PM, Jan Kiszka wrote:
> From: Jan Kiszka
>
> Allows to shutdown a foreground session via ctrl-c.
>
> Signed-off-by: Jan Kiszka
> ---
> contrib/ivshmem-server/main.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/contrib/ivshmem-server/main.c
From: Jan Kiszka
Allows to shutdown a foreground session via ctrl-c.
Signed-off-by: Jan Kiszka
---
contrib/ivshmem-server/main.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/contrib/ivshmem-server/main.c b/contrib/ivshmem-server/main.c
index 197c79c57e..8a81cdb04c
From: Jan Kiszka
So far, the server leaves the posix shared memory object behind when
terminating, requiring the user to explicitly remove it in order to
start a new instance.
Signed-off-by: Jan Kiszka
---
contrib/ivshmem-server/ivshmem-server.c | 1 +
1 file changed, 1 insertion(+)
diff
>
> are available in the Git repository at:
>
> https://gitlab.com/philmd/qemu.git tags/edk2-next-20190803
>
> for you to fetch changes up to 177cd674d6203d3c1a98e170ea56c5a904ac4ce8:
>
> Makefile: remove DESTDIR from firmware
From: Olaf Hering
The resulting firmware files should only contain the runtime path.
Fixes commit 26ce90fde5c ("Makefile: install the edk2 firmware images
and their descriptors")
Signed-off-by: Olaf Hering
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by:
-next-20190803
for you to fetch changes up to 177cd674d6203d3c1a98e170ea56c5a904ac4ce8:
Makefile: remove DESTDIR from firmware file content (2019-08-03 09:52:32
+0200)
A harmless build-sys patch that fixes a regression affecting
Currently the make rules are wrongly using qemu/virt opensbi image
for sifive_u machine. Correct it.
Signed-off-by: Bin Meng
---
roms/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/roms/Makefile b/roms/Makefile
index dc70fb5..775c963 100644
--- a/roms/Makefile
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