Re: [Qemu-devel] [PATCH] Makefile: remove unused variables

Markus Armbruster writes: > Paolo Bonzini writes: > >> Signed-off-by: Paolo Bonzini >> --- >> Makefile | 4 >> 1 file changed, 4 deletions(-) >> >> diff --git a/Makefile b/Makefile >> index 73fbba0..7b0e2f4 100644 >> --- a/Makefile >> +++ b/Makefile >> @@ -429,10 +429,6 @@ dummy :=

Re: [Qemu-devel] [PATCH] Makefile: remove unused variables

Paolo Bonzini writes: > Signed-off-by: Paolo Bonzini > --- > Makefile | 4 > 1 file changed, 4 deletions(-) > > diff --git a/Makefile b/Makefile > index 73fbba0..7b0e2f4 100644 > --- a/Makefile > +++ b/Makefile > @@ -429,10 +429,6 @@ dummy := $(call unnest-vars,, \ >

Re: [Qemu-devel] [PATCH v2] make check-unit: use after free in test-opts-visitor

Andrey Shinkevich writes: > On 02/08/2019 14:34, Markus Armbruster wrote: >> Andrey Shinkevich writes: >> >>> In struct OptsVisitor, repeated_opts member points to a list in the >>> unprocessed_opts hash table after the list has been destroyed. A >>> subsequent call to visit_type_int()

[Qemu-devel] [PATCH 2/2] migration/postcopy: use QEMU_IS_ALIGNED to replace host_offset

Use QEMU_IS_ALIGNED for the check, it would be more consistent with other align calculations. Signed-off-by: Wei Yang --- migration/ram.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/migration/ram.c b/migration/ram.c index d86661a015..dfbf71c580 100644 ---

[Qemu-devel] [PATCH 0/2] migration/postcopy: simplify postcopy_chunk_hostpages_pass

When looking into function postcopy_chunk_hostpages_pass(), we could use alignment calculation to simplify it. Wei Yang (2): migration/postcopy: simplify calculation of run_start and fixup_start_addr migration/postcopy: use QEMU_IS_ALIGNED to replace host_offset migration/ram.c | 37

[Qemu-devel] [PATCH 1/2] migration/postcopy: simplify calculation of run_start and fixup_start_addr

The purpose of the calculation is to find a HostPage which is partially dirty. * fixup_start_addr points to the start of the HostPage to discard * run_start points to the next HostPage to check While in the middle stage, there would two cases for run_start: * aligned with HostPage means

[Qemu-devel] [PATCH v3] hmp: Remove migration capabilities from "info migrate"

With the growth of migration capabilities, it is not proper to display them in "info migrate". Users are recommended to use "info migrate_capabiltiies" to list them. Signed-off-by: Wei Yang Suggested-by: Dr. David Alan Gilbert --- v3: * remove un-used variable caps v2: * remove

Re: [Qemu-devel] [PATCH v2] hmp: Remove migration capabilities from "info migrate"

On Mon, Aug 05, 2019 at 12:12:25PM +0100, Dr. David Alan Gilbert wrote: >* Wei Yang (richardw.y...@linux.intel.com) wrote: >> With the growth of migration capabilities, it is not proper to display >> them in "info migrate". Users are recommended to use "info >> migrate_capabiltiies" to list them.

Re: [Qemu-devel] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place

On Mon, Aug 5, 2019 at 9:08 AM Bin Meng wrote: > > sifive_mmio_emulate() is currently only used in the sifive_e machine > codes. It can be helpful for other machines as well. > > Change it to an inline routine and move it to sifive_cpu.h, so that > other machines like sifive_u can use it. > >

Re: [Qemu-devel] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree

On Mon, Aug 5, 2019 at 9:13 AM Bin Meng wrote: > > This updates model and compatible strings to use the same strings > as used in the Linux kernel device tree (hifive-unleashed-a00.dts). > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > > --- > > hw/riscv/sifive_u.c | 5

Re: [Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree

On Mon, Aug 5, 2019 at 9:05 AM Bin Meng wrote: > > OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating > chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will > use this information to locate the serial node and probe its driver. > However currently we generate the

Re: [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses

On Mon, Aug 5, 2019 at 9:05 AM Bin Meng wrote: > > This updates the UART base address to match the hardware. > > Signed-off-by: Bin Meng Acked-by: Alistair Francis Alistair > --- > > hw/riscv/sifive_u.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git

Re: [Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming

On Mon, Aug 5, 2019 at 9:07 AM Bin Meng wrote: > > It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN > for hfxosccfg register programming. > > Signed-off-by: Bin Meng Acked-by: Alistair Francis Alistair > --- > > hw/riscv/sifive_e_prci.c | 2 +- > 1 file changed, 1

Re: [Qemu-devel] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header

On Mon, Aug 5, 2019 at 9:10 AM Bin Meng wrote: > > sifive_u machine does not use PRCI as of today. Remove the prci > header inclusion. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/riscv/sifive_u.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git

Re: [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string

On Mon, Aug 5, 2019 at 9:03 AM Bin Meng wrote: > > With heterogeneous harts config, the PLIC hart topology configuration > string are "M,MS,.." because of the monitor hart #0. > > Suggested-by: Fabien Chouteau > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > >

Re: [Qemu-devel] [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2

On Mon, Aug 5, 2019 at 9:42 AM Jonathan Behrens wrote: > > I'm not familiar with QEMU conventions on this, but would it make sense to > require having exactly 5 CPUs to match the real board? SMP can sometimes cause failures, so I think it makes some sense to keep the default low. Alistair > >

Re: [Qemu-devel] [PATCH v3 02/18] tests/boot-serial-test: add support for all the PowerNV machines

On Wed, Jul 31, 2019 at 04:12:17PM +0200, Cédric Le Goater wrote: > Use the machine names specifiying the CPU type, POWER8 and POWER9. > > Signed-off-by: Cédric Le Goater Applied to ppc-for-4.2, thanks. > --- > tests/boot-serial-test.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-)

Re: [Qemu-devel] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines

On Mon, Aug 5, 2019 at 9:07 AM Bin Meng wrote: > > Group SiFive E and U cpu type defines into one header file. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > include/hw/riscv/sifive_cpu.h | 31 +++ > include/hw/riscv/sifive_e.h |

Re: [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell

On Mon, Aug 5, 2019 at 9:04 AM Bin Meng wrote: > > Some of the properties only have 1 cell so we should use > qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells(). > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/riscv/sifive_u.c | 16 >

Re: [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property

On Mon, Aug 5, 2019 at 9:06 AM Bin Meng wrote: > > "linux,phandle" property is optional. Remove all instances in the > sifive_u and virt machine device tree. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/riscv/sifive_u.c | 3 --- > hw/riscv/virt.c | 3

[Qemu-devel] [PATCH v4 1/3] target/arm: Split out recompute_hflags et al

Create functions to compute the values of the a64 and a32 hflags, as well as one to compute the values that are shared between them. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Tested-by: Alex Bennée Reviewed-by: Alex Bennée

[Qemu-devel] [PATCH v4 3/3] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state

This is the payoff. >From perf record -g data of ubuntu 18 boot and shutdown: BEFORE: - 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr - 20.22% helper_lookup_tb_ptr + 10.05% tb_htable_lookup - 9.13% cpu_get_tb_cpu_state 3.20% aa64_va_parameters_both

[Qemu-devel] [PATCH v4 2/3] target/arm: Rebuild hflags at EL changes and MSR writes

Now setting, but not relying upon, env->hflags. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v2: Fixed partial conversion to assignment to env->hflags. --- linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c

[Qemu-devel] [PATCH v4 0/3] target/arm: Reduce overhead of cpu_get_tb_cpu_state

Version 3 was back in February: https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg06002.html Changes since v3: * Rebase. * Do not cache XSCALE_CPAR now that it overlaps VECSTRIDE. * Leave the new v7m bits as uncached. I haven't figured out all of the ways fpccr is modified.

Re: [Qemu-devel] [PATCH] util/hbitmap: fix unaligned reset

On 02/08/19 23:19, Max Reitz wrote: > > But I don’t know whether this patch is the best way forward still. I > think call hbitmap_reset() with unaligned boundaries generally calls for > trouble, as John has laid out. If mirror’s do_sync_target_write() is > the only offender right now, I’d

Re: [Qemu-devel] [PATCH] target/i386: Return 'indefinite integer value' for invalid SSE fp->int conversions

On 05/08/19 23:13, Richard Henderson wrote: > On 8/5/19 11:03 AM, Peter Maydell wrote: >> The x86 architecture requires that all conversions from floating >> point to integer which raise the 'invalid' exception (infinities of >> both signs, NaN, and all values which don't fit in the destination >>

Re: [Qemu-devel] [PATCH] tests/test-hbitmap: test next_zero and _next_dirty_area after truncate

Patchew URL: https://patchew.org/QEMU/20190805164652.42409-1-vsement...@virtuozzo.com/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ===

Re: [Qemu-devel] [PATCH 2/3] iotests: Enable -d for Python non-unittest tests

On 8/2/19 10:07 AM, Kevin Wolf wrote: > Am 01.08.2019 um 19:57 hat Max Reitz geschrieben: >> On 01.08.19 17:17, Kevin Wolf wrote: >>> The part of iotests.main() that is related to the implementation of the >>> debug option -d and enables QEMU and QMP logging is not only useful in >>> tests that

[Qemu-devel] [PATCH] Makefile: remove unused variables

Signed-off-by: Paolo Bonzini --- Makefile | 4 1 file changed, 4 deletions(-) diff --git a/Makefile b/Makefile index 73fbba0..7b0e2f4 100644 --- a/Makefile +++ b/Makefile @@ -429,10 +429,6 @@ dummy := $(call unnest-vars,, \ io-obj-y \ common-obj-y \

Re: [Qemu-devel] [PATCH] target/i386: Return 'indefinite integer value' for invalid SSE fp->int conversions

Patchew URL: https://patchew.org/QEMU/20190805180332.10185-1-peter.mayd...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PATCH] target/i386: Return 'indefinite integer value' for invalid SSE

Re: [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree

On 8/5/19 8:44 AM, Peter Maydell wrote: > On Fri, 26 Jul 2019 at 18:50, Richard Henderson > wrote: >> >> This unifies the implementation of the actual instructions >> for a32, t32, and t16. In order to make this happen, we >> need several preliminary cleanups. Most importantly to how >> we

Re: [Qemu-devel] [PATCH] target/i386: Return 'indefinite integer value' for invalid SSE fp->int conversions

On 8/5/19 11:03 AM, Peter Maydell wrote: > The x86 architecture requires that all conversions from floating > point to integer which raise the 'invalid' exception (infinities of > both signs, NaN, and all values which don't fit in the destination > integer) return what the x86 spec calls the

[Qemu-devel] [PATCH 2/3] tests/acceptance/avocado_qemu: add method to get supported machine types

add `get_machine_types()` to return list of supported machine types by the qemu binary. Signed-off-by: Balamuruhan S --- tests/acceptance/avocado_qemu/__init__.py | 6 ++ 1 file changed, 6 insertions(+) diff --git a/tests/acceptance/avocado_qemu/__init__.py

[Qemu-devel] [PATCH 1/3] tests/acceptance/migration: fix post migration check

assert `query-migrate` in target doesn't give migration status and test errors even if migration succeeds. In target: {'execute': 'query-migrate'} {"return": {}} Signed-off-by: Balamuruhan S --- tests/acceptance/migration.py | 1 - 1 file changed, 1 deletion(-) diff --git

[Qemu-devel] [PATCH 3/3] tests/acceptance/migration: test to migrate will all machine types

add migration test to query machine types supported by qemu binary and migrate vm will all supported type. Signed-off-by: Balamuruhan S --- tests/acceptance/migration.py | 26 ++ 1 file changed, 26 insertions(+) diff --git a/tests/acceptance/migration.py

[Qemu-devel] [PATCH 0/3] Add acceptance test for migration

Add new test for migration that bringup vm with different machine types and migrate it, introduce new API in avocado_qemu to query all the machine types supported by qemu. Test run: # avocado run migration.py JOB ID : ef54f57a073eb267d2347e32225f2adbe27969de JOB LOG:

[Qemu-devel] [Bug 1838946] Re: qemu 3.10 golang crash

Facing similar crash with the latest qemu, Can you give some pointers to debug further like backtrace/breakpoints or so $ ./qemu-4.1.0-rc3/arm-linux-user/qemu-arm --version qemu-arm version 4.0.93 Copyright (c) 2003-2019 Fabrice Bellard and the QEMU Project developers $

Re: [Qemu-devel] [PATCH] util/hbitmap: fix unaligned reset

On 8/5/19 5:48 AM, Vladimir Sementsov-Ogievskiy wrote: > 05.08.2019 12:26, Vladimir Sementsov-Ogievskiy wrote: >> 02.08.2019 22:21, John Snow wrote: >>> >>> >>> On 8/2/19 2:58 PM, Vladimir Sementsov-Ogievskiy wrote: hbitmap_reset is broken: it rounds up the requested region. It leads to

[Qemu-devel] ]Re: [BUG] gcov support appears to be broken - solved?

> > it shows very low coverage for our FP code (softfloat), while, in > > fact, we know that "make check" contains detailed tests on FP > > functionalities. But this is most likely a separate problem of a very > > different nature, perhaps the issue of separate git repo for FP tests > >

Re: [Qemu-devel] [BUG] gcov support appears to be broken - solved?

> > it shows very low coverage for our FP code (softfloat), while, in > > fact, we know that "make check" contains detailed tests on FP > > functionalities. But this is most likely a separate problem of a very > > different nature, perhaps the issue of separate git repo for FP tests > >

Re: [Qemu-devel] [BUG] gcov support appears to be broken - solved?

Aleksandar Markovic writes: >>> #./configure --enable-gcov >>> #make >>> #make check >>> #make coverage-report >>> >>> It seems that first three commands execute as expected. (For example, >>> there are plenty of files generated by "make check" that would've not >>> been generated if

[Qemu-devel] [PATCH] gdbstub: Fix handling of '!' packet with new infra

Since the '!' packet is not handled by the new infrastructure, gdb_handle_packet() would call run_cmd_parser() with a NULL cmd_parser value, which would lead to an unsupported packet ("$#00") being sent, which could confuse the gdb client. This also has a side-effect of speeding up the initial

Re: [Qemu-devel] [PATCH 3/4] virtiofsd: fix lo_destroy() resource leaks

* Dr. David Alan Gilbert (dgilb...@redhat.com) wrote: > * Stefan Hajnoczi (stefa...@redhat.com) wrote: > > Now that lo_destroy() is serialized we can call unref_inode() so that > > all inode resources are freed. > > > > Signed-off-by: Stefan Hajnoczi > > Reviewed-by: Dr. David Alan Gilbert >

Re: [Qemu-devel] [BUG] gcov support appears to be broken - solved?

>> #./configure --enable-gcov >> #make >> #make check >> #make coverage-report >> >> It seems that first three commands execute as expected. (For example, >> there are plenty of files generated by "make check" that would've not >> been generated if "enable-gcov" hadn't been chosen.) However, the

Re: [Qemu-devel] [PATCH v2 0/9] add failover feature for assigned network devices

On Mon, Aug 05, 2019 at 10:22:25AM -0400, Michael S. Tsirkin wrote: On Mon, Aug 05, 2019 at 03:12:15PM +0200, Jens Freimann wrote: On Fri, Aug 02, 2019 at 11:22:10AM -0400, Michael S. Tsirkin wrote: > On Fri, Aug 02, 2019 at 05:05:56PM +0200, Jens Freimann wrote: > > This is implementing the

Re: [Qemu-devel] [PULL 0/7] Block patches for 4.1.0-rc4

On Mon, 5 Aug 2019 at 19:21, Max Reitz wrote: > Would dropping the test patches make it better? :-) > > I am reasonably (i.e., rc4-levels of) confident that the patches don’t > break anything that wasn’t broken before. > > (I’m least confident about the test patches working for everyone and >

Re: [Qemu-devel] [PULL 0/7] Block patches for 4.1.0-rc4

On 05.08.19 20:05, Peter Maydell wrote: > On Mon, 5 Aug 2019 at 17:37, Max Reitz wrote: >> >> The following changes since commit 9bb68d34dda9be60335e73e65c8fb61bca035362: >> >> Merge remote-tracking branch >> 'remotes/philmd-gitlab/tags/edk2-next-20190803' into staging (2019-08-05 >> 11:05:36

[Qemu-devel] [Bug 1815423] Re: x86_64 TCG: Incorrect floating point cast to int.

https://patchew.org/QEMU/20190805180332.10185-1-peter.mayd...@linaro.org/ is a patch which fixes the C test case (and may also fix the node.js case, though I don't have a setup to test that). ** Changed in: qemu Status: Confirmed => In Progress -- You received this bug notification

Re: [Qemu-devel] [PATCH] target/i386: Return 'indefinite integer value' for invalid SSE fp->int conversions

Patchew URL: https://patchew.org/QEMU/20190805180332.10185-1-peter.mayd...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PATCH] target/i386: Return 'indefinite integer value' for invalid SSE

Re: [Qemu-devel] [PATCH] qtest: Rename qtest.c:qtest_init()

On 8/4/19 11:13 PM, Oleinik, Alexander wrote: > Both the qtest client, libqtest.c, and server, qtest.c, used the same > name for initialization functions which can cause confusion. > > Signed-off-by: Alexander Oleinik > --- > Thank you, Thomas Huth for the suggestion. Sometimes we use:

Re: [Qemu-devel] [PULL 0/7] Block patches for 4.1.0-rc4

On Mon, 5 Aug 2019 at 19:05, Peter Maydell wrote: > This is quite a lot of changes for rc4 -- how confident are > you about them ? I suppose 3 out of 4 commits are updating > the test suite... 3 out of 7, I meant :-) thanks -- PMM

Re: [Qemu-devel] [PULL 0/7] Block patches for 4.1.0-rc4

On Mon, 5 Aug 2019 at 17:37, Max Reitz wrote: > > The following changes since commit 9bb68d34dda9be60335e73e65c8fb61bca035362: > > Merge remote-tracking branch > 'remotes/philmd-gitlab/tags/edk2-next-20190803' into staging (2019-08-05 > 11:05:36 +0100) > > are available in the Git repository

[Qemu-devel] [PATCH] target/i386: Return 'indefinite integer value' for invalid SSE fp->int conversions

The x86 architecture requires that all conversions from floating point to integer which raise the 'invalid' exception (infinities of both signs, NaN, and all values which don't fit in the destination integer) return what the x86 spec calls the "indefinite integer value", which is 0x8000_ for

Re: [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes

On Fri, Aug 2, 2019 at 5:27 PM Bin Meng wrote: > > Some of the SoC IP block sizes are wrong. Correct them according > to the FE310 manual. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/riscv/sifive_e.c | 6 +++--- > 1 file changed, 3 insertions(+), 3

Re: [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names

On Wed, Jul 31, 2019 at 1:10 AM Chih-Min Chao wrote: > > > > On Wed, Jul 31, 2019 at 2:41 AM Alistair Francis wrote: >> >> On Mon, Jul 29, 2019 at 8:19 AM Chih-Min Chao >> wrote: >> > >> > >> > On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis >> > wrote: >> >> >> >> From: Atish Patra >> >>

Re: [Qemu-devel] [PATCH v2 4/8] hw/core: Add a config switch for the "register" device

On Wed, Jul 31, 2019 at 5:33 AM Paolo Bonzini wrote: > > On 31/07/19 13:44, Philippe Mathieu-Daudé wrote: > > What about naming it REGISTER_ARRAY or REGISTER_BLOCK? > > > > The API is: > > > > RegisterInfoArray *register_init_block32(...); > > > > Cc'ing Alistair for better name ideas :) > >

Re: [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios

On Fri, Aug 2, 2019 at 11:08 PM Bin Meng wrote: > > Currently the make rules are wrongly using qemu/virt opensbi image > for sifive_u machine. Correct it. > > Signed-off-by: Bin Meng Good catch. @Palmer Dabbelt can you take this for 4.1? Reviewed-by: Alistair Francis Alistair > > --- > >

[Qemu-devel] [PATCH v3] make check-unit: use after free in test-opts-visitor

In the struct OptsVisitor, the 'repeated_opts' member points to a list in the 'unprocessed_opts' hash table after the list has been destroyed. A subsequent call to visit_type_int() references the deleted list. It results in use-after-free issue reproduced by running the test case under the

Re: [Qemu-devel] [Qemu-riscv] [PATCH 26/28] riscv: hw: Update PLIC device tree

I was a little surprised to see the "riscv,max-priority" element removed, but there is no mention of it in the kernel documentation so I guess that max-priority=7 is now

Re: [Qemu-devel] [PULL 0/7] Block patches for 4.1.0-rc4

On 05.08.19 18:59, Vladimir Sementsov-Ogievskiy wrote: > 05.08.2019 19:37, Max Reitz wrote: >> The following changes since commit 9bb68d34dda9be60335e73e65c8fb61bca035362: >> >>Merge remote-tracking branch >> 'remotes/philmd-gitlab/tags/edk2-next-20190803' into staging (2019-08-05 >>

Re: [Qemu-devel] [PULL 0/7] Block patches for 4.1.0-rc4

05.08.2019 19:37, Max Reitz wrote: > The following changes since commit 9bb68d34dda9be60335e73e65c8fb61bca035362: > >Merge remote-tracking branch > 'remotes/philmd-gitlab/tags/edk2-next-20190803' into staging (2019-08-05 > 11:05:36 +0100) > > are available in the Git repository at: > >

[Qemu-devel] [PATCH] tests/test-hbitmap: test next_zero and _next_dirty_area after truncate

Test that hbitmap_next_zero and hbitmap_next_dirty_area can find things after old bitmap end. Signed-off-by: Vladimir Sementsov-Ogievskiy --- It's a follow-up for [PATCH for-4.1] util/hbitmap: update orig_size on truncate tests/test-hbitmap.c | 22 ++ 1 file changed,

Re: [Qemu-devel] [Qemu-riscv] [PATCH 09/28] riscv: sifive_u: Update UART base addresses

Reviewed-by: Jonathan Behrens On Mon, Aug 5, 2019 at 12:07 PM Bin Meng wrote: > This updates the UART base address to match the hardware. > > Signed-off-by: Bin Meng > --- > > hw/riscv/sifive_u.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git

Re: [Qemu-devel] [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2

I'm not familiar with QEMU conventions on this, but would it make sense to require having exactly 5 CPUs to match the real board? Jonathan On Mon, Aug 5, 2019 at 12:05 PM Bin Meng wrote: > It is not useful if we only have one management CPU. > > Signed-off-by: Bin Meng > --- > >

[Qemu-devel] [PULL 7/7] block/backup: disable copy_range for compressed backup

From: Vladimir Sementsov-Ogievskiy Enabled by default copy_range ignores compress option. It's definitely unexpected for user. It's broken since introduction of copy_range usage in backup in 9ded4a011496. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-id:

[Qemu-devel] [PULL 4/7] iotests: Test incremental backup after truncation

Signed-off-by: Max Reitz Message-id: 20190805152840.32190-1-mre...@redhat.com Signed-off-by: Max Reitz --- tests/qemu-iotests/124 | 38 ++ tests/qemu-iotests/124.out | 4 ++-- 2 files changed, 36 insertions(+), 6 deletions(-) diff --git

[Qemu-devel] [PULL 1/7] backup: Copy only dirty areas

The backup job must only copy areas that the copy_bitmap reports as dirty. This is always the case when using traditional non-offloading backup, because it copies each cluster separately. When offloading the copy operation, we sometimes copy more than one cluster at a time, but we only check

[Qemu-devel] [PULL 5/7] mirror: Only mirror granularity-aligned chunks

In write-blocking mode, all writes to the top node directly go to the target. We must only mirror chunks of data that are aligned to the job's granularity, because that is how the dirty bitmap works. Therefore, the request alignment for writes must be the job's granularity (in write-blocking

[Qemu-devel] [PULL 6/7] iotests: Test unaligned blocking mirror write

Signed-off-by: Max Reitz Message-id: 20190805113526.20319-1-mre...@redhat.com Reviewed-by: Vladimir Sementsov-Ogievskiy Signed-off-by: Max Reitz --- tests/qemu-iotests/151 | 25 + tests/qemu-iotests/151.out | 4 ++-- 2 files changed, 27 insertions(+), 2

[Qemu-devel] [PULL 2/7] iotests: Test backup job with two guest writes

Perform two guest writes to not yet backed up areas of an image, where the former touches an inner area of the latter. Before HEAD^, copy offloading broke this in two ways: (1) The target image differs from the reference image (what the source was when the backup started). (2) But you will

[Qemu-devel] [PULL 3/7] util/hbitmap: update orig_size on truncate

From: Vladimir Sementsov-Ogievskiy Without this, hbitmap_next_zero and hbitmap_next_dirty_area are broken after truncate. So, orig_size is broken since it's introduction in 76d570dc495c56bb. Fixes: 76d570dc495c56bb Signed-off-by: Vladimir Sementsov-Ogievskiy Message-id:

[Qemu-devel] [PULL 0/7] Block patches for 4.1.0-rc4

The following changes since commit 9bb68d34dda9be60335e73e65c8fb61bca035362: Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20190803' into staging (2019-08-05 11:05:36 +0100) are available in the Git repository at: https://github.com/XanClic/qemu.git

Re: [Qemu-devel] [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore

On 05/08/2019 18:10, Bin Meng wrote: > Thank you for the suggestion. A patch was created for this: > http://patchwork.ozlabs.org/patch/1142282/ Awesome, thank you Bin!

Re: [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate

On 8/5/19 8:32 AM, Peter Maydell wrote: >> -/* load a 32-bit value from a register and perform a 64-bit accumulate. */ >> -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) >> -{ >> -TCGv_i64 tmp; >> -TCGv_i32 tmp2; >> - >> -/* Load value and extend to 64 bits. */ >> -

Re: [Qemu-devel] [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore

Hi Fabien, On Tue, Jul 9, 2019 at 12:31 AM Fabien Chouteau wrote: > > Hi Bin, > > Thanks for this patch. > > I know I am very late to the game but I have a comment here. > > On 17/05/2019 17:51, Bin Meng wrote: > > +/* create PLIC hart topology configuration string */ > > +

[Qemu-devel] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree

This updates model and compatible strings to use the same strings as used in the Linux kernel device tree (hifive-unleashed-a00.dts). Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c

Re: [Qemu-devel] [PATCH 2/3] block/backup: disable copy_range for compressed backup

On 30.07.19 18:32, Vladimir Sementsov-Ogievskiy wrote: > Enabled by default copy_range ignores compress option. It's definitely > unexpected for user. > > It's broken since introduction of copy_range usage in backup in > 9ded4a011496. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- >

[Qemu-devel] [PATCH 27/28] riscv: virt: Change create_fdt() to return void

There is no need to return fdt at the end of create_fdt() because it's already saved in s->fdt. Other machines (sifive_u, spike) don't do it neither. Signed-off-by: Bin Meng --- hw/riscv/virt.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c

[Qemu-devel] [PATCH 26/28] riscv: hw: Update PLIC device tree

This removes "reg-names" and "riscv,max-priority" properties of the PLIC node from device tree, and updates its compatible string, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 4 +--- hw/riscv/virt.c | 4 +--- 2 files changed, 2

Re: [Qemu-devel] [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore

Hi Alistair, On Tue, Jul 16, 2019 at 5:33 AM Alistair Francis wrote: > > On Sat, Jul 13, 2019 at 8:23 PM Bin Meng wrote: > > > > Hi Fabien, > > > > On Tue, Jul 9, 2019 at 12:31 AM Fabien Chouteau > > wrote: > > > > > > Hi Bin, > > > > > > Thanks for this patch. > > > > > > I know I am very

[Qemu-devel] [PATCH 24/28] riscv: sifive_u: Fix broken GEM support

At present the GEM support in sifive_u machine is seriously broken. - The GEM block register base was set to a weird number (0x100900FC), which for no way could work with the cadence_gem model in QEMU. - The generated DT node for GEM has a "clocks-names" which is an invalid property name.

[Qemu-devel] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header

sifive_u machine does not use PRCI as of today. Remove the prci header inclusion. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9f05e09..dfcb525 100644 --- a/hw/riscv/sifive_u.c +++

[Qemu-devel] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree

The Linux kernel SiFive UART driver expects an aliases node to be present in the device tree, from which the driver extracts the port number from "serial#" in the aliases node. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[Qemu-devel] [PATCH 14/28] riscv: sifive: Implement PRCI model for FU540

This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng --- hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_prci.c | 163 +++

[Qemu-devel] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties

Now that we have added PRCI nodes, update existing UART and ethernet nodes to use PRCI as their clock sources, to keep in sync with the Linux kernel device tree. With above changes, the previously handcrafted "/soc/ethclk" node is no longer needed. Remove it. Signed-off-by: Bin Meng ---

[Qemu-devel] [PATCH 25/28] riscv: sifive_u: Support loading initramfs

The loading of initramfs is currently not supported on 'sifive_u'. Add the support to make '-initrd' command line parameter useful. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c

[Qemu-devel] [PATCH 05/28] riscv: hart: Support heterogeneous harts population

At present we only allow symmetric harts to be created. In order to support heterogeneous harts like SiFive FU540, update hart array's "cpu-type" property to allow cpu type to be set per hart, separated by delimiter ",". The frist cpu type before the delimiter is assigned to hart 0, and the second

[Qemu-devel] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place

sifive_mmio_emulate() is currently only used in the sifive_e machine codes. It can be helpful for other machines as well. Change it to an inline routine and move it to sifive_cpu.h, so that other machines like sifive_u can use it. Signed-off-by: Bin Meng --- hw/riscv/sifive_e.c | 8

[Qemu-devel] [PATCH 16/28] riscv: sifive_u: Add PRCI block to the SoC

Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 21 - include/hw/riscv/sifive_u.h | 1 + 2 files changed, 21 insertions(+), 1 deletion(-) diff

[Qemu-devel] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines

Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng --- include/hw/riscv/sifive_cpu.h | 31 +++ include/hw/riscv/sifive_e.h | 7 +-- include/hw/riscv/sifive_u.h | 7 +-- 3 files changed, 33 insertions(+), 12 deletions(-)

[Qemu-devel] [PATCH 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes

To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 23 +++ include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 25 insertions(+) diff

[Qemu-devel] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP

This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng --- hw/riscv/Makefile.objs | 1

[Qemu-devel] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size

Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng --- hw/riscv/sifive_e_prci.c | 2 +- include/hw/riscv/sifive_e_prci.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property

"linux,phandle" property is optional. Remove all instances in the sifive_u and virt machine device tree. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 3 --- hw/riscv/virt.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index

[Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming

It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN for hfxosccfg register programming. Signed-off-by: Bin Meng --- hw/riscv/sifive_e_prci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c index

[Qemu-devel] [PATCH 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. Signed-off-by: Bin Meng --- hw/riscv/Makefile.objs | 2 +- hw/riscv/sifive_e.c

[Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree

OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will use this information to locate the serial node and probe its driver. However currently we generate the UART node name as "/soc/uart@...", causing U-Boot fail to

[Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses

This updates the UART base address to match the hardware. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b235f29..9f05e09 100644 --- a/hw/riscv/sifive_u.c +++

[Qemu-devel] [PATCH 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine

As of today, the QEMU 'sifive_u' machine is a special target that does not boot the upstream OpenSBI/U-Boot firmware images built for the real SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform "qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced in the

[Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell

Some of the properties only have 1 cell so we should use qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells(). Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 16 hw/riscv/virt.c | 24 2 files changed, 20 insertions(+), 20 deletions(-)

  1   2   3   >