From: Nicholas Piggin
Move the i386 suspend_wakeup logic out of the fallback path, and into
the new ->wakeup method.
Signed-off-by: Nicholas Piggin
Message-Id: <20190722061752.22114-1-npig...@gmail.com>
Acked-by: Paolo Bonzini
Signed-off-by: David Gibson
---
hw/i386/pc.c | 8
vl.c
This patch documents the steps to use virtio pmem.
It also documents other useful information about
virtio pmem e.g use-case, comparison with Qemu NVDIMM
backend and current limitations.
Signed-off-by: Pankaj Gupta
---
v1->v2
- Fixes on text format and 'Guest Data persistence'
section -
From: Greg Kurz
PHBs already take care of clearing the MSIs from the bitmap during reset
or unplug. No need to do this globally from the machine code. Rather add
an assert to ensure that PHBs have acted as expected.
Signed-off-by: Greg Kurz
Message-Id:
From: "Paul A. Clarke"
The POWER8 and POWER9 User's Manuals specify the implementation
behavior for what the ISA leaves "undefined" behavior for the
xscvdpspn and xscvdpsp instructions. This patch corrects the QEMU
implementation to match the hardware implementation for that case.
ISA 3.0B has
From: Shivaprasad G Bhat
The logic is broken for multiple vcpu guests, also causing memory leak.
The logic is in place to handle kvm not having KVM_CAP_PPC_IRQ_LEVEL,
which is part of the kernel now since 2.6.37. Instead of fixing the
leak, drop the redundant logic which is not excercised on new
From: Cédric Le Goater
If the XIVE presenter can not find the NVT dispatched on any of the HW
threads, it can not deliver the interrupt. XIVE offers an escalation
mechanism to handle such scenarios and inform the hypervisor that an
action should be taken.
Escalation is configured by setting the
From: Cédric Le Goater
If backlog is activated ('b' bit) on the END, the pending priority of
a missed event is recorded in the IPB field of the NVT for a later
resend.
Signed-off-by: Cédric Le Goater
Message-Id: <20190718115420.19919-5-...@kaod.org>
Signed-off-by: David Gibson
---
From: "Paul A. Clarke"
helper_todouble() was not properly converting any denormalized 32 bit
float to 64 bit double.
Fix-suggested-by: Richard Henderson
Signed-off-by: Paul A. Clarke
v2:
- Splitting patch "ppc: Three floating point fixes"; this is just one part.
- Original suggested "fix"
From: Cédric Le Goater
When the 's' bit is set the escalation is said to be 'silent' or
'silent/gather'. In such configuration, the notification sequence is
skipped and only the escalation sequence is performed. This is used to
configure all the EQs of a vCPU to escalate on a single EQ which
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Message-Id: <20190718115420.19919-2-...@kaod.org>
Signed-off-by: David Gibson
---
include/hw/ppc/xive.h | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index
From: Michael Roth
This implements the H_TPM_COMM hypercall, which is used by an
Ultravisor to pass TPM commands directly to the host's TPM device, or
a TPM Resource Manager associated with the device.
This also introduces a new virtual device, spapr-tpm-proxy, which
is used to configure the
From: Cédric Le Goater
When a vCPU is not dispatched anymore on a HW thread, the Hypervisor
(KVM on Linux) invalidates the OS interrupt context of a vCPU with
this special command. It returns the OS CAM line value and resets the
VO bit.
Signed-off-by: Cédric Le Goater
Message-Id:
From: Alexey Kardashevskiy
DPDES stores a status of a doorbell message and if it is lost in
migration, the destination CPU won't receive it. This does not hit us
much as IPIs complete too quick to catch a pending one and even if
we missed one, broadcasts happen often enough to wake that CPU.
From: Shivaprasad G Bhat
Free all SpaprOptionVector local pointers after use.
Signed-off-by: Shivaprasad G Bhat
Message-Id:
<156335160761.82682.11912058325777251614.st...@lep8c.aus.stglabs.ibm.com>
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr_hcall.c | 2 ++
1 file
From: Paul Mackerras
Linux guest kernels have code which scans the string of characters
returned from the H_GET_TERM_CHAR hypercall and removes any \0
character which comes immediately after a \r character. This is to
work around a bug which was present in some ancient versions of
PowerVM. In
From: Nicholas Piggin
This does not do directed yielding and is not quite as strict as PAPR
specifies in terms of precise dispatch behaviour. This generally will
mean suboptimal performance, rather than guest misbehaviour. Linux
does not rely on exact dispatch behaviour.
Signed-off-by: Nicholas
From: Shivaprasad G Bhat
Leaking the drc_name while preparing the DT properties.
Fixing that.
Also, remove the const qualifier from spapr_drc_name().
Signed-off-by: Shivaprasad G Bhat
Message-Id:
<156335159028.82682.5404622104535818162.st...@lep8c.aus.stglabs.ibm.com>
Reviewed-by: Greg Kurz
From: Cédric Le Goater
Provide a better output of the XIVE END structures including the
escalation information and extend the PowerNV machine 'info pic'
command with a dump of the END EAS table used for escalations.
Signed-off-by: Cédric Le Goater
Message-Id:
From: "Paul A. Clarke"
helper_todouble() was not properly converting INFINITY from 32 bit
float to 64 bit double.
(Normalized operand conversion is unchanged, other than indentation.)
Signed-off-by: Paul A. Clarke
Message-Id: <1566242388-9244-1-git-send-email...@us.ibm.com>
Reviewed-by:
From: Nicholas Piggin
This has been useful to modify and test the Linux pseries suspend
code but it requires modification to the guest to call it (due to
being gated by other unimplemented features). It is not otherwise
used by Linux yet, but work is slowly progressing there.
Signed-off-by:
From: Nicholas Piggin
H_PROD is added, and H_CEDE is modified to test the prod bit
according to PAPR.
Signed-off-by: Nicholas Piggin
Message-Id: <20190718034214.14948-3-npig...@gmail.com>
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 1 +
From: Nicholas Piggin
Waking from suspend is not logically a machine reset on all machines,
particularly in the paravirtualized case rather than hardware
emulated. The ppc spapr machine for example just invokes hypervisor
to suspend, and expects that call to return with the machine in the
same
From: Greg Kurz
When the machine is reset, the MSI bitmap is cleared but the allocated
MSIs are not freed. Some operating systems, such as AIX, can detect the
previous configuration and assert.
Empty the MSI cache, this performs the needed cleanup.
Signed-off-by: Greg Kurz
Message-Id:
From: Shivaprasad G Bhat
Free the capability name string after setting
the capability.
Signed-off-by: Shivaprasad G Bhat
Message-Id:
<156335156198.82682.8756968724044750843.st...@lep8c.aus.stglabs.ibm.com>
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr_caps.c | 4 +++-
From: Stefan Brankovic
Optimization of altivec instructions vsl and vsr(Vector Shift Left/Rigt).
Perform shift operation (left and right respectively) on 128 bit value of
register vA by value specified in bits 125-127 of register vB. Lowest 3
bits in each byte element of register vB must be
From: Cédric Le Goater
If an IRQ is allocated and not configured, such as a MSI requested by
a PCI driver, it can be saved in its default state and possibly later
on restored using the same state. If not initially MASKED, KVM will
try to find a matching priority/target tuple for the interrupt
From: Nicholas Piggin
Implement cpu_exec_enter/exit on ppc which calls into new methods of
the same name in PPCVirtualHypervisorClass. These are used by spapr
to implement the splpar VPA dispatch counter initially.
Signed-off-by: Nicholas Piggin
Message-Id:
From: Stefan Brankovic
Adding simple macro that is calling tcg implementation of appropriate
instruction if altivec support is active.
Optimization of altivec instruction lvsl (Load Vector for Shift Left).
Place bytes sh:sh+15 of value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F
in destination
From: Stefan Brankovic
Optimize Altivec instruction vclzw (Vector Count Leading Zeros Word).
This instruction counts the number of leading zeros of each word element
in source register and places result in the appropriate word element of
destination register.
Counting is to be performed in four
From: Greg Kurz
When freeing MSIs, we need to:
- remove them from the machine's MSI bitmap
- remove them from the IC backend
- remove them from the PHB's MSI cache
This is currently open coded in two places in rtas_ibm_change_msi(),
and we're about to need this in spapr_phb_reset() as well.
From: Alex Bennée
The opcode decode tables aren't really part of the CPUPPCState but an
internal implementation detail for the translator. This can cause
problems with memcpy in cpu_copy as any table created during
ppc_cpu_realize get written over causing a memory leak. To avoid this
move the
From: Michael Roth
For now this only covers hcalls relating to TPM communication since
it's the only one particularly important from a QEMU perspective atm,
but others can be added here where it makes sense.
The full specification for all hcalls/ucalls will eventually be made
available in the
-20190821
for you to fetch changes up to c0e6616b6685ffdb4c5e091bc152e46e14703dd1:
ppc: Fix emulated single to double denormalized conversions (2019-08-21
17:17:39 +1000)
ppc patch queue for 2019-08-21
First ppc and spapr pull
From: Cédric Le Goater
When the 'u' bit is set the escalation is said to be 'unconditional'
which means that the ESe PQ bits are not used. Introduce a
xive_router_end_es_notify() routine to share code with the ESn
notification.
Signed-off-by: Cédric Le Goater
Message-Id:
From: Stefan Brankovic
Optimize Altivec instruction vclzd (Vector Count Leading Zeros Doubleword).
This instruction counts the number of leading zeros of each doubleword element
in source register and places result in the appropriate doubleword element of
destination register.
Using tcg-s count
From: Cornelia Huck
Add 4.2 machine types for arm/i440fx/q35/s390x/spapr.
For i440fx and q35, unversioned cpu models are still translated
to -v1, as 0788a56bd1ae ("i386: Make unversioned CPU models be
aliases") states this should only transition to the latest cpu
model version in 4.3 (or
From: Alexey Kardashevskiy
Currently we basically print IO address twice, fix this.
Fixes: 7e472264e9e2 ("PPC: spapr: iommu: rework traces")
Signed-off-by: Alexey Kardashevskiy
Message-Id: <20190812054202.125492-1-...@ozlabs.ru>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
From: Stefan Brankovic
Optimize altivec instruction vgbbd (Vector Gather Bits by Bytes by Doubleword)
All ith bits (i in range 1 to 8) of each byte of doubleword element in
source register are concatenated and placed into ith byte of appropriate
doubleword element in destination register.
From: Daniel Black
Its not immediately obvious how cap-X=Y setting need to be applied
to the command line so, for spapr capability error messages, this
has been clarified to:
appending -machine cap-X=Y
The wrong value messages have been left as is, as the user has found
the right location.
From: "Maxiwell S. Garcia"
Re-read the timebase before migrate was ported from x86 commit:
6053a86fe7bd: kvmclock: reduce kvmclock difference on migration
The clock move makes the guest knows about the paused time between
the stop and migrate commands. This is an issue in an already-paused
We've had the qemu and kernel KVM infrastructure to handle larger TCE
page sizes for a while, but forgot to update the defaults to actually
allow them. This turns that change on.
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 6 ++
hw/ppc/spapr_pci.c | 3 ++-
2 files changed, 8
On Mon, Aug 19, 2019 at 2:58 PM Alex Bennée wrote:
>
> This is intended to be a useful page we can link to in the banner of
> the IRC channel explaining the various support options someone might
> have.
>
> Signed-off-by: Alex Bennée
May be you should remove "bug reporting" and "contact"
Hi,
> Using the default QEMU config, we build SeaBIOS to use the TSC timer:
>
> builds/seabios-128k/.config:CONFIG_TSC_TIMER=y
> builds/seabios-256k/.config:CONFIG_TSC_TIMER=y
> Do we need a cpu with TSC support to run SeaBIOS?
Hmm. seabios uses pmtimer if available. isapc has no pmtimer
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